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This study explores cobalt–cerium (Co90Ce10) thin films deposited on silicon (Si) (100) and glass substrates via direct current (DC) magnetron sputtering, with thicknesses from 10 nanometer (nm) to 50 nm. Post-deposition annealing treatments, conducted from 100 °C to 300 °C, resulted in significant changes in surface roughness, surface energy, and magnetic domain size, demonstrating the potential to tune magnetic properties via thermal processing. The films exhibited hydrophilic behavior, with thinner films showing a stronger substrate effect, crucial for surface engineering in device fabrication. Increased film thickness reduced transmittance due to photon signal inhibition and light scattering, important for optimizing optical devices. Furthermore, the reduction in sheet resistance and resistivity with increasing thickness and heat treatment highlights the significance of these parameters in optimizing the electrical properties for practical applications. [ABSTRACT FROM AUTHOR]

Magnetic random access memory (MRAM) has been considered as a promising memory technology because of its attractive properties such as non-volatility, fast access, zero standby leakage and high density. Although integrating MRAM with complementary metal-oxide-semiconductor (CMOS) logic may incur extra manufacturing cost because of the hybrid magnetic-CMOS fabrication process, it is feasible and cost-effective to fabricate MRAM and CMOS logic separately and then integrate them using 3D stacking. In this work, we first studied the MRAM properties and built an MRAM cache model in terms of performance, energy and area. Using this model, we evaluated the impact of stacking MRAM caches atop microprocessor cores and compared MRAM against its static random access memory (SRAM) and dynamic random access memory (DRAM) counterparts. Our simulation result shows that MRAM stacking can provide competitive instruction-per-cycle (IPC) performance with a large reduction in power consumption. [ABSTRACT FROM AUTHOR]

Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues. [ABSTRACT FROM AUTHOR]

BiFeO 3 (BFO) is the only room temperature multiferroic material that has been extensively studied due to its multifunctional properties. BFO with a canted G-type antiferromagnetic (AFM) ordering exhibits strong exchange bias characteristics with NiFe which offers the potential to design and utilize devices working based on multiferroic features. In the past, it was known that the presence of 180 ∘ domain walls of BFO hinders a plausible exchange bias interaction. To understand the role of the strain-induced effects on such 180 ∘ domain walls and its effect on the exchange bias, NiFe, a soft ferromagnetic layer, was grown on the epitaxial BFO AFM layers. An approximately 80 nm BFO layer was grown epitaxially in both the tetragonal (001) phase on the LaAlO 3 (001) substrate and the rhombohedral (111) phase on the SrTiO 3 (111) substrate, with a thin (10 nm) layer of Ni 80 Fe 20 on top of it. An exchange bias of 510 Oe was observed in the tetragonal phase of BFO with a c / a ratio of 1.22, which is comparable with the exchange bias shown by the (111) oriented rhombohedral phase (360 Oe). Both the tetragonal (001) and rhombohedral (111) layers possess ferroelectric polarization normal to the sample surface and so the domain walls are mostly 180 ∘ oriented which is expected to have a minimum effect on the exchange bias. However, the weak strain-induced structural variants in the (111) oriented rhombohedral BFO and the monoclinic distortion present in the tetragonal BFO introduce non- 180 ∘ domain walls in the system. These variants arising due to the structural distortion are expected to play a key role in defining the ferroelectric domain wall nature, thereby exhibiting exchange bias characteristics. [ABSTRACT FROM AUTHOR]

We report on the fabrication of memory devices based on a nanoporous GeSbTe layer electrodeposited inbetween TiN and Ag electrodes. It is shown that devices can operate along two distinct electrical modes consisting of a volatile or a non-volatile resistance switching mode upon appropriate preconditioning procedures. Based on electrical measurements conducted in both switching modes and physical analysis performed on a device after electrical stress, resistance switching is attributed to the formation/dissolution of a conductive filament from the Ag electrode into the GST layer whereas the volatile/non-volatile resistance switching is attributed to the presence of an interface layer between the GST and the Ag top electrode. Due to their simple, low-cost and low-temperature fabrication procedure, these devices could be advantageously exploited in flexible electronic applications or embedded into the back-end of line CMOS technology. [ABSTRACT FROM AUTHOR]