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Current embedded systems are usually designed for data-dominated applications, but they have a tight energy and time budget. Scratch-pad memories are completely software-controlled memories with predictable behaviour and good performance and energy characteristics, thus they tend to become a standard feature in many embedded systems. However, their predictability is not helping if the application accesses its data dynamically, when the addresses of the accessed data depend on the application's input. In such cases, predetermining the scratch-pad content at design-time is not always possible as the compiler cannot predict the runtime input. Moreover, in this case, both data reuse and data placement in the scratch-pad are inefficient because chunks of data already stored cannot be efficiently reused and combined with the runtime accessed data blocks. State-of-the art techniques copy each new data block to the scratch-pad without considering whether portions of them are already in it. Such dynamic temporal locality cannot be predicted or exploited by the compiler. The authors here present a system architecture, strongly connected to the system's scratch-pad and the processor's compiler, which is able to efficiently exploit run-time data reuse in the scratch-pad by being capable of holding valuable information, such as the exact data contents of the scratch-pad at runtime, and using it to do all the necessary operations for placing each new data block in scratch-pad. It is fine tuned for applications with run-time reuse between rectangular data blocks. The application domain of the proposed architecture is multimedia applications with run-time reuse, certain applications with linked lists and multi-threaded applications. It operates in a time and energy-efficient manner when compared with existing scratch-pad architectures without the authors’ scratch-pad accelerator engine, showing its higher normalised performance and lower normalised energy consumption. Experimental results show up to 2.5 times performance increase compared with existing scratch-pad architectures and 5 times compared with cache architectures and energy decrease up to 1.9 and 3.9 times, respectively. [ABSTRACT FROM AUTHOR]

A new algorithm for producing message authenticating codes (MACs) was recently proposed by NIST. The MAC protects both a message's integrity—by ensuring that a different MAC will be produced if the message has changed-as well as its authenticity because only someone who knows the secret key could have generated a valid MAC. The proposed security scheme incorporates an FIPS approved and secure block cipher algorithm and was standardized by NIST in May, 2005. In this paper is presented the first efficient hardware implementation of the CMAC standard. [ABSTRACT FROM AUTHOR]

In this paper, a high-performance reconfigurable coarse-grain data-path, part of a hybrid reconfigurable platform, is introduced. The data-path consists of coarse-grain components that their flexibility and universality is shown to increase the system's performance due to significant reductions in latency. A methodology of unsophisticated but efficient algorithms for mapping computational intensive applications on the proposed data-path is also presented. Results on Digital Signal Processing and multimedia benchmarks show an average execution cycles reduction of 20%, combined with an area consumption decrease, when the proposed data-path is compared with a high-performance one. The average cycles reduction is even greater, 44%, when the comparison is held with a data-path that instantiates primitive computational resources on FPGA hardware. [ABSTRACT FROM AUTHOR]

In this paper, a methodology for the calculation of the undetectable double-faults in self-checking circuits with bit-sliced architecture is introduced. This methodology is based on a systematic exploration of the combinations of nodes where undetectable double-faults can arise. The self-checking n-bit 2-to-1 multiplexer coded by parity is used as a test vehicle for the presentation of the methodology and the number of the undetectable double-faults is given in a parametric way. The proposed methodology can easily be applied to other bit-sliced circuits. Common self-checking circuits are implemented for di9erent coding schemes and are using standard cell technology to verify the proposed methodology. The e9ectiveness of these implementations in fault detection as well as their requirements in hardware and power are also investigated. [ABSTRACT FROM AUTHOR]

A systematic methodology for energy dissipation reduction of multimedia applications realized on architectures based on embedded cores and application specific data memory organization is proposed. Performance and area are explicitly taken into account. The proposed methodology includes two major steps: A high-level code transformation step that reorganizes the original description of the target application. The second major step includes the determination of the processor, memory and bus organization of the system and is briefly described. Experimental results from several real-life demonstrators prove the impact of the high level step of the proposed methodology. [ABSTRACT FROM AUTHOR]

In this paper, the problem of scheduling the computation of partial products in transformational Digital Signal Processing (DSP) algorithms, aiming at the minimization of the switching activity in data and address buses, is addressed. The problem is stated as a hierarchical scheduling problem. Two different optimization algorithms, which are based on the Travelling Salesman Problem (TSP), are defined. The proposed optimization algorithms are independent on the target architecture and can be adapted to take into account it. Experimental results obtained from the application of the proposed algorithms in various widely used DSP transformations, like Discrete Cosine Transform (DCT) and Discrete Fourier Transform (DFT), show that significant switching activity savings in data and address buses can be achieved, resulting in corresponding power savings. In addition, the differences between the two proposed methods are underlined, providing envisage for their suitable selection for implementation, in particular transformational algorithms and architectures. [ABSTRACT FROM AUTHOR]

Presents information on a proposed algorithm for video coding and decoding and low-power image, which is based on vector quantization. Definition of vector quantization; Information on the estimation of power consumption; In-depth look at the proposed algorithm; Details on the results of experiments which were conducted with the application of the proposed algorithm.