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This paper is dedicated to a review of the international effort to map the future of nanoelectronics from materials to systems for the new electronics industry. The following sections are highlighted: the Roadmap structure with the international teams, the methodology and historical evolution, the various eras of scaling, the new ecosystems and computer industry, the evolving supply chain, the development of SoC and SiP, the advent of the Internet of Everything and the 5G communications, the dramatic increase of data centers, the power challenge, the technology fusion, heterogeneous and system integration, the emerging technologies, devices and computing architectures, and the main challenges for future applications. [ABSTRACT FROM AUTHOR]

Quantum computers are creating buzz from Silicon Valley to the halls of Congress. But the hardware has only been prototyped at small scale. Could applying the engineering processes used to scale up semiconductors also accelerate quantum computer development? [ABSTRACT FROM AUTHOR]

Rather than continue the expensive and time-consuming quest for transistor replacement, the authors argue that 3D chips coupled with new computer architectures can keep Moore’s law on its traditional scaling path. [ABSTRACT FROM PUBLISHER]

The combination of Moore's law and Dennard's scaling laws constituted the fundamental guidelines that provided the semiconductor industry with the foundation of a technically and economically viable roadmap until the end of the previous century. During this time, the transistor evolved from bipolar to PMOS to NMOS to CMOS. However, by the mid-1990s it was clear that fundamental physical limits of the MOS transistor were going to halt Dennard's scaling by 2005, at best. Eventually the power consumed by a single IC, under the relentless growth in the number of transistors and the continuous increase in operating frequency, pushed the IC temperature beyond reliable limits. Several new memory devices operating on completely new physics principles have been invented in the past 10 years and have already demonstrated that computing performance can be substantially improved by monolithically integrating several of these new heterogeneous memory layers on top of logic layers powered by a combination of CMOS and "new switch" transistors. This new phase, called 3D power scaling, will continue to support increase in transistor count at Moore's law pace well into the next decade. [ABSTRACT FROM PUBLISHER]

The IEEE Rebooting Computing Initiative, proposed in 2012, has launched a 15-year technology roadmap to address escalating computing-performance pressures: stalled device-physics advances coupled with big data demands, novel machine-learning problems, and complex software paradigms. Potential solutions range from new transistor technology to quantum computing. [ABSTRACT FROM PUBLISHER]

The article discusses efforts of the International Planning Working Group on Nanoelectronics (IPWGN) to identify research funding and program gaps in relation to nanoelectronics. Topics discussed include the most underfunded areas of nanoelectronics research in the U.S., Europe increasing its direct funding for micro and nanoelectronics research and the main focus of Japanese nanoelectronics research efforts, including photoresistance for handling extreme ultraviolet (EUV) light.

Focuses on the SIA's 1997 National Technology Roadmap for Semiconductors in the United States. Organizational structure; Metrics for the Overall Roadmap Technology Characteristics; Scaling issues; Research resources.

Features the 2003 edition of the reference document of the International Technology Roadmap for Semiconductors organization. Usability of the manual in various semiconductor firms; Availability of the manuals; Details on the Web site of the organization.