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The development of new bioelectronic platforms could provide exciting new opportunities for clinical analysis, environmental monitoring, and defense. Wearable adhesive tapes could adhere to skin to be in close contact with sweat that consists of many healthcare-related proteins, small molecules, and ions, and thus could function as unique platforms for the sensor construction. Here, we show for the first time the construction of wearable adhesive tape-based smart biosensing systems, and their determinations of lactate and glucose. The sensor is built by printing carbon graphite and Ag/AgCl inks on an adhesive tape to function as the working, reference, and counter electrodes, followed by the immobilization of lactate oxidase or glucose oxidase on the working electrode. The sensor shows a sensitive and broad detection range from micromolar to millimolar, and a quick measuring time of within 5 min for the determination of lactate or glucose. It is expected that these results could open up exciting new avenues for the development of novel wearable sensors, and toward advanced sweat-sensor applications. [ABSTRACT FROM AUTHOR]

A synergetic‐equalisation coding scheme for pulse‐amplitude modulation 4‐level (PAM4) is proposed, based on which a 216 Gb/s 9‐bit 8‐wire 4‐level (9B8W4L) transceiver is designed. According to the scheme, eight channels are grouped into four pairs based on the states for encoding. The two channels in pair transmit the same symbol in this unit interval (UI), and transmit different symbols in different pairs in the next UI. When decoding, the symbols in different channels are subtracted from and added with the others, following the grouping in the prior UI. From this, the first post‐cursor inter‐symbol interference is eliminated. Based on the proposed coding scheme, the PAM4 transceiver transmits 9‐bit data by eight channels, giving a channel utilisation of 112.5%. The improvement of channel utilisation reduces the Nyquist frequency for the same data rate, which is of great significance for reducing channel loss and power consumption. The 216 Gb/s 9B8W4L transceiver with 1‐tap feed‐forward equaliser achieves a bit error rate <10−12 through −20 dB channel loss at the Nyquist frequency of 12 GHz. [ABSTRACT FROM AUTHOR]

A hardware‐efficient slope‐error (SE) algorithm based four‐level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC‐768 JTOL mask by at least 0.35 UI at the bit error rate of 10−12. The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm2. [ABSTRACT FROM AUTHOR]

Electronic systems are prevalent in every field of human activity. Undergraduate education in the field of Circuits and Systems (CAS) at Peking University (PKU) is the focus of this paper. We highlight some of the practices at undergraduate level, which have been developed in an attempt to make CAS education more appealing and effective. Undergraduate students share the same curriculum in their first year of study to equip them with adequate depth and breadth in the electronic and computer engineering knowledge domains. The curriculum outlines are described with emphasis on CAS courses. A structured seminar class aims to create interactive learning space. Students are encouraged to practice in laboratories and in contests. The paper first reviews the key challenges faced. We then describe existing CAS education at PKU. We conclude with a look at future practices. The practices here are believed to ultimately contribute to technological advances and social prosperity. [ABSTRACT FROM PUBLISHER]

An analogue equaliser with a novel digitally tuned variable degeneration resistance is realised in a 65 nm CMOS technology. Implemented with three parallel resistance branches and one serial resistance branch to well fit the optimal conductance curve, the proposed variable degeneration resistance is exploited to achieve a wide boost range while significantly improving the linearity of the tuned boost factors compared with the equaliser with a traditional degeneration resistance structure. [ABSTRACT FROM AUTHOR]

A 65 nm CMOS 20 Gb/s transmitter with a low‐voltage differential signalling (LVDS) driver is presented. A novel power‐efficient pre‐emphasis method that eliminates power wasting in conventional pre‐emphasis is proposed. The input to the driver is pre‐coded so that the pre‐emphasis taps only inject current to the output nodes upon voltage level transition of the output signal. Current does not flow through the pre‐emphasis taps when there is no transition. Simulation results show that the proposed pre‐emphasis achieves the same output waveform and pre‐emphasis capability as the conventional approach while consuming less power. [ABSTRACT FROM AUTHOR]

A 40 Gbps 4‐tap 4‐level pulse amplitude modulation closed‐loop decision feedback equaliser (DFE) is proposed. The DFE adopts a novel high‐speed comparator to resolve the critical timing constraints of the first tap. The comparator decreases the slicing delay by shortening the gap between initial and target voltages. Compared with the existing closed‐loop DFE designs, the proposed scheme relieves timing constraints without complex clock distribution circuits and extra area. Simulations based on the RF‐MOS model verify that the delay of the comparator is improved by 32.8% and the output swing is increased by more than 2.8 times. The proposed DFE which can compensate −9.5 dB channel loss is designed in 55 nm CMOS technology. The power consumption is 67 mW from a 1.2 V supply and the circuit occupies an active area of 0.021 mm2, achieving 1.68 pJ/bit energy efficiency. [ABSTRACT FROM AUTHOR]

A novel 10 Gbit/s source‐series‐terminated (SST) transmitter in 65 nm CMOS technology is presented. Different from the conventional SST transmitter with the swing fixed to the supply voltage, the proposed transmitter, employing modified SST topology with switch‐based shunting legs, achieves tunable swing to provide suitable a output voltage for specific channel loss, resulting in higher power efficiency for the short and medium‐length channel. The proposed de‐emphasis scheme operates with the shunting path connecting the differential output pins instead of the voltage supply and the ground, which is more efficient than the conventional way. Fewer slices for de‐emphasis are needed along with less parasitic capacitance, and thus the power efficiency is improved. A full‐rate delay‐matching pre‐driver is used to avoid a complicated structure. Swing ranges from 50 mV to 1.2 V at a 1.2 V supply. The de‐emphasis could be tuned from 0 to −15.5 dB with power consumption dropping from 15.6 to 13.3 mW at the nominal swing of 1.2 V. [ABSTRACT FROM AUTHOR]

A deeper SSC estimator used as a CDR with a low power mechanism based on third‐order architecture is proposed to suppress the disadvantage of the conventional third‐order CDR happening at the switching points of SSC (spread spectrum clocking). For 10 Gbit/s data speed, the depth of its SSC tracking may be up to 10000ppm at 30 kHz which helps to reduce more EMI. [ABSTRACT FROM AUTHOR]