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Background: Acorus calamus, commonly known as Vacha holds a significant place in Ayurvedic medicine, addressing memory issues and acting as an anthelminthic. A. calamus rhizomes are known to be toxic due to presence of β-asarone and are used in Ayurvedic medicines only after elaborate processing known as Sodhana (detoxification or purification). As mentioned in Ayurvedic texts like Rasatrangini and Bhaisajya Ratnavali, Sodhana entails the transformation of potentially poisonous plants/substances into non-toxic forms. This study aims to uncover the chemical basis of this ancient detoxification process. Study design: The plant material was detoxified following the methods mentioned in the Ayurvedic Formulary of India. The plant material was boiled in gomutra (cow urine) and decanted. Subsequently, it was boiled with Spaeranthus indicus (Alambusa kwath) and then with Panchpallav kwath (a decoction of leaves from five different plants). The plant material so obtained was dried and subjected to swedana (steam distillation), dried again and extracted to obtain processed (detoxified) extract. Both the unprocessed and processed extracts were analyzed for secondary metabolites using HPLC, LCMS, and 1H NMR. Results: This study demonstrated that detoxification process resulted in morphological changes in rhizome, almost ten-fold reduction in extractive yield, reduced amount of major toxic component β-asarone and other toxic metabolites like asaronaldehyde, acorone, calamusin, acoraminol, acoramone, 1,2-dihydroxyasarone, asarotonide, propioveratrone, azulene and calamol in the extract, and isomerisation of β-asarone to α-asarone. Further the toxic metabolites were screened for genotoxicity by molecular docking. Conclusion: Our findings have identified the chemical basis of Ayurvedic detoxification process.

The control of networked power-electronics systems (PESs) using predictive switching sequences has been described in this paper. The switching-sequence-based control (SBC), first introduced in Mazumder and Acharya (2008), applies converter switching sequences to an optimization cost function to be satisfied under stability bounds. To evaluate the SBC control scalability and efficacy, the control strategy is implemented for centralized and distributed network architectures for different PES topologies. Given the two network architectures, dynamic and steady-state performances obtained using SBC are discussed using two different case illustrations: for a standalone and network of parallel hybrid active neutral-point-clamped (H-ANPC) inverters; and for a standalone and network of parallel differential-mode Ćuk rectifiers (DMCRs). Hence, the work highlights the feasibility of extending the SBC control application to PESs networks subject to communication constraints and latency dependencies.

Increasing the switching frequency of the power semiconductor devices (PSDs) reduces the size and cost of the passive elements, thereby positively affecting the power density of a high-frequency (HF) power electronic system (PES). To achieve a higher switching frequency of a PES, yet low switching losses, the speed of switching transitions of PSDs need to be increased. However, such fast transitions adversely affect PES performance in terms of electromagnetic interference (EMI) and device stress. Hence, a switching transition control (STC) scheme is developed to create optimality between switching PSDs with higher transitions yet maintaining safe levels of parasitic oscillations, that result from reducing the transition time of these devices. The switching transition control (STC) framework helps the HF PES achieve a target efficiency improvement by controlling the high di/dt and dv/dt regions of a PSD on the fly. Results are shown to validate that this improvement of efficiency is not feasible with a passive gate drive. An HF Ćuk PES using a Cree SiC MOSFET half-bridge module is fabricated for the testing purpose of the STC framework. The STC network is based on a simple switched resistor network, synthesized using high-speed GaN-FETs and built across two generations, Gen-1, and Gen-2. Practical operational issues of the STC network with fast switching GaN-FET in the Gen-1 board are analyzed and are overcome with design modification in Gen-2. The work has ramifications in meeting a system-level goal of an HF WBG PES, like a target efficiency increment, while not deteriorating the EMI performance and PSD stress levels that result due to parasitic oscillations in such PES.