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Failure risk must be tiny in high-integrity systems, such as those in cars, satellites and aircraft. Hence, safety measures must be deployed to avoid a single fault leading to a failure. Redundancy has been often used to address this concern, but it has been proven insufficient if a single fault can cause the same error in all redundant elements, which defeats the purpose of redundancy for error detection. Hence, to avoid this scenario, diversity is implemented along with redundancy, being lockstep execution the most popular diverse redundancy solution for computing cores. However, classic lockstep solutions have non-negligible limitations if implemented in hardware (e.g., half of the cores can only be used for redundant execution and are not even visible at user level), or in software (e.g., the software loop to enforce staggering is long and costs performance). This paper tackles the limitations of classic lockstep solutions by providing an extended analysis and evaluation of SafeDE, a Diversity Enforcement hardware module combining the short loop to enforce diversity of hardware solutions, and the non-intrusiveness of software solutions. Hence, cores can operate in lockstep mode efficiently or run independent tasks. In this paper, we present SafeDE and its rationale, its application to N-modular systems, its hardware and software integration, and an evaluation showing its performance and area efficiency, and its behavior in the presence of faults. [ABSTRACT FROM AUTHOR]

The space domain demands increased performance, reliable and easy to verify and validate platforms to match the requirements of highly autonomous missions and systems that need to undergo qualification and certification against safety guidelines, and be commercialized worldwide minimizing export restrictions. Unfortunately, commercial platforms either fail to match domainspecific requirements for space (e.g. safety requirements), are limited by US export regulations, or simply fail both sets of requirements. This paper introduces De-RISC, a novel HW/SW platform meeting space requirements for safety- and mission-critical applications by construction, with explicit support to ease performance validation and diagnosis, and based on the RISC-V instruction set architecture. The De-RISC platform, which builds upon fentISS' XtratuM hypervisor and a Cobham Gaisler (CG) NOEL-V based MPSoC, will reach commercial maturity in 2022, and will be assessed against a space use case. [ABSTRACT FROM AUTHOR]