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Graphene nanoribbons will be essential components in future graphene nanoelectronics (1). However, in typical nanoribbons produced from lithographically patterned exfoliated graphene, the charge carriers travel only about ten nanometres between scattering events, resulting in minimum sheet resistances of about one kilohm per square (2-5). Here we show that 40-nanometre-wide graphene nanoribbons epitaxially grown on silicon carbide (6,7) are single-channel room-temperature ballistic conductors on a length scale greater than ten micrometres, which is similar to the performance of metallic carbon nanotubes. This is equivalent to sheet resistances below 1 ohm per square, surpassing theoretical predictions for perfect graphene (8) by at least an order of magnitude. In neutral graphene ribbons, we show that transport is dominated by two modes. One is ballistic and temperature independent; the other is thermally activated. Transport is protected from back-scattering, possibly reflecting ground-state properties of neutral graphene. At room temperature, the resistance of both modes is found to increase abruptly at a particular length--the ballistic mode at 16 micrometres and the other at 160 nanometres. Our epitaxial graphene nanoribbons will be important not only in fundamental science, but also--because they can be readily produced in thousands--in advanced nanoelectronics, which can make use of their room-temperature ballistic transport properties., The energy spectrum of a graphene ribbon with length L and width W is approximately given by [E.sub.n,m] = ± [??]c* [square root of [(nπ/W).sup.2] + [(mπ/L).sup.2]] (1) where c* [...]

We report on the fabrication and characterization of fully vertical gallium nitride trench metal oxide semiconductor field effect transistors on native substrates with a metal-free gate first process and a chlorine-free trench etching method. Trenches were fabricated using sulfur hexafluoride and argon plasma etching in combination with alkaline wet etching posttreatment to create crystal oriented trenches along the a- and m-planes. Low pressure chemical vapor deposited silicon dioxide was used as gate dielectric with a poly-silicon gate contact. The metal-free gate structure was separated by a silicon dioxide passivation from any subsequent metal containing contact formation processing steps. The breakdown robustness of the gate structure was examined in the forward direction and no temperature dependence was observed up to 450 K. Fabricated trench MOSFETs showed only small hysteresis effects during transfer characterization but a positive threshold shift was observed. An inversion channel carrier field effect mobility of ≈ 10 cm 2 /V s was extracted. The area specific on resistance was calculated to be 5.8 m Ω cm 2. Results for devices with differently oriented trenches were comparable and no significant performance difference was observed. [ABSTRACT FROM AUTHOR]

Planar metal-insulator-semiconductor capacitors are fabricated on native gallium nitride substrates with different gate dielectrics, namely, silicon dioxide, silicon nitride, and aluminum oxide. The leakage current was measured to determine their robustness regarding electrical breakdown. Hysteresis effects were evaluated for the different gate dielectrics and for the substrate and the epitaxial surface. A gate-first process with a gate contact made from poly-crystalline silicon was compared to a gate-last process with a sputtered aluminum gate. The former showed superior robustness against electrical breakdown with a dielectric breakdown field strength of ≈ 9 MV/cm, which was found to be mostly independent of temperature in the range of 250–450 K. Furthermore, gate oxide traps were estimated by means of stress/recovery gate current transient measurements to confirm field strength limits for high lifetime requirements. Based on the various measurements, silicon dioxide emerged as the best choice regarding breakdown robustness and hysteresis effects. A limit for the dielectric field strength of 3–4 MV/cm is proposed to avoid short- and long-term damage of the dielectric layer. [ABSTRACT FROM AUTHOR]

During the last few years and with the commercialization of the gallium nitride based high electron mobility transistor, research effort on gallium nitride has been strongly increasing. Besides activities regarding lateral devices like the gallium nitride high electron mobility transistor, progress in the growth of native gallium nitride substrates encourages the development of vertical devices. In particular, for power electronics above 600 V, vertical architecture shows superior performance compared to lateral devices. This makes the vertical approach interesting for the use in traction inverters in the rising market of e-mobility. A key aspect in the fabrication of most vertical devices is the formation and optimization of trenches in the semiconductor. In this work, the fabrication of 1.5– 2 μ m deep, crystal plane oriented trenches in gallium nitride with lateral dimension as small as 1 μ m is demonstrated. The trenches were produced by means of plasma etching based on sulfur hexafluoride and argon as well as a subsequent wet etching step in tetramethylammonium hydroxide and potassium hydroxide. By accurately aligning the trenches along the [ 1 ¯ 010 ] - and [ 1 2 ¯ 10 ] -directions, the authors were able to evaluate the wet etching behavior of the respective crystal planes and achieved smooth vertical sidewalls. [ABSTRACT FROM AUTHOR]

Epitaxially grown sidewall graphene nanoribbons show a robust quantum conductance of e2/h. By means of in-situ transport measurements with a nanoprobe system, we realized invasive and non-invasive 4-point-probe configurations. The invasiveness correlates with the contact resistance of the voltage probes. In particular, we achieved now non-invasive voltage probes revealing an almost zero resistance in a collinear 4 point-probe measurement. This proofs the ballistic nature of our epitaxially grown sidewall nanoribbons on SiC(0001) mesa structures. [ABSTRACT FROM AUTHOR]

Structured Silicon Carbide was proposed to be an ideal template for the production of arrays of edge specific graphene nanoribbons (GNRs), which could be used as a base material for graphene transistors. We prepared periodic arrays of nanoscaled stripe-mesas on SiC surfaces using electron beam lithography and reactive ion etching. Subsequent epitaxial graphene growth by annealing is differentiated between the basal-plane mesas and the faceting stripe walls as monitored by means of atomic force microscopy (AFM). Microscopic low energy electron diffraction (μ-LEED) revealed that the graphene ribbons on the facetted mesa side walls grow in epitaxial relation to the basal-plane graphene with an armchair orientation at the facet edges. The π-band system of the ribbons exhibits linear bands with a Dirac like shape corresponding to monolayer graphene as identified by angle-resolved photoemission spectroscopy (ARPES). [ABSTRACT FROM AUTHOR]

We realize nanometer size constrictions in ballistic graphene nanoribbons grown on sidewalls of SiC mesa structures. The high quality of our devices allows the observation of a number of electronic quantum interference phenomena. The transmissions of Fabry-Perot-like resonances are probed by in situ transport measurements at various temperatures. The energies of the resonances are determined by the size of the constrictions, which can be controlled precisely using STM lithography. The temperature and size dependence of the measured conductances are in quantitative agreement with tight-binding calculations. The fact that these interference effects are visible even at room temperature makes the reported devices attractive as building blocks for future carbon based electronics. [ABSTRACT FROM AUTHOR]

The realization of ballistic graphene pn-junctions is an essential task in order to study Klein tunneling phenomena. Here we show that intercalation of Ge under the buffer layer of pre-structured SiC-samples succeeds to make truly nano-scaled pn-junctions. By means of local tunneling spectroscopy the junction width is found to be as narrow as 5 nm which is a hundred times smaller compared to electrically gated structures. The ballistic transmission across the junction is directly proven by systematic transport measurements with a 4-tip STM. Various npn- and pnp-junctions are studied with respect to the barrier length. The pn-junctions are shown to act as polarizer and analyzer with the second junction becoming transparent in case of a fully ballistic barrier. This can be attributed to the almost full suppression of electron transmission through the junction away from normal incidence. [ABSTRACT FROM AUTHOR]

The electrical transport properties of epitaxial graphene layers are correlated with the SiC surface morphology. In this study we show by atomic force microscopy and Raman measurements that the surface morphology and the structure of the epitaxial graphene layers change significantly when different pretreatment procedures are applied to nearly on-axis 6H-SiC(0 0 0 1) substrates. It turns out that the often used hydrogen etching of the substrate is responsible for undesirable high macro-steps evolving during graphene growth. A more advantageous type of sub-nanometer stepped graphene layers is obtained with a new method: a high-temperature conditioning of the SiC surface in argon atmosphere. The results can be explained by the observed graphene buffer layer domains after the conditioning process which suppress giant step bunching and graphene step flow growth. The superior electronic quality is demonstrated by a less extrinsic resistance anisotropy obtained in nano-probe transport experiments and by the excellent quantization of the Hall resistance in low-temperature magneto-transport measurements. The quantum Hall resistance agrees with the nominal value (half of the von Klitzing constant) within a standard deviation of 4.5 × 10(-9) which qualifies this method for the fabrication of electrical quantum standards.