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This study introduces a pioneering design for leaky integrate-and-fire (LIF) neurons by integrating memristor devices with CMOS transistors, thereby forming an innovative hybrid CMOS/memristor neuron circuit. Employing Pt/TaOx/Ta as the memristor device, the proposed model was meticulously implemented and rigorously evaluated using the Cadence Virtuoso simulation environment. The simulation outcomes affirm the effective functionality of the design, marking a significant advancement in hybrid circuit engineering. Notably, the proposed neuron circuit exhibits a compact footprint, attributed to the efficient utilization of hybrid CMOS/memristor gates. This characteristic is poised to address the critical challenge of scaling in current neuromorphic systems, offering a viable pathway to substantially augment density and cater to the escalating demands of advanced computational architectures. The findings of this research hold promising implications for enhancing the efficiency and scalability of neuromorphic systems, setting a new benchmark for future developments in this domain. [ABSTRACT FROM AUTHOR]

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Neuromorphic computing research is being actively pursued to address the challenges posed by the need for energy-efficient processing of big data. One of the promising approaches to tackle the challenges is the hardware implementation of spiking neural networks (SNNs) with bio-plausible learning rules. Numerous research works have been done to implement the SNN hardware with different synaptic plasticity rules to emulate human brain operations. While a standard spike-timing-dependent-plasticity (STDP) rule is emulated in many SNN hardware, the various STDP rules found in the biological brain have rarely been implemented in hardware. This study proposes a CMOS-memristor hybrid synapse circuit for the hardware implementation of a Ca ion-based plasticity model to emulate the various STDP curves. The memristor was adopted as a memory device in the CMOS synapse circuit because memristors have been identified as promising candidates for analog non-volatile memory devices in terms of energy efficiency and scalability. The circuit design was divided into four sub-blocks based on biological behavior, exploiting the non-volatile and analog state properties of memristors. The circuit was designed to vary weights using an H-bridge circuit structure and PWM modulation. The various STDP curves have been emulated in one CMOS-memristor hybrid circuit, and furthermore a simple neural network operation was demonstrated for associative learning such as Pavlovian conditioning. The proposed circuit is expected to facilitate large-scale operations for neuromorphic computing through its scale-up. [ABSTRACT FROM AUTHOR]

Gate-tunable transmons (gatemons) employing semiconductor Josephson junctions have recently emerged as building blocks for hybrid quantum circuits. In this study, we present a gatemon fabricated in planar Germanium. We induce superconductivity in a two-dimensional hole gas by evaporating aluminum atop a thin spacer, which separates the superconductor from the Ge quantum well. The Josephson junction is then integrated into an Xmon circuit and capacitively coupled to a transmission line resonator. We showcase the qubit tunability in a broad frequency range with resonator and two-tone spectroscopy. Time-domain characterizations reveal energy relaxation and coherence times up to 75 ns. Our results, combined with the recent advances in the spin qubit field, pave the way towards novel hybrid and protected qubits in a group IV, CMOS-compatible material. A gatemon is a transmon-type superconducting qubit made using a hybrid superconductor-semiconductor approach enabling tunability with electric gates. Here the authors demonstrate a gatemon qubit in planar germanium, which is anticipated to have various advantages. [ABSTRACT FROM AUTHOR]

We investigate a hybrid device allowing a photon–phonon coupling of a transmission line radiation (TLR) and a nanoeletromechanical system (NEMS), mediated by a superconducting qubit population imbalance. We demonstrate the derivation of an effective Hamiltonian for the strongly dispersive regime for this system. The qubit works as a quantum switch, allowing a conditioned transfer of excitations between the TLR and NEMS. We show that this regime allows the system to be employed for signal processing and force estimation. Additionally, we explore the ability of the quantum switch to generate non-classical states. [ABSTRACT FROM AUTHOR]

Lithium-ion batteries, as the main energy storage component of electric vehicles (EVs), play a crucial role in ensuring the safe and reliable operation of the battery systems through monitoring their state of health (SOH). However, temperature variations and battery aging have significant impacts on the internal parameters of lithium-ion batteries, and these changes directly correlate with the accuracy of battery SOH estimation. To address these issues, this paper proposes an estimation method for lithium-ion battery SOH that considers the impact of temperature. The method begins with reconstructing a second-order hybrid equivalent circuit model for lithium-ion batteries, through which an adaptive update rate for battery model parameters is designed. On this basis, a nonlinear observer for battery states is introduced by integrating filters to estimate SOH. The proposed method considers the impact of capacity in the design of the parameter adaptive update rate, enabling the capacity to be dynamically adjusted based on the actual state of the batteries. This reduces the cumulative error in the SOC observer and improves the modeling accuracy of battery models. Experimental results demonstrate that the method proposed in this paper exhibits exceptional performance in SOH estimation under different temperature conditions. The mean absolute error for SOH estimation does not exceed 0.5%, and the root mean square error does not exceed 0.2%. This method can significantly improve the estimation accuracy of SOH, providing a more efficient and accurate solution for battery management systems in EVs. [ABSTRACT FROM AUTHOR]

This paper presents an improved method for encrypting color images, surpassing the effectiveness of genetic crossover and substitution operations. The technique incorporates dynamic random functions to enhance the integrity of the resulting vector, increasing temporal complexity to thwart potential attacks. The improvement involves integrating genetic crossover and utilizing two extensive pseudorandom replacement tables derived from established chaotic maps in cryptography. Following the controlled vectorization of the original image, our approach initiates with a first genetic crossover inspired by deoxyribonucleic acid (DNA) behavior at the pixel level. This genetic crossover is succeeded by a confusion-diffusion lap, reinforcing the connection between encrypted pixels and their neighboring counterparts. The confusion-diffusion process employs dynamic pseudorandom affine functions at the pixel level. Then a second genetic crossover operator is applied. Simulations conducted on a diverse set of images with varying sizes and formats showcase the robustness of our method against statistical, brute-force, and differential attacks. [ABSTRACT FROM AUTHOR]

The resonance circuit's design has a major influence on the inductive electric vehicle (EV) charging system's performance and the distance between the primary and secondary inductive coils. If resonance circuitry is not included in an inductive power transfer (IPT) system, its performance suffers dramatically and its power transfer efficiency suffers significantly. Furthermore, the design of the resonance circuit has a major impact on the rating as well as the voltage and current strains on the semiconductor switches. The sequence, amplitude, and shape of the waveform are determined by the configuration of the energy storage components. The arrangement of these components is critical in defining how the inductive power transfer system behaves and operates. A few popular architectures play an important role in shaping how the system works. In this paper, the significance and effect of resonance circuits on the inductive charging of electric vehicles have been reviewed and discussed comprehensively. Furthermore, a detailed discussion was presented for the second-order resonance circuit, the higher-order resonance circuit, and the hybrid resonance circuit. Additionally, H-bridge resonant inverter topology was discussed and three main resonant architectures for the H-bridge inverter were studied inclusively. They include the inductor-capacitor-inductor (LCL) resonance architecture, switched inductor-capacitor (SLC) resonance architecture, and High-gain resonance architecture. Also, a comparison of these architectures was done and represented in tabular form. Lastly, an analysis of the effect of frequency variations in the resonant circuit architectures. [ABSTRACT FROM AUTHOR]

In order to solve problems such as a slow switching speed, a high switching power, a loss of pure IGBT modulators, and the weak withstanding load short-circuit ability of pure SiC MOSFET modulators used for vacuum loads, this paper proposes a new scheme for high-voltage pulse modulators based on SiC MOSFET/IGBT hybrid connecting circuits. It has a low power loss like the pure SiC MOSFET modulator and a strong withstanding load short-circuit ability like the pure IGBT modulator. Firstly, the principle circuit of the hybrid connecting modulator are discussed and chosen. And the basic working processes of the hybrid parallel-series modulator is described in detail. Secondly, three key points in this new scheme are analyzed and designed as follows: the static and dynamic voltage sharing; the actualizing of the ZVS process for IGBTs; the improvement of short-circuit protection for SiC MOSFETs. A modulator consisting of 16-stage 1200 V-SiC MOSFETs and 1200 V-IGBTs in hybrid parallel-series states is tested. Based on the sample circuit, the working data, such as high-voltage pulse waveforms of 10 kV/2 KHz/10 μs, static and dynamic voltage sharing, the driving control sequence, the U/I sequence of the IGBT, the short-circuit protection waveform, and the calculation, are obtained and discussed. [ABSTRACT FROM AUTHOR]

A novel hybrid bandpass filter (BPF) with wideband and high selectivity is proposed in this paper. The hybrid BPF is composed of two film bulk acoustic resonator (FBAR) cells and three lumped component resonators realized by the integrated passive device (IPD) technology. The ABCD matrix to S-parameters matrix method is used to calculate the frequency response of the BPF. Moreover, the expressions of transmission zeros (TZs) have been extracted. In the design process, an iterative design approach is proposed to improve the circuit and layout of the hybrid filter based on the packaged acoustic-electric hybrid simulation effect. Finally, two parts of the filter are packaged based on the flip-chip method, and two prototypes for the BPF are measured. The measured results of two chips with 3 dB fractional bandwidth of 13.7% and 15.8% are designed and fabricated, which verifies the validity of the proposed design principle. [ABSTRACT FROM AUTHOR]

DC circuit breakers (DCCBs) are the key equipment to rapidly interrupt the fault current in high-voltage DC power grids and ensure the safe operation of the system. However, most DCCBs do not take current-limiting measures and rely solely on current-limiting reactors in the system to limit the rate of current rise during the interruption process. The extensive use of fully controlled power electronic devices in circuit breakers (CBs) results in high costs. To address the issues above, this paper proposes a DCCB topology with a current-limiting function based on thyristors and diodes, which can reduce the cost of CB while ensuring reliable interruption. The impact of various parameters on CB performance is analyzed using numerical calculations to optimize the parameters. Then, a simulation model of a 500 kV/16 kA DCCB is built in PSCAD/EMTDC, and the performance of the proposed CB topology is compared with the other CB topologies. By comparison, the proposed DCCB topology can reliably isolate fault currents and reduce the amplitude of fault currents and the cost of CBs. Significantly, the energy absorbed by the metal oxide varistor (MOV) during the interruption process decreases by 64.2%, reducing the cost and volume of the MOV. Finally, the feasibility of the CB is further verified in the ±500 kV 4-terminal high-voltage DC power grid simulation model. The results show that the proposed DCCB topology can limit the fault current rise rate, interrupt and isolate the fault reliably, and reduce the cost. [ABSTRACT FROM AUTHOR]

Mass-deployable implementations for quantum communication require compact, reliable, and low-cost hardware solutions for photon generation, control and analysis. We present a fiber-pigtailed hybrid photonic circuit comprising nonlinear waveguides for photon-pair generation and a polymer interposer reaching 68 dB of pump suppression and photon separation based on a polarizing beam splitter with > 25 dB polarization extinction ratio. The optical stability of the hybrid assembly enhances the quality of the entanglement, and the efficient background suppression and photon routing further reduce accidental coincidences. We thus achieve a 96 - 8 + 3 % concurrence and a 96 - 5 + 2 % fidelity to a Bell state. The generated telecom-wavelength, time-bin entangled photon pairs are ideally suited for distributing Bell pairs over fiber networks with low dispersion. [ABSTRACT FROM AUTHOR]

Spins are prototypical systems with the potential to probe magnetic fields down to the atomic scale limit. Exploiting their quantum nature through appropriate sensing protocols allows to enlarge their applicability to fields not always accessible by classical sensors. Here we first show that quantum sensing protocols for AC magnetic fields can be implemented with molecular spin ensembles embedded into hybrid quantum circuits. We then show that, using only echo detection at microwave frequency and no optical readout, Dynamical Decoupling protocols synchronized with the AC magnetic fields can enhance sensitivity up to S ≈ 10−10 − 10−9 T Hz−1/2 with a low (4-5) number of applied pulses. These results paves the way for the development of strategies to exploit molecular spins as quantum sensors. [ABSTRACT FROM AUTHOR]

For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor–CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network's controller. Firstly, the input neurons perform preprocessing for the DVS camera's events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply–Accumulate (MAC) calculations according to the memristor's current–voltage relationship. The hidden and output neurons can convert the crossbar's column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network's controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network's performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme. [ABSTRACT FROM AUTHOR]

A distributed feedback laser with integrated quarter‐wave phase shift and more than 100 mW optical output power at an emission wavelength of 780 nm is presented. The laser provides mode‐hop‐free tuning over a wide range of injections currents and operating temperatures by design and can serve as an enabling component for more complex systems such as chips with additional monolithically integrated amplifiers, chip arrays and sources for hybrid integrated photonic circuits. [ABSTRACT FROM AUTHOR]

Real-time heterogeneous parallel embedded digital signal processor (DSP) systems process multiple data streams in parallel in a stringent time interval. This type of system on chip (SoC) requires the network on chip (NoC) to establish multiple symbiotic parallel data transmission paths with ultra-low transmission latency in real time. Our early NoC research PCCNOC meets this need. The PCCNOC uses packet routing to establish and lock a transmission circuit, so that PCCNOC is perfectly suitable for ultra-low latency and high-bandwidth transmission of long data packets. However, a parallel multi-data stream DSP system also needs to transmit roughly the same number of short data packets for job configuration and job execution status reports. While transferring short data packets, the link establishment routing delay of short data packets becomes relatively obvious. Our further research, thus, introduced PaCHNOC, a hybrid NoC in which long data packets are transmitted through a circuit established and locked by routing, and short data packets are attached to the routing packet and the transmission is completed during the routing process, thus avoiding the PCCNOC setup delay. Simulation shows that PaCHNOC performs well in supporting real-time heterogeneous parallel embedded DSP systems and achieves overall latency reduction 65% compared with related works. Finally, we used PaCHNOC in the baseband subsystem of a real 5G base station, which proved that our research is the best NoC for baseband subsystem of 5G base stations, which reduce 31% comprehensive latency in comparison to related works. [ABSTRACT FROM AUTHOR]

This paper proposes a fast transient load response capacitor-less low-dropout regulator (CL-LDO) for digital analog hybrid circuits in the 180 nm process, capable of converting input voltages from 1.2 V to 1.8 V into an output voltage of 1 V. The design incorporates a rail-to-rail input and push–pull output (RIPO) amplifier to enhance the gain while satisfying the requirement for low power consumption. A super source follower buffer (SSFB) with internal stability is introduced to ensure loop stability. The proposed structure ensures the steady-state performance of the LDO without an on-chip capacitor. The auxiliary circuit, or transient enhancement circuit, does not compromise the steady-state stability and effectively enhances the transient performance during sudden load current steps. The proposed LDO consumes a quiescent current of 47 µA and achieves 25 µV/mA load regulation with a load current ranging from 0 to 20 mA. The simulation results demonstrate that a settling time of 0.2 µs is achieved for load steps ranging from 0 mA to 20 mA, while a settling time of 0.5 µs is attained for load steps ranging from 20 mA to 0 mA, with an edge time of 0.1 µs. [ABSTRACT FROM AUTHOR]

Hydrogel-gated synaptic transistors offer unique advantages, including biocompatibility, tunable electrical properties, being biodegradable, and having an ability to mimic biological synaptic plasticity. For processing massive data with ultralow power consumption due to high parallelism and human brain-like processing abilities, synaptic transistors have been widely considered for replacing von Neumann architecture-based traditional computers due to the parting of memory and control units. The crucial components mimic the complex biological signal, synaptic, and sensing systems. Hydrogel, as a gate dielectric, is the key factor for ionotropic devices owing to the excellent stability, ultra-high linearity, and extremely low operating voltage of the biodegradable and biocompatible polymers. Moreover, hydrogel exhibits ionotronic functions through a hybrid circuit of mobile ions and mobile electrons that can easily interface between machines and humans. To determine the high-efficiency neuromorphic chips, the development of synaptic devices based on organic field effect transistors (OFETs) with ultra-low power dissipation and very large-scale integration, including bio-friendly devices, is needed. This review highlights the latest advancements in neuromorphic computing by exploring synaptic transistor developments. Here, we focus on hydrogel-based ionic-gated three-terminal (3T) synaptic devices, their essential components, and their working principle, and summarize the essential neurodegenerative applications published recently. In addition, because hydrogel-gated FETs are the crucial members of neuromorphic devices in terms of cutting-edge synaptic progress and performances, the review will also summarize the biodegradable and biocompatible polymers with which such devices can be implemented. It is expected that neuromorphic devices might provide potential solutions for the future generation of interactive sensation, memory, and computation to facilitate the development of multimodal, large-scale, ultralow-power intelligent systems. [ABSTRACT FROM AUTHOR]

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively. [ABSTRACT FROM AUTHOR]

The series‐type direct current (DC) hybrid circuit breaker (S‐HCB) concept was previously reported to offer better performance than solid‐state circuit breakers (SSCB) and hybrid circuit breakers (HCB). S‐HCB offers low conduction power loss like an HCB and μs$\umu \text{s}$‐scale interruption time, which is even faster than an SSCB. It uses a pulse transformer to isolate the lower‐voltage high‐inductance power electronic circuit from the high‐voltage, low‐inductance main power loop. This paper provides analysis of the impact of the S‐HCB circuit components on the overall system performance and a scalable S‐HCB design guide for different DC system voltage and current ratings. In addition, system energy flow analysis is performed in the time domain to provide an understanding of how energy is delivered, dissipated, and released throughout the entire fault interruption process. The S‐HCB prototype was experimentally tested at 3 kV/30 A and 6 kV/150A with the results showing the interruption of the low fault current of 30 A and the high fault current of 150 A within 8 μs$\umu \text{s}$ and maintaining the fault current at a near zero value for 300μs$\nobreakspace \umu \text{s}$ to enable an arcless opening of a series mechanical switch. The key design challenges of S‐HCB at high voltage and high current ratings were discussed and possible solutions to mitigate those challenges were introduced. [ABSTRACT FROM AUTHOR]

This document is an editorial for a special issue of the journal Nanomaterials titled "Nano-Optics and Nano-Optoelectronics: Challenges and Future Trends." The editorial highlights the importance of nano-optics and nano-optoelectronics in investigating light at the nanometer scale and the interaction of nanometer-scale objects with light. The field has seen extensive research in the past decade, with promising applications in various areas such as optical communication, sensing, imaging, medicine, and green energy. The special issue includes sixteen papers that discuss recent advances in nanostructures and nanomaterials, as well as practical nano-optical and nano-optoelectronic technologies. The articles cover topics such as metastructures, metalenses, nanoparticles, layered 2D materials, and nano-semiconductors, and explore their applications in photodetectors, solar cells, modulators, light emitters, and nanofabrication. The issue also includes reviews on nano-related infrared absorption technology and neuromorphic photonics devices. Overall, the special issue provides valuable insights into the latest developments and future trends in nano-optics and nano-optoelectronics. [Extracted from the article]

Hybrid circuit breakers are the most promising circuit breakers among DC circuit breakers. Conventional hybrid circuit breakers complete fault current isolation by converting current to IGBT when fault current occurs. However, in this case, the fault current continues to increase, so the IGBT must be large enough to withstand this current. In addition, in the case of a method of detecting and operating a fault, a delay time of up to hundreds of microseconds occurs, and in a hybrid circuit breaker, this delay time is a very large value. To solve this problem, this paper proposes a hybrid Z-source circuit breaker that operates without delay for low-impedance faults. The proposed breaker is designed to reduce stress on IGBTs and mechanical switches by generating a current zero crossing, as well as to enable the breaker to trip quickly in high-risk cases such as low-impedance fault circuits. Due to the limited environment of the laboratory, we performed 600 V fault isolation experiments. As a result of the experiment, it was confirmed that the proposed circuit breaker successfully isolated the fault within 1.6 ms. The current limiting feature of the Z-source appears to reduce stress on the IGBTs and MOVs used, and it allows for faster fault isolation. [ABSTRACT FROM AUTHOR]

The combination of permanent magnets and electrically excited windings creates an air gap magnetic field. The development of a hybrid magnetic circuit motor with an adjustable magnetic field is of great significance. This article introduces a hybrid magnetic circuit motor design that combines salient pole electromagnetic and permanent magnets. A tubular magnetic barrier has been designed to reduce inter-pole leakage and enhance the usage rate of permanent magnets in the hybrid magnetic circuit motor. The optimum eccentricity of the rotor has been accurately designed, resulting in an improved sinusoidal distribution of the air gap magnetic density waveform. An analysis of the static composite magnetic field under various excitation currents has been conducted, showcasing the capability of the hybrid magnetic circuit motor to stably adjust the air gap flux density level and output torque. A prototype has undergone comprehensive trial production and testing, conclusively confirming the machine's superior output performance. [ABSTRACT FROM AUTHOR]

As synthetic biology permeates society, the signal processing circuits in engineered living systems must be customized to meet practical demands. Towards this mission, novel regulatory mechanisms and genetic circuits with unprecedented complexity have been implemented over the past decade. These regulatory mechanisms, such as transcription and translation control, could be integrated into hybrid circuits termed "multi-level circuits". The multi-level circuit design will tremendously benefit the current genetic circuit design paradigm, from modifying basic circuit dynamics to facilitating real-world applications, unleashing our capabilities to customize cellular signal processing and address global challenges through synthetic biology. As synthetic biology permeates society, the signal processing circuits in engineered living systems must be customized to meet practical demands. In this review, the authors outline design strategies for the DNA, RNA, and protein-level circuits and the hybrid "multi-level" circuits. [ABSTRACT FROM AUTHOR]

With the fast growth of electronic technology today, the hybrid circuit of analog and digital circuits has become a trend in the growth of electronic technology. To address fault diagnosis in analog circuits, Haar wavelet is applied for fault feature extraction. The K-means clustering method and pseudoinverse algorithm were used to optimize the center value and weight value of the radial basis function neural network, respectively. The adaptive step size was improved in the wolf pack algorithm, the parameters of the radial basis function neural network were optimized based on the wolf pack algorithm, and a wolf pack algorithm optimized radial basis function neural network model was constructed. The test results show that this model converges after 40 times of training, with an error value of 10−3 and an average value of the mean squared error of 0.45. Comparing the fault diagnosis rates of the original model, genetic algorithm optimized radial basis function neural network model, and wolf colony algorithm optimized radial basis function neural network model, the last model has the best fault diagnosis rate, reaching 95.52%. The wolf colony algorithm is utilized to optimize the radial basis function neural network model to diagnose the faults in the standard filter circuit, and the fault diagnosis rate reaches 96.17%. The findings express that the radial basis function neural network model optimized by the wolf colony algorithm has a good diagnosis effect for different faults in the analog circuit. [ABSTRACT FROM AUTHOR]

Aimed at the optimization design of the parameters of the commutation circuit of a hybrid DC-current-limiting circuit breaker (HDCCLCB), a parameter selection model considering the short-time withstand of the thyristor and the volume of the commutation circuit is proposed by simplifying the object, and the commutation circuit parameters were preliminarily obtained. In order to verify the correctness of the method of selecting the commutation circuit parameters, the circuit simulation model of the HDCCLCB was built. The experimental platform was built, and the breaking experiment was completed under the fault condition with the current rising rate of 20 A/μs. The correctness of the simulation model and parameter design method was verified by comparing the circuit model simulation results with the experimental results. In order to further optimize the parameters of the commutation circuit, a mathematical model for optimization design was established. Taking the maximum critical breakdown voltage under unit capacitance energy as the objective function, the arcing time before commutating and the current-limiting inductance and capacitance are enumerated to obtain the optimized commutation circuit parameters. By comparing this result with the result of the preliminary design, the objective function is improved by 20.7%, laying a solid foundation for further research and the development of current-limiting circuit breakers for medium-voltage DC systems. [ABSTRACT FROM AUTHOR]

The new emerging non-volatile memory (NVM) devices known as memristors could be the promising candidate for future digital architecture, owing to their nanoscale size and its ability to integrate with the existing CMOS technology. The device has involved in various applications from memory design to analog and digital circuit design. In this paper, a combination of memristor devices and CMOS transistors is working together to form a hybrid CMOS-memristor circuit for XAX- Module, a core element used as digital circuit for elliptic curve cryptography. The proposed design was implemented using Pt/TaOx/Ta memristor device and simulated in Cadence Virtuoso. The simulation results demonstrate the design functionality. The proposed module appears to be efficient in terms of layout area, delay and power consumption since the design utilizes the hybrid CMOS/memristor gates. [ABSTRACT FROM AUTHOR]

LED (light-emitting diode) drivers with the nonresonant DC-DC converters produce higher current and voltage ripple than the resonant converters. The resonant converter-based LED drivers provide low cost, high efficiency, enhanced soft switching capabilities, and simple construction. Therefore, this research work is motivated to propose a hybrid resonant converter to power the LED. The proposed modified hybrid resonant with valley-fill converter is built by removing the capacitors across the switches and the output diode is replaced with a valley-fill circuit in the conventional hybrid resonant converter. With the valley-fill circuit, the switches and the diode are subjected to reduced stress, reduced flicker, and improved efficiency. The modified Hybrid resonant converter with valley-fill circuit LED driver's performance parameters are compared with existing resonant converter topologies in terms of component count, current stress, voltage stress across the switch and output diode, LED voltage ripple, current ripple, and efficiency. A 10 W, 24 V laboratory prototype of modified Hybrid resonant converter with valleyfill circuit LED driver is developed, and the simulation results are validated. [ABSTRACT FROM AUTHOR]

Hybrid quantum systems have shown promise in image classification by combining the strengths of both classical and quantum algorithms. These systems leverage the parallel processing power of quantum computers to perform complex computations while utilizing classical algorithms to handle the vast amounts of data involved in imaging. The hybrid approach is intended to improve accuracy and speed compared to traditional classical methods. Further research and development in this area can revolutionize the way medical images are classified and help improve patient diagnosis and treatment. The use of Conventional Neural Networks (CNN) for the classification and diagnosis of medical images using big datasets requires, in most cases, the use of special high-performance computing machines, which are very expensive and hard to access by most researchers. A new form of Machine Learning (ML), Quantum machine learning (QML), is being introduced as an emerging strategy to overcome this problem. A hybrid quantum–classical CNN uses both quantum and classical convolution layers designed to use a parameterized quantum circuit. This means that the computing model utilizes a quantum circuits approach to construct QML algorithms, which are then used to transform the quantum state to extract image hidden features. This computational acceleration is expected to achieve better algorithm performance than classical CNNs. This study intends to evaluate the performance of a Hybrid Quantum CNN (HQCNN) against a conventional CNN. This is followed by some optimizer modifications for both proposed and classical CNN methods to investigate the possible further improvement of their performance. The optimizer modification is based on forcing the optimizer to be directly adaptive to model accuracy. The optimizer adaptiveness is based on the development of an optimizer with a loss base adaptive momentum. Several algorithms are developed to achieve the above-mentioned goals, including CNN, QCNN, CNN with the adaptive optimizer, and QCNN with the Adaptive optimizer. The four algorithms are tested against a Kaggle brain dataset containing over 7000 samples. The test results show the hybrid quantum circuit algorithm outperformed the conventional CNN algorithm. The performance of both algorithms was further improved by using a fully adaptive SGD optimizer. [ABSTRACT FROM AUTHOR]

The state of the energy-absorption branch MOV in the hybrid DC circuit breaker (DCCB) has a very important impact on the short fault breaking operation of the circuit breaker. Therefore, it is necessary to evaluate the state of the MOV, which is also called the "sleep component". Due to DCCB being placed indoors, the aging is mainly caused by short-circuit impulse current. Therefore, this paper mainly focuses on the study of the short-circuit impulse aging characteristics of the energy-absorption branch MOV. The dynamic simulation system of a hybrid DCCB was built to investigate the impulse of short-circuit current on the MOV of the energy-absorption branch during the circuit breaking process. Then, an accelerated impulse aging test platform was built and the accelerated impulse aging tests of the MOV were conducted. The aging characteristics of the MOV were analyzed in detail and detailed analysis was conducted of the macroscopic parameters and microstructure changes. The results indicate that the nonlinear coefficient α could be emphasized as a basis for judging the "sleeping" component states and aging degree of the hybrid DC circuit breaker, and can be expected to be applicable to MOV condition monitoring of BCCB in the future. [ABSTRACT FROM AUTHOR]

This paper presents a 250 kHz bidirectional battery charger circuit using a GaN HEMT. The charger is subjected to a high-/low-side constant voltage at 200 V/20 V. The charger circuit is a hybrid of the LLC and flyback circuit topologies. Both the power output analysis and efficiency control of this circuit are simplified when the magnetization current is minimized using the low-resistance GaN HEMT. The switching frequency is controlled to match the series resonance in a way that is analogous to conventional LLC circuit controls, while the duty ratio that determines the power output and the dead time, which determines the zero voltage switching, is controlled in an analogous manner to the flyback circuit control. The charging and discharging modes were altered by applying a double-throw relay that changes the transformer turn ratio, which is different from conventional LLC designs using the switching frequency adjustment. A nominal turn ratio with Np = 35 and Ns = 3.5 for a 200 V/20 V converter can only produce an internal series resonance with no current flowing in any charging direction. The proposed circuit using a transformer with multiple windings (Np = 35, Ns,F = 4, and Ns,R = 3) was fabricated to deliver 125 W output power from the power grid battery to the vehicle battery in the forward (charging) mode and 90 W in the reverse (discharging) mode. The conversion efficiency was calculated to be as high as 97% in the forward mode and 95% in the reverse mode. The high conversion efficiency is due to the characteristics of the GaN HEMT, including low resistive and switching losses. The equations derived in this paper associate these losses with the series resonant frequency and power conversion rate, which highlight the advantages of using a GaN HEMT in this CLLC design. [ABSTRACT FROM AUTHOR]

We present a novel closed-loop system designed to integrate biological and artificial neurons of the oscillatory type into a unified circuit. The system comprises an electronic circuit based on the FitzHugh-Nagumo model, which provides stimulation to living neurons in acute hippocampal mouse brain slices. The local field potentials generated by the living neurons trigger a transition in the FitzHugh–Nagumo circuit from an excitable state to an oscillatory mode, and in turn, the spikes produced by the electronic circuit synchronize with the living-neuron spikes. The key advantage of this hybrid electrobiological autogenerator lies in its capability to control biological neuron signals, which holds significant promise for diverse neuromorphic applications. [ABSTRACT FROM AUTHOR]

Multi‐terminal flexible DC power grid plays an important role in large‐scale new energy integration, which usually requires the installation of multi‐terminal DC circuit breaker (MTCB) at the intersection of multiple DC lines. At present, the research on multi‐terminal DC circuit breaker is mostly limited to theoretical simulation calculation, and there are few experimental studies and engineering applications. In this paper, a four‐terminal DC circuit breaker based on commutating path multiplexing is proposed, which combines with the compact natural commutation scheme of hybrid gap, greatly reducing the cost and volume of the circuit breaker. The commutation characteristics of the four‐terminal hybrid DC circuit breaker equivalent prototype at 10‐kV voltage level were tested. On this basis, the equivalent prototype of the circuit breaker test results shows that under 10‐kV voltage level, the four‐terminal circuit breaker topology can achieve breaking of 11 kA in 2.8 ms by the natural commutation method. [ABSTRACT FROM AUTHOR]

This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold‐FET connected high electron mobility transistors acting as varactors. Two types of periodically‐loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two‐tone measurements, and the circuit demonstrates a 3rd‐order intercept input power larger than 30 dBm for control biases above −12 V. [ABSTRACT FROM AUTHOR]

In this paper, a controllable hybrid plasmonic integrated circuit (CHPIC) composed of hybrid plasmonic waveguide (HPW)-based rhombic nano-antenna, polarization beam splitter, coupler, filter, and sensor has been designed and investigated for the first time. In order to control the power into a corresponding input port, a graphene-based 1 × 3 power splitter with switchable output has been exploited. The functionality of each device has been studied comprehensively based on the finite element method and the advantages over state-of-the-art have been compared. Moreover, the effect of connection of CHPIC to the photonic and plasmonic waveguides has been studied to exhibit the capability of variety excitation methods of the CHPIC. Furthermore, the performance of the proposed CHPIC connected to inter/intra wireless transmission links has been investigated. The wireless transmission link consists of two HPW-based nano-antennas as transmitter and receiver with the maximum gain and directivity of 10 dB and 10.2 dBi, respectively, at 193.5 THz. The suggested CHPIC can be used for applications such as optical wireless communication and inter/intra-chip optical interconnects. [ABSTRACT FROM AUTHOR]

In this study, a new 36‐pulse rectifier with a hybrid DC‐reinjection circuit is proposed. It multiplies the AC‐side input voltage steps from 12 to 36 using a hybrid auxiliary circuit for voltage and current modulation. Both the AC and DC side harmonics of the rectifier system are efficiently suppressed when combined with filter capacitors at DC side. Only 2 more diodes and an IGBT are used in the proposed approach for constituting the injection circuit. The cascaded structure of rectifier bridges allows for significant voltage gain, making it appropriate for high power output rectification applications. The proposed 12‐pulse rectifier's phase shifting structure and 36‐pulse rectifier's operational theory are introduced. The injection transformer's turn ratio and the IGBT's conduction angle are both designed to have the lowest possible harmonic distortion of the voltage at AC side. Analyses are done on the rectifier's impedance matching feature and energy loss of IGBT. The operating performance of the rectifier is assessed when the active switch fails. With the help of a 1.8 kW prototype and a HIL system based on Starsim, the theoretical portion is confirmed. The results of the simulation and experiments support the effectiveness of the hybrid voltage harmonic injection method studied. [ABSTRACT FROM AUTHOR]

In recent years, low-voltage direct current (LVDC) microgrids are becoming more attractive because they represent a solution to integrate renewable sources, storage, and electronic loads bringing some advantages in comparison with traditional AC grids. However, the protection of such a network involves many challenges, especially in the case of LVDC microgrids with more than one feeder and multiple energy sources. Indeed, the traditional protection breakers used for an AC grid cannot isolate the faults and protect the components of a DC grid, while the use of solid-state circuit breakers increases energy losses. This paper deals with the analysis and design of the protection schemes for LVDC microgrids through the combination of mechanical circuit breakers and hybrid circuit breakers. This solution has the advantage of energy loss reduction but introduces further issues due to the slow transition times of the mechanical circuit breakers. Thus, a completely decentralized control system capable of overcoming the fast fault-clearing time, cost-effectiveness, and selectivity issues is designed to protect from pole-to-pole faults. The proposed control strategy is compared with a centralized protection scheme available in the literature through numerical simulation. The two algorithms show similar performances, with a mean voltage dip duration of less than 30 ms and a maximum voltage dip duration of about 100 ms in the most severe fault condition, but the proposed solution is more reliable and flexible since it does not depend on the communication system. [ABSTRACT FROM AUTHOR]

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits. Increasing functional density is desirable for future scaling of electronics. Here, the authors use a nanowire ferroelectric tunnel field-effect transistor to achieve reconfigurable signal modulations for low-power and high-density analogue circuits. [ABSTRACT FROM AUTHOR]

The high‐voltage direct current (HVDC) power transmission short‐circuit fault protection is a big challenge, and it is the main obstacle to promote the HVDC multi‐terminal networks. A natural commutation current topology (NCCT) of hybrid HVDC circuit breaker (DCCB) integrated with limiting fault current is proposed in this paper, which shares several obvious merits, such as lower peak fault current, shorter fault isolation time and low turn‐off loss. The main contributions in this paper are made as follows. (1). A second‐order RLC circuit in novel NCCT circuit breaker is utilized as the current limiting circuit to dramatically reduce the fault current rising slope and its peak value. (2) A asynchronous NCCT circuit breaker has been investigated to broaden the proposed NCCT circuit breaker's optimal working area. (3) By taking China Zhangbei 500 kV four‐terminal DC grid as an example, an optimization design technique of the asynchronous NCCT‐DCCB is developed to demonstrate the process of the theoretical analysis and parameter design. The correctness of the proposed NCCT‐DCCB and the feasibility of the optimization design technique are confirmed by EMT simulation on PSCAD/EMTDC and hardware‐in‐loop experiment on PLECS‐RtBox. [ABSTRACT FROM AUTHOR]

Sense amplifier is a key element of memory and a CMOS-based spin hybrid circuit. Magnetic tunnel junction (MTJ) is a key spintronic device used in spin-based memory and hybrid circuits. This paper presents a design of a voltage-controlled magnetic anisotropy MTJ-based sense amplifier (VCMA-SA) that offers better reliability, power efficiency and high-speed performance. MTJ switching between different resistive states in this paper takes place through the faster and energy-efficient voltage-controlled magnetic anisotropy (VCMA) scheme rather than the traditional spin-transfer torque (STT)-based magnetization switching. This paper demonstrates that SA based on VCMA-MTJ switching is faster, reliable and more energy-efficient compared with iPMA-based STT switching. [ABSTRACT FROM AUTHOR]

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In this paper, Astable Multivibrator (AMV) circuits are designed and simulated using pure Carbon Nanotube Field Effect Transistors (CNTFETs) as well as hybrid CNT-CMOS technology, and simulation results are compared with conventional CMOS technology by varying the value of resistor- 'R', capacitor- 'C', supply voltage- 'Vdd' and temperature- 'T'. It has been found that novel CNT-based AMV outperforms conventional CMOS-based AMV and the performance of hybrid circuits exists between PURE-CNT-AMV and CMOS-AMV. The rise time and fall time of PURE-CNT-AMV are improved by 97.2% and 96.5% respectively as compared to CMOS-AMV, which increases the speed of operation of the circuit. A significant improvement of approximately 3515% is observed in the slew rate of PURE-CNT-AMV and also, the amplitude of the output square wave is increased by 0.91%. In addition, the maximum usable frequency for PURE-CNT-AMV is increased by 656.96% as compared to CMOS-AMV. Furthermore, the behavior of CNT-based AMV circuits is also analyzed by varying the number of CNTs- 'N', inter CNT pitch- 'S' and CNT diameter- 'DCNT' at R = 50kΩ, C = 1 pf and Vdd = 0.9 V. However, the power dissipation of PURE-CNT-AMV is 3.7% higher than CMOS-AMV which can be improved by adjusting the value of 'R–C' delay network, operating the circuit at lower supply voltage, and choosing the optimum value of N, S and DCNT. [ABSTRACT FROM AUTHOR]

Hybrid DC circuit breakers (HDCCBs) have excellent performance in terms of breaking speed and low losses and have become the mainstream technology for dc fault isolation in dc grids. However, because of the breaking limitation of the solid-state branch in HdcCBs, the existing HdcCBs are still weak in breaking high current. Although the breaking ability can be improved by series and parallel devices, the cost will increase rapidly, and it is very difficult to share current by paralleling a single type of device. This article proposes a novel HdcCB topology that combines two types of power electronic devices in solid-state branches to meet the requirement of a large breaking capacity in dc grids. The structure and breaking principles of this novel topology, which aims to break high current, are introduced. The design methods of the key parameters are presented. Then, the current breaking ability of the novel topology is verified by developing a prototype completing a 10 kV/60 kA breaking test in 3 ms. Finally, this novel topology is compared with other dc circuit breakers at the same breaking level, which shows that this novel topology has obvious advantages in cost and volume with fewer devices. [ABSTRACT FROM AUTHOR]

A transient multi-physics model incorporated with an electromagneto-thermomechanical coupling is developed to capture the multi-field behavior of a single-pancake (SP) insert no-insulation (NI) coil in a hybrid magnet during the charging and discharging processes. The coupled problem is resolved by means of the finite element method (FEM) for the magneto-thermo-elastic behaviors and the Runge-Kutta method for the transient responses of the electrical circuits of the hybrid superconducting magnet system. The results reveal that the transient multi-physics responses of the insert NI coil primarily depend on the charging/discharging procedure of the hybrid magnet. Moreover, a reverse azimuthal current and a compressive hoop stress are induced in the insert NI coil during the charging process, while a forward azimuthal current and a tensile hoop stress are observed during the discharging process. The induced voltages in the insert NI coil can drive the currents flowing across the radial turns where the contact resistance exists. Therefore, it brings forth significant Joule heat, causing a temperature rise and a uniform distribution of this heat in the coil turns. Accordingly, a thermally/mechanically unstable or quenching event may be encountered when a high operating current is flowing in the insert NI coil. It is numerically predicted that a quick charging will induce a compressive hoop stress which may bring a risk of buckling instability in the coil, while a discharging will not. The simulations provide an insight of hybrid superconducting magnets under transient start-up or shutdown phases which are inevitably encountered in practical applications. [ABSTRACT FROM AUTHOR]

Electronic memory with ever-increasing storage capacity is always in high demand. Every year, a computer transforms into a smaller, faster, and more reliable device. Memristor is a passive aspect recently developed that is gaining popularity. The non-volatile and small area features of this element are very essential. A Memristor's ability to fabricate around CMOS architectures is a step forward in VLSI design enhancement. When developing a fast multilevel switching device, increasing information density in the same silicon area is a desirable feature. In this design and analysis, a unique memristor-based CMOS inverter is presented. A unique inverter with a nonvolatile output and good performance. This characteristic makes it useful for a substitute inverter as well as an SRAM memory cell that supports input negation for special uses. Memristor-based CMOS design is an emerging concept that targets efficient memory computing systems. Simulations were performed in cadence using a memristor model extracted to analyze and compare power consumption. The analyses of non-volatility, the voltage produced, and read/write period were performed with cadence virtuoso 130 nm CMOS technology using a power supply voltage of 1.9 V while consuming 35.67 µW, and the delay is 9.235 ps. The comparsion with a pure CMOS implementation is promising in terms of power, area and delay significant improvement. Further, the Monte Carlo simulation results using 2000 samples confirmed the total power and delay of the proposed design. [ABSTRACT FROM AUTHOR]

Recently, hybrid logic circuits based on magnetic tunnel junctions (MTJs) have been widely investigated to realize zero standby power. However, such hybrid CMOS/MTJ logic circuits suffer from a severe sensing reliability due to the limited tunnel magnetoresistance ratio (TMR ≤ 150%) of the MTJ and the large process variation in the deep sub-micrometer technology node. In this paper, a novel differential sensing amplifier (DSA) is proposed, in which two PMOS transistors are added to connect the discharging branches and evaluation branches. Owing to the positive feedback realized by these two added PMOS transistors, it can achieve a large sensing margin. By using an industrial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can achieve a smaller sensing error rate of 9% in comparison with the previously proposed DSAs with a TMR ratio of 100% and process variation of 10%, while maintaining almost the same sensing delay of 74.5 ps and sensing energy of 1.92 fJ/bit. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel technique for passively autoranging a photonic current transducer (PCT) that incorporates a current transformer (CT), piezoelectric transducer (PZT) and fiber Bragg grating (FBG). Due to the usage of single-mode fiber and FBG, multiple PCTs can be interconnected and distributed over a long distance, for example along a power network, greatly reducing the cost of sensor deployment and offering other unique advantages. The autoranging technique relies on the usage of multiple, serially connected CT burden resistors and associated static MOSFET switches to realize instantaneous shortening of the resistors in response to increasing measured current. This functionality is realized passively, utilizing a modular, μW-power comparator circuit that powers itself from the electrical energy supplied by the CT within a small fraction of the 50/60 Hz cycle. The resultant instantaneous changes in sensor gain will be ultimately detected by the central FBG interrogator through real-time analysis of the optical signals and will be used to apply appropriate gain scaling for each sensor. The technique will facilitate the usage of a single PCT to cover an extended dynamic range of the measurement that is required to realize a combined metering- and protection-class current sensor. This paper is limited to the description of the design process, construction, and testing of a prototype passive autoranging circuitry for integration with the PCT. The two-stage circuitry that is based on two burden resistors, 1 Ω and 10 Ω, is used to prove the concept and demonstrate the practically achievable circuit characteristics. It is shown that the circuit correctly reacts to input current threshold breaches of approximately 2 A and 20 A within a 3 ms reaction time. The circuit produces distinct voltage dips across burden resistors that will be used for signal scaling by the FBG interrogator. [ABSTRACT FROM AUTHOR]

A boost converter is used in various applications to obtain a higher voltage than the input voltage. One of the current main circuit systems for hybrid electric vehicles (HEVs) is a combination of a two-phase boost converter (parallel circuit) and a three-phase two-level inverter. In this study, we focus on the boost converter to achieve even higher efficiency and propose an interleaving scheme for a boost converter suitable for a three-level inverter (series circuit). The series circuit has two capacitors connected in series and makes it suitable as a power supply for a three-level inverter. We analyze the input current ripple of the series and parallel circuit in order to show the superiority of the series circuit. Furthermore, we propose a novel output voltage control strategy using an optimal regulator, namely a Linear Quadratic Regulator (LQR), for the series circuit. As a result, we found the input current ripple of the series circuit is smaller than the parallel circuit and demonstrated the superiority of the series circuit. The simulation and experimental results show the effectiveness of the proposed interleaving scheme and optimal regulator. [ABSTRACT FROM AUTHOR]

Energy routers act as an interface between the distribution network and electrical facilities, which meet the requirements of clean energy substitution and achieve the energy sharing and information transmission in the energy network. However, the protection of the dc load side of residential energy routers including interruption and isolation of short-circuit fault currents is vital for discussion. Since the traditional mechanical and hybrid circuit breakers for dc fault protection have the drawback of slow operation, a solid-state circuit breaker (SSCB) is an optimal solution for fast dc fault interruption. In this paper, a dc SSCB is proposed that uses an RCD + MOV snubber circuit, which is considered the best and most complete circuit used in common SSCBs. There are two main contributions in this paper: First, a dc SSCB is designed, which isolates both positive and negative terminals of a circuit and its working principle and operating modes along with the formulas for calculation of crucial time intervals, voltages, and currents along with the design procedure are provided. Second, a soft turn-on auxiliary is designed to prevent a high current surge caused by the capacitance difference between the source and the load. The experimental results demonstrate the proper performance of the topology and the validity of the findings. [ABSTRACT FROM AUTHOR]

This article is a study of the research development of electrodynamic phenomena occurring in ultra-fast electrodynamic drives. These types of linear drives are among the fastest, not only because of the huge accelerations achieved, but, above all, because of the extremely short reaction time. For this reason, electrodynamic drives are used in hybrid short-circuit breakers. The phenomena occurring in this type of drive are actually magneto-thermo-elastic in nature, but the coupling of these phenomena should be considered weak if the criteria for repeatable operation in a hybrid circuit breaker system are met. The authors have been researching this type of drive for many years through not only experimental studies, but also primarily simulation studies developing models of such drives. The authors present the history of the development starting from the first works of Thomson, and Kesserling and ending with the most current models, including mainly their own. This article presents mainly works studying electrodynamic phenomena. Thermal and mechanical phenomena were comprehensively presented by the authors in previous papers. [ABSTRACT FROM AUTHOR]