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High-voltage direct current (HVDC) circuit breaker development and deployment strongly depend on the testing process, which ensures that the HVDC circuit breakers will satisfy design requirements. This article presents an HVDC circuit breaker test bench circuit configuration that can provide controllable large output currents to simulate different fault conditions for the current breaking test and high output voltage for the dielectric withstand test. The current breaking test circuit is based on multiple cascaded power converters connected in parallel to provide the necessary output current capability. Each cascaded power converter is composed of multiple cells that are operated by a phase-shifted pulsewidth-modulated signal for greater controllability and higher quality of the output waveform. The dielectric withstand test circuit is a simple high-voltage source with a low power rating that can also be used to charge the test bench and the internal circuitry of the circuit breaker that is to be tested. The proposed test bench ensures that fault conditions can be replicated accurately and offers greater flexibility by being able to test mechanical, semiconductor-based, or hybrid HVDC circuit breakers with different current and voltage ratings on the same hardware without any changes. The idea and the operating principle of the proposed test bench are verified experimentally on a downscaled system that consists of three cascaded power converters connected in parallel with three cells per cascaded power converter and with a total equivalent switching frequency of 92.5 kHz. [ABSTRACT FROM AUTHOR]

• A CAOC-MPHDCB is proposed by combining with the principle of controllable active oscillation and the MPHDCB based on negative voltage source, which can not only greatly cut down the total cost and operation loss, but also reduce the insulation requirement of commutation circuit. The CAOC only needs an energy storage capacitor to store several kV pre-charge voltage, and can generate a high voltage on a pulse capacitor after several oscillations. Like a NVS, the CAOC can generate a negative voltage on the transfer branch to accelerate the current commutating from the main branch into the transfer branch. In addition, the IGBT full-bridge in the CAOC only needs to withstand the pre-charge voltage with low amplitude at any time. The simulation results verify the effectiveness of CAOC-MPHDCB, and shows its great application prospect in the field of HVDC interruption. The hybrid high voltage DC circuit breaker (HDCB) is widely regarded as the most promising solution to the fault current interruption of VSC-based DC grids. However, because of a large number of power electronic modules connected in series in transfer branch, the cost of existing HDCBs are pretty high, which limiting their large-scale commercial application. In this paper, a novel multi-port hybrid high voltage DC circuit breaker commutated by controllable active oscillation circuit (CAOC-MPHDCB) is proposed. Based on the principle of controllable active oscillation, the proposed CAOC-MPHDCB can realize the reliable commutation and fast interruption of fault current while significantly reducing the total cost and operation loss. In addition, the CAOC-MPHDCB can not only isolate line faults that occur continuously in a short time, but also maintain system ring-network structure after isolating the faulty DC bus. The influencing mechanism of parameters on the performance of CAOC-MPHDCB are analysed in detail, and the selection methods of corresponding parameters are obtained. The simulation results show that the principle of CAOC-MPHDCB is effective and feasible. [ABSTRACT FROM AUTHOR]

• The equivalent discharging circuit of the hybrid cascaded LCC/MMC inverter is simplified into a first-order RL circuit by assuming the firing-advance angle is constant after the fault. • The mathematical fault current expressions of the hybrid cascaded LCC/MMC high voltage direct current system are analyzed. • By changing the inserted sequence of submodules, an active fault current limiting strategy based on the submodule sorting algorithm is proposed. • The proposed active current limiting strategy can cooperate with other current limiting strategies to further suppress the fault current. The hybrid cascaded LCC/MMC high voltage direct current (HC-HVDC) system is a prospective topology that can avoid the commutation failure problem of LCC-HVDC while ensuring bulk power transmission capability. However, the complex topology results in different DC fault characteristics at the receiving end, which brings challenges to fault detection and current limiting technology. As a result, it is of great theoretical importance to investigate the fault characteristics of the HC-HVDC system and propose the corresponding fault current limiting strategy. Firstly, this paper simplifies the equivalent discharging circuit of the hybrid cascaded LCC/MMC inverter into a first-order RL circuit by assuming the firing-advance angle is constant after fault, and proposes the fault current expressions by Laplace transform. Secondly, by changing the insertion sequence of submodules, an active fault current limiting strategy based on the submodule sorting algorithm (SMS-FCL) is proposed, which can accomplish fault current suppression, reactive power and DC voltage support, and energy loss reduction simultaneously. Moreover, the proposed SMS-FCL can cooperate with other FCLs to further suppress the fault current, and the cooperation prerequisites are analyzed. Finally, an LCC-LCC/MMC HVDC system is built in PSCAD/EMTDC to validate the accuracy of the proposed fault current expressions and the effectiveness of the current limiting strategy. [ABSTRACT FROM AUTHOR]

One of the technical challenges that needs to be addressed for the future of the multi-terminal high voltage direct current (M-HVDC) grid is DC fault isolation. In this regard, HVDC circuit breakers (DCCBs), particularly hybrid circuit breakers (H-DCCBs), are paramount. The H-DCCB, proposed by the ABB, has the potential to ensure a reliable and safer grid operation, mainly due to its millisecond-level current interruption capability and lower on-state losses as compared to electromechanical and solid-state based DCCBs. This paper aims to study and evaluate the operational parameters, e.g., electrical, and thermal stresses on the IGBT valves and energy absorbed by the surge arrestors within H-DCCB during different DC fault scenarios. A comprehensive set of modeling requirements matching with operational conditions are developed. A meshed four-terminal HVDC test bench consisting of twelve H-DCCBs is designed in PSCAD/EMTDC to study the impacts of the M-HVDC grid on the operational parameters of H-DCCB. Thus, the system under study is tested for different current interruption scenarios under a (i) low impedance fault current and (ii) high impedance fault current. Both grid-level and self-level protection strategies are implemented for each type of DC fault. [ABSTRACT FROM AUTHOR]