Search

Onboard computers are expected to perform more and more processor intensive tasks autonomously. Examples can be found in a broad number of applications: efficient data compression for Earth Observation data, system anomaly and fault detection, data encryption, sensor data fusion, etc. More over, the increasing interest in Artificial intelligence (AI) from the Space Industry has only exacerbated the problem. Vision based navigation in Space, Earth Observation data validation in Space, signal to noise ratio (SNR) reduction are only some examples of the need of AI in Space. The Space Industry, as many other industries, has focused exclusively in the use of standard parallelisation techniques for the acceleration of processor intensive algorithms. Parallelisation tools like OpenMP are used to break down a specific operation within the algorithm, e.g. matrix multiplication, into smaller pieces that are processed using several parallel threads. This technique ensures a low processing time of the algorithm. However, it has limited control of CPU usage and moreover it lacks control of the data throughput. In this work the authors propose a well known paradigm to data processing that has recently been rising renewed interest in Academia: pipelining. Pipelining, as opposed to parallelisation, breaks down an algorithm in steps or operation and assign threads to each of these steps. Pipelining is somehow an an assembly line, where each thread is in charge of one specific piece of the product. Academia research shows significant improvements in the overall performance of the algorithm. Moreover, the authors of this paper made use of a lock-free data processing framework to implement a novel pipeline framework that can enhance onboard processing performance even more. This lead to ground-breaking results in terms of CPU usage and data throughput: more than 20%-60% CPU reduction and 2x - 8x data processing rate increase. Two validation experiments are presented by the authors. First, an algorithms consisting on a number of matrix multiplications to be performed sequentially. And secondly, an AI network for Asteroid pose estimation using data from past Space mission. Both experiments where benchmarked and compared with OpenMP, for the matrix multiplication example, and with TensorFlowLite for the AI algorithm, In both instances, the here presented lock-free pipelined approach substantially outperformed both OpenMP and TensorFlowLite both in terms of CPU and data throughput.

EO-ALERT (http://eo-alert-h2020.eu/) is a European Commission H2020 project coordinated by DEIMOS Space, whose main objective is to obtain Earth Observation products with very low latency ( In order to program this COTS device from a global perspective in high level languages, the platform concept has been used. It is based on the block design of the FPGA and the custom Linux created with the Petalinux tool. Once the platform is ready, the new tools for programming Xilinx® COTS allow using all board resources such as IP cores in the FPGA for hardware acceleration or the use of parallel processing frameworks like OpenMP to fork the data between the 4 available cores to increase the performance. To process the sensor images and obtain the target products, artificial intelligence (AI) and machine learning (ML) algorithms developed in the project are implemented by migrating them to the target Hardware, taking into account the most efficient implementation on the system multi-core (4 A53 ARM® cores) or FPGA. The development includes the use of rapid prototyping tools to produce optimized hardware IP blocks and SW libraries. In the implementation and verification phase, a PIL (Processor-In-the-Loop) testbench is created. The objective of the test bench is to have a multi-board breadboard representative of the final architecture, in which to validate the design and its performance. The execution times are measured in the PIL platform, obtaining at the present moment results within the requirements ( For that, the HW architecture allows a master-slave configuration, to be used for this on-board processing, thus reducing the total latency of the product generation or cover more area. On each board the processing takes advantage of the board’s resources (multi-core, FPGA) to obtain the processed products and alerts, which are centralised in the master processing board. In addition, the results are highly significative due to the evaluation of the resulting processing system is performed experimentally using real Earth Observation data from a reference-image database, corresponding to the DEIMOS-2 VHR optical satellite and the multispectral SEVIRI instrument on the MSG satellite. Ground truth information from multiple sources is used in the verification phase. Furthermore, the performance of the initial algorithms is compared with those obtained in the Hardware, thus obtaining an evaluation of the effect of the Hardware implementation. © 2021 EO-ALERT All Rights Reserved

An important challenge faced by mission-critical computers is the ability to scale the processing performance, while maintaining a high level of dependability in a harsh environment. The adoption of COTS multi-core processors, as in non-critical industries, poses difficulties both in terms of timing interference due to concurrent access to shared hardware resources, and reliability under thermal and radiation stress. Specific dependability-related features are thus required for space computers. In this domain, the LEON processors [1] are a European success-story, adopting an open architecture, being available as open-source implementations to allow validation by a wide user base, and having fault-tolerant implementations available to support missions with high-reliability requirements. The recent RISC-V [2] open-source instruction set architecture is a great opportunity to push this concept further, with a renewed potential for growth and wide adoption. The De-RISC project (Dependable Real-time Infrastructure for Safety-critical Computer) aims at providing the first complete processing platform for space, leveraging RISC-V cores and state-of-the-art hypervisor technology. The platform is composed of an FPGA-based SoC with high-performance NOEL-V cores [3], minimized interference channels and many space-grade peripherals. The SoC platform hosts both the XtratuM Next Generation (XNG) hypervisor [4] and LithOS guest operating system [5] for applications isolation and scheduling. In addition, the platform implements advanced monitoring techniques that help to ensure the real-time behaviour in a multicore context. In order to validate the platform, in addition to basic benchmarks and tests, a realistic space use-case will be deployed, based on the LVCUGEN (Logiciel de Vol Charge Utile GENerique) framework [6], the CNES generic payload software based on Time & Space Partitioning. WIth the CCSDS123 hyperspectral image compression [7] as a high-throughput application and TM/TC communications as low-latency critical application, it covers a complete mixed-critical system. The current status of the project is in line with the plans: the prototype platform is already functional and almost complete, with new features added in scheduled internal releases. The validation phase has started, and will proceed incrementally until the end of the project. The commercial release of the platform is expected for Q2 2022. References: [1] https://www.gaisler.com/index.php/products/processors/leon5 [2] https://riscv.org/ [3] https://www.gaisler.com/index.php/products/processors/noel-v [4] https://fentiss.com/products/hypervisor/ [5] https://fentiss.com/products/lithos/ [6] Julien Galizzi, Jean-Jacques Metge, Paul Arberet, Eric Morand, Fabien Vigeant, et al.. LVCUGEN (TSP-based solution) and first porting feedback. Embedded Real Time Software and Systems (ERTS2012), Feb 2012, Toulouse, France. [7] Lucana Santos Falcon, Roberto Camarero. Introduction to CCSDS compression standards and implementations offered by ESA, European Workshop on On-Board Data Processing (OBDP2019), Feb 2019, Noordwijk, Netherlands.