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This paper presents a scalable software architecture based on robot operating system 2 (ROS2) for service robots. ROS2 supports the data distribution service (DDS) protocol that provides benefits such as real-time operation and security and performance enhancements. However, ROS2 still lacks task management capabilities, essential for practical robotic applications consisting of multiple threads and processes. Moreover, integrating new devices into ROS2 requires additional development effort to create specific drivers for specific devices. The proposed software architecture addresses these drawbacks and provides a simple and user-friendly programming interface for easier integrating of various devices and existing ROS2 applications. Moreover, it is designed using python with multi-processing to avoid issues related to the python global interrupt lock (GIL). To verify the developed software architecture, an application for a custom-made service robot called the SeoulTech service robot (SSR) is implemented on a Jetson Xavier NX board with various features, such as ROS2 navigation and SLAM, text-to-speech (TTS), speech recognition, and face recognition.

Many mobile systems run on ARM-based devices today. People use these for increasingly diverse yet security-sensitive applications. ARM has adopted a security model to tackle this threat, where they manage private information in an isolated trusted execution environment (TEE) provided by TrustZone. This TrustZone-based model has been proven effective, but due to security concerns, it is available solely for the vendors applications, thereby hindering the broad use of TrustZone. Consequently, we propose a runtime framework backed by TrustZone to construct a secondary TEE. AMBASSY has its residence built on an on-chip field-programmable gate array (FPGA), which is a standard component in an ARM/FPGA hybrid system readily available on the market today. This study, to the best of our knowledge, is the first attempt to broaden the use of TrustZone by using an FPGA to build a secondary TEE for arbitrary third-parties, which otherwise should be expelled to the Normal World. This paper describes many design challenges that we have overcome to fully implement AMBASSY on an FPGA. Our experiments demonstrate the practicality of AMBASSY by presenting the security analysis and performance results of third-party application samples. The samples all run safely on AMBASSY, with shorter execution time than regular TEE applications in TrustZone (by a factor of 5.552).

Embedded SoC System verification have become chief challenge in recent years due to increase in complex architectures and software’s. Even though SoC caters the needs for implementing the complex architectures, verification still remains crucial in terms of the accuracy, time computation and most importantly complex methodologies. Several methodologies were proposed, one such is Universal Verification Methodology (UVM), which occupies the major role in the SoC verification, UVM needs brighter light of research for the better improvisation in terms of the testing features and time of computation. Hence HUM (Hybrid Universal Methodology) was proposed with idea of extending the UVM by integrating the Fault Injection Systems along with Intelligent Predictors. The proposed tool has been tested with the IoTWireless Transceivers algorithms. The algorithms are targeted for the ARM architectures and results proved to be more vital.

Generally the accelerators type identifies the edge computing performance hugely and it includes Integrated Circuit (IC), Graphical Processing Unit (GPU) and Field Programmable Gate Array (FPGA). Among these accelerator FPGAs are widely used in several edge computing areas since it has the ability to reconfigure and has high energy efficient. The consequence also comes out with the paradigm of scheduling efficiency on CPU’s (software tasks) and FPGA (hardware tasks). However the conventional schemes not entirely exploited the variations among hardware and software tasks which results in low scheduling efficiency. Therefore a task scheduling system is proposed on basis of fully active reconfigurable system. The scheduling efficiency for the proposed scheme can be increased by switching the task overheads and by predicting the execution time for hardware with minimum task switching times.

Bu çalışmada, endüstride yaygın bir şekilde kullanılan ve bu nedenle kestirimci bakım tedbirlerinin alınması önem arz eden asenkron motorlarda (ASM) meydana gelebilecek arızaların ön kestirimlerinin yapılması için endüstriyel nesnelerin interneti (IIoT) tabanlı bir sensör kartı sistemi gerçekleştirilmiştir. Gerçekleştirilen sistem 3 fazlı 250 kW gücünde ve 315L gövde yapısındaki bir ASM üzerinde denenmiştir. Bu ASM’un bulunduğu şartlar geliştirilen gömülü sistemde bulunan sensörlerle algılanmış, gömülü sistem ile bir bulut ağına aktarılmıştır. Sensör kartı uygulamasında Wi-Fi ve Bluetooth haberleşme protokollerini içeren ESP-WROOM-32 mikrodenetleyicisi, frekansa bağlı oluşan titreşim verilerini üç eksende tespit eden bir LIS3DH ivmeölçer ve sıcaklık verileri için 10 KΩ değerinde NTC ASM’un üzerine montajlanmıştır. Bu sensör verileri değerlendirilerek ASM’da oluşabilecek kestirimci bakım tespitleri yapılmış ve ASM için bu tespitler ile kullanıcılara uyarı gönderecek kestirimci bakım kararları oluşturulmuştur., In this study, an industrial internet of things (IIoT) based sensor card system has been developed to predict the failures that may occur in induction motors (IMs), which is widely used in the industry and therefore it is important to take predictive maintenance measures. The realized system has been tested on a 3-phase IM with 250 kW power and 315L body structure. The conditions of this IM were detected by the sensors in the embedded system and transferred to a cloud network with the embedded system. The ESP-WROOM-32 microcontroller, which includes Wi-Fi and Bluetooth communication protocols in the sensor card application, is mounted on a LIS3DH accelerometer that detects frequency-dependent vibration data in three axes and NTC IM at 10 KΩ for temperature data. By evaluating these sensor data, predictive maintenance determinations that may occur in the IM were made and predictive maintenance decisions were made for the IM to send warnings to the users with these detections.

Technological advancement has decreased network latencies while simultaneously increasing local latencies. This may impact exergames-video games that incorporate exercise-the most since exergames tend to have complicated platforms to capture player actions. This article presents a study using a custom desktop-based exergame that controls for local latency and measures player performance and quality of experience (QoE). Analysis of the results from a 37-person user study shows that while player performance and QoE degrade with latency, exergame actions are fairly tolerant of even hundreds of milliseconds of latency. Our data point toward a crucial tipping point at latency values of approximately 400 ms.

In this paper, an embedded system is used as a host for the intercom and as a chatbot server for this system. The chatbot server controls door locks, cameras, buzzers, and related devices through web services on the WoT (Web of Things) to provide residents and visitors with better functionality and integrational services. This system can greatly improve the security and convenience of the system compared with the traditional intercom system. The resident uses the instant messaging software of the smartphone to replace the handset function, and there is no need to install and learn new apps, reducing the cost of the handset and the wiring indoors and outdoors. Whether or not the residents are at home, they can check whether there are visitors and check the status of their doors through their smartphones. Conversely, any visitor can also contact the resident through this intercom, while there is no way to confirm whether the resident is at home or not, which enhances the security of the house. This system provides flexibility in wireless installation and use and sufficient mobility for residents. The system architecture strikes a good balance between user convenience and home security and between performance and cost, effectively improving home security and reducing costs.

Purpose Primary Health Care (PHC) is the coordinator of health care in Brazil and needs to be strengthened in the diagnostic field to increase health care quality. Aiming to improve the diagnostic tools currently available in PHC, this work describes the process of development and validation of two point-of-care biomedical devices for screening patients with syphilis or different kinds of cancer. Methods The development of these devices followed nine stages of action based on the requirements established by the Ministry of Health. During development, both systems followed the stages of circuit planning, software simulation to verify the components used, cost assessment for the acquisition of features, simulation in contact matrix, development of the embedded system, and planning of the printed circuit board and storage box. Results Both devices underwent preliminary functionality tests to assess their quality. The performance tests applied on the device to diagnose syphilis performed 8,733,194 requests, with a flow of 2426 requests/second, reaching the desired parameters of robustness, integrity, durability, and stability. In addition, functioning tests on the cancer-screening device indicated the ability to detect standard fluorescence in a minimal (150 uL) sample volume. Conclusions Together, the methodology used for developing the devices resulted in promising equipment to improve the diagnosis and meet the requirements for executing technologies for testing and triaging patients in PHC.

Extensive research efforts are being carried out to evaluate and improve the reliability of computing devices, either through beam experiments or simulation-based fault injection. Unfortunately, it is still largely unclear to which extend fault injection can provide an accurate error rate estimation at early stages and if beam experiments can be used to identify the weakest resources in a device. The challenges associated with reliability evaluation grow with the increase of complexity of the hardware and the software. In this paper, we combine and analyze data gathered with extensive beam experiments (on the final physical CPU hardware) and microarchitectural fault injections (on early microarchitectural CPU models). We target a standalone Arm Cortex-A5 and an Arm Cortex-A9 integrated in an SoC and evaluate their reliability in bare-metal and Linux-based configurations. We find that both the SoC integration and the OS presence increase the system DUEs (Detected Unrecoverable Errors) rate (for different reasons) but do not significantly impact the SDCs (Silent Data Corruptions) rate which is solely attributed to the CPU core. Our reliability analysis demonstrates that, even considering SoC integration and OS inclusion, early, pre-silicon microarchitecture-level fault injection delivers accurate SDC rates estimations and lower bounds for the DUE rates.

Games are energy-intensive applications on mobile devices. Optimizing the energy efficiency of games is hence critical for battery-limited mobile devices. Although the advent of energy-aware scheduling (EAS) integrated in recent devices has provided opportunities for improved energy management, the framework is not specifically tuned for game applications. In this paper, we aim to improve the energy efficiency of game applications running on EAS-enabled mobile devices. To this end, we first analyze the functional characteristics of games, and investigate the source of the energy inefficiency. We then propose a scheme, called System-level Energy-optimization for Game Applications (SEGA), to improve the energy efficiency of games. SEGA governs CPU and GPU power consumption in a tightly coupled manner by employing three key techniques: (1) Gsync-aware GPU DVFS governor, (2) adaptive capacity clamping, and (3) on-demand touch boosting. We implemented SEGA on the latest Android-based smartphones. The evaluation results for 23 popular games showed that SEGA reduced the energy consumption of the Google Pixel 2 XL and Samsung Galaxy S9 Plus smartphones, at the device level, by 6.1-22.3% and 4.0-11.7%, respectively, with a quality of service (QoS) degradation of 1.1% and 0.5%, on average.

Low power consumption, real-time computing, and high reliability are three key requirements/design objectives of real-time embedded systems. The standby-sparing technique can improve system reliability while it might increase the temperature of the system beyond safe limits. In this paper, we propose a thermal-aware standby-sparing (TASS) technique that aims at maximizing the Quality of Service (QoS) of soft real-time tasks, which is defined as a function of the finishing time of running tasks. The proposed technique tolerates permanent and transient faults for multicore real-time embedded systems while meeting the Thermal Safe Power (TSP) as the core-level power constraint, which avoids thermal emergencies in on-chip systems. Our TASS proposed method provides an opportunity to remove the overlaps of the execution of main and backup tasks to prevent extra power consumption due to applying the fault-tolerant technique. Meanwhile, in order to maximize the QoS, we employ a heterogeneous platform to execute the main tasks as soon as possible on high-performance cores with more power budget. Experiments show that our proposed method improves QoS up to 39.78% (on average by 18.40%) and reduces the peak power consumption and temperature by up to 40.21% and 15.47C (on average 28.31% and 13.60C), respectively, at runtime, while keeping the system reliability at the required level.

The ongoing trend from mass-produced to mass-customized products with batch sizes as small as a single unit has highlighted the need for highly adaptable robotic systems with lower downtime for maintenance. To address these demands, this article proposes the development of a novel reconfigurable collaborative robot (cobot), which has the potential to open up many new scenarios within the rapidly emerging flexible manufacturing environments. As the technological contribution, we present a complete hard- and software architecture for a quickly reconfigurable EtherCAT-based robot. This novel approach allows to automatically reconstruct the topology of different robot structures, composed of a set of body modules, each of which represents an EtherCAT slave. As the theoretical contribution, we propose a method to obtain in an automatic way the kinematic and dynamic model of the robot and store it in universal robot description format (URDF) as soon as the physical robot is assembled or reconfigured. The method also automatically reshapes a generic optimization-based controller to be instantly used after reconfiguration. While this article focuses on reconfigurable manipulators, the proposed concept can support arbitrary serial kinematic tree-like configurations. We demonstrate the contributions with examples of the following: how the topology of the robot is reconstructed and the URDF model is generated, and a Cartesian task application for a cobot built with the basic modules, demonstrating the quick reconfigurabilty of the system from a 4-degrees-of-freedom (DOF) robot to a 5-DOF robot, in order to satisfy new workspace requirements.

Основним напрямом розвитку сучасного приладобудування є створення компактних інтелектуальних датчиків і приладів на базі однокристальних мікроконтролерів які реалізують багатозадачну функціональність. Для програмного забезпечення таких мікроконтролерів критичним є забезпечення режиму реального часу їх функціонування в умовах мінімальних обчислювальних ресурсів з урахуванням критичного часу виконання кожної з задач які відповідний датчик чи прилад реалізує. Метою роботи є реалізація паралельної багатозадачності в системах реального часу на базі однокристального мікроконтролера. Реалізація поставленої мети передбачає вирішення завдання створення програмного механізму, що забезпечує паралельне скоординоване виконання декількох задач одночасно при мінімальних обчислювальних ресурсах, з урахуванням обмежень на час реакції системи, що побудована на однокристальному мікроконтролері, на зовнішні і внутрішні події. Методологія вирішення поставленого завдання полягає в виділенні основних типів задач в системах реального часу і створення механізму координації їх виконання, який потребує мінімум обчислювальних ресурсів мікроконтролера. Наукова новизна. У статті показано, що використання принципу примусової багатозадачності, який заснований на квантуванні часу і використанням алгоритму диспетчеризації з плануванням, що витісняє задачі за пріоритетом, дозволяє реалізувати режим реального часу і квазіпаралельної багатозадачності в системах на однокристальних мікроконтролерах з мінімальними обчислювальними ресурсами. Висновки. Використання запропонованого механізму реалізації паралельної багатозадачності для однокристальних мікроконтролерів дозволяє ефективно розділити обчислювальні ресурси між задачами, забезпечити функціонування системи на базі мікроконтролера в режимі реального часу і мінімізувати затрати часу на узгодження окремих програмних модулів при їх доробці.

As interconnects dominate circuit performance in modern FPGAs, placement becomes a crucial stage for timing closure. Traditional FPGA placers seldom consider the timing constraints, and thus may lead to illegal routing solutions. In this paper, we present an incremental timing-driven placement flow for advanced FPGAs. First, a timing-based global placement strategy is designed to guide heterogeneous blocks to desired locations with satisfied timing constraints. Then, a timing-aware packing algorithm is developed to mitigate the design complexity while improving the timing results. Finally, we propose a critical path-based optimization method to generate optimized layout without timing violations. We evaluate our algorithm based on industrial circuits using an advanced FPGA device. The experimental results show that our placer achieves an 5.1% improvement in worst slack, and produces placements that require 16.7% less time to route when compared with the leading commercial tool Xilinx Vivado.

In this paper, we present an efficient 3D display technique that employs current 2D TV channels. First, a gradient background depth is generated for the still region. To create a stereo effect, multiple objects are detected and segmented using the binary format. Object depth is estimated according to the object size and its location. Depth value is assigned as a proportion of the object size using the linear quantitative method. Each object size is calculated and its depth value is proportional to the size parameter. If an object is the largest one and is located in the central region, the maximum depth value is assigned. For real-time implementation, dual ARM cores perform the task using the algorithm of the proposed stereo conversion. Our results show that a low-cost embedded system can perform the proposed 3D algorithm, with a processing time of 43ms per frame. The signal from a TV channel can be sampled and converted to a 3D format display on a conventional LCD screen.

Spin transfer torque magneto-resistive random-access memory (STT-MRAM) has many advantages, such as scalability, persistence, practically infinite endurance, and fast access speed, that make it a promising and emerging technology for memory. However, this technology has multiple reliability issues such as read and write reliability, higher write power, and long write latency, etc. At elevated temperatures, these issues exacerbate further. As the temperature increases massively in the latest compute nodes, we need to study and understand the effect of temperature on STT-MRAM memory writes and reliability. In this paper, we propose temperature-aware memory controller and device architecture techniques specific to STT-MRAM technology, that can improve write reliability, retention reliability, and memory power without sacrificing the performance. Our simulation results show that the proposed techniques cumulatively improve write BER on an average by 603X, increase retention reliability by 65%, along with 27% power reduction and 5.8% improved system performance over the baseline STT-MRAM based memory subsystem.

Using less electric power or speeding up processing is catching the interests of researchers in deep learning. Quantization has offered distillation mechanisms that substitute floating numbers for integers, but little has been suggested about the floating numbers themselves. The use of Q-format notation reduces computational overheads that frees resources for the introduction of more operations. Our experiments, conditioned on varying regimes, introduce automatic differentiation on algorithms like the fast Fourier transforms and Winograd minimal filtering to reduce computational complexity (expressed in total number of MACs) and suggest a path towards the assistive intelligence concept. Empirical results show that, under specific heuristics, the Q-format number notation can overcome the shortfalls of floating numbers, especially for embedded systems. Further benchmarks like the FPBench standard give more details by comparing our proposals with common deep learning operations.

Graphics Processing Units (GPUs) are now a key component of many devices and systems, including those in the cloud and data centers, thus are also subject to side-channel attacks. Existing side-channel attacks on GPUs typically leak information from graphics libraries like OpenGL and CUDA, which require creating contentions within the GPU resource space and are being mitigated with software patches. This paper evaluates potential side channels exposed at a lower-level interface between GPUs and CPUs, namely the graphics interrupts. These signals could indicate unique signatures of GPU workload, allowing a spy process to infer the behavior of other processes. We demonstrate the practicality and generality of such side-channel exploitation with a variety of assumed attack scenarios. Simulations on both Nvidia and Intel graphics adapters showed that our attack could achieve high accuracy, while in-depth studies were also presented to explore the low-level rationale behind such effectiveness. On top of that, we further propose a practical mitigation scheme which protects GPU workloads against the graphics-interrupt-based side-channel attack by piggybacking mask payloads on them to generate interfering graphics interrupt ``noises’'. Experiments show that our mitigation technique effectively prohibited spy processes from inferring user behaviors via analyzing runtime patterns of graphics interrupt with only trivial overhead.

Deep learning has been proved to be one of the most effective method in feature encoding for different intelligent applications such as video based human action recognition. However, its non-convex optimization mechanism leads large memory consumption, which hinders its deployment on the smart embedded systems with limited computation resources. To overcome this challenge, we propose a novel deep model compression technique for smart embedded systems, which realizes both the memory size reduction and inference complexity decrease within a small drop of accuracy. First, we propose an improved naive Bayes inference based channel parameter pruning to obtain a sparse model with higher accuracy. Then, to improve the inference efficiency, the improved Tucker decomposition method is proposed, where an improved genetic algorithm is used to optimize the Tucker ranks. Finally, to elevate effectiveness of our proposed method, extensive experiments are conducted. The experimental results show that our method can achieve the state-of-the-art performance compared with existing methods in terms of accuracy, parameter compression and floating point operations reduction.

Indoor occupancy estimation is a process that contributes to maintaining quality standards in areas, and, nowadays, it serves as a reference to identify possible foci of infectious respiratory diseases contagion. This paper presents a tool for indoor occupancy estimation with Simple Mail Transfer Protocol notification, using a Raspberry Pi embedded board. The system is presented as an alternative to conventional occupancy estimation systems by measuring CO2 levels in the area. The method is based on image processing by applying the background subtraction technique using Python programming language. Initially, the area where the system is tested is characterized, and preprocessing, filtering, and thresholding stages are applied, as well of notification via e-mail for SMTP. The developed system is compared with a CO2 measurement system by applying a prioritization matrix comparing factors such as detection time, hit rate, and implementation costs. The proposed method presented better performance in the totality of the comparison parameters, with a prioritization of 87.972%. Basing the system in open-source software tools and high level and low-cost hardware tools allows for the system to be replicated and implemented on a large scale in controlled environments. RESUMEN La estimación de ocupación en espacios interiores es un proceso que contribuye a mantener estándares de calidad en las zonas, y que, al día de hoy, sirve como referencia para identificar posibles focos de contagio de enfermedades respiratorias infecciosas. Este artículo presenta una herramienta para la estimación de ocupación en espacios interiores con notificación mediante el Protocolo Simple de Transferencia de Correo (SMTP) usando una placa embebida Raspberry Pi. El sistema se presenta como alternativa a los sistemas convencionales de estimación de ocupación midiendo los niveles de CO en la zona. El método se basa en procesamiento de imágenes aplicando la técnica de sustracción de fondo mediante lenguaje de programación Python. Inicialmente, se caracteriza la zona donde se prueba el sistema, y se aplican etapas de preprocesamiento, filtrados y umbralización, además de notificación vía correo electrónico por SMTP. El sistema desarrollado se compara con un sistema de medición de CO2 aplicando una matriz de priorización comparando factores como el tiempo de detección, tasa de aciertos y costos de implementación. El método propuesto presentó mejor rendimiento en la totalidad de los parámetros de comparación, con una priorización de 87.972 %. Basar el sistema en herramientas de software de código abierto y herramientas de hardware de alto nivel y bajo costo permite replicar e implementar el sistema a gran escala en ambientes controlados.

Due to recent explosion of data volume and velocity, a new array of lightweight key-value stores have emerged to serve as alternatives to traditional databases. The majority of these storage engines, however, sacrifice their read performance in order to cope with write throughput by avoiding random disk access when writing a record in favor of fast sequential accesses. But, the boundary between sequential vs. random access is becoming blurred with the advent of solid-state drives (SSDs). In this work, we propose our new key-value store, LogStore, optimized for hybrid storage architectures. Additionally, introduce a novel cost-based data staging model based on log-structured storage, in which recent changes are first stored on SSDs, and pushed to HDD as it ages, while minimizing the read/write amplification for merging data from SSDs and HDDs. Furthermore, we take a holistic approach in improving both the read and write performance by dynamically optimizing the data layout, such as deferring and reversing the compaction process, and developing an access strategy to leverage the strengths of each available medium in our storage hierarchy. Lastly, in our extensive evaluation, we demonstrate that LogStore achieves up to 6x improvement in throughput/latency over LevelDB, a state-of-the-art key-value store

The design and manufacturing steps of a chip typically involve several parties. For example, a chip may comprise several third-party Intellectual Property (IP) cores and the Integrated Circuit (IC) fabrication may be outsourced to a third-party foundry. IP cores and ICs are shared with potentially untrusted third parties and, as a result, are subject to piracy attacks. Even more, any legally purchased chip may be reverse-engineered to retrieve the design down to transistor-level and, thereby, it is also subject to piracy attacks. In this paper, we propose MixLock, an anti-piracy countermeasure for mixed-signal IP cores and ICs. MixLock protection is based on inserting a lock mechanism into the design such that correct functionality is established only after applying a key which is the designer’s secret. The lock mechanism acts on the mixed-signal performances by leveraging logic locking of the digital part. MixLock presents several key attributes. It is generally applicable, it is non-intrusive to the sensitive analog section, it incurs no performance penalty and has very low area and power overheads, it is fully automated, and it is capable of co-optimizing security in both the analog and digital domains. We demonstrate MixLock on a Σ Analog-to-Digital Converter (ADC) using hardware measurements and an audio demonstrator.

Phase Change Memory (PCM) can directly connect persistent memory to main memory bus, while it achieves high read throughput and low standby power, the critical concerns are its poor write performance and limited durability. A naturally in-spired design is the hybrid memory architecture that fuses DRAM and PCM, so as to exploit the positive aspects of both types of memory. Unfortunately, existing solutions are seriously challenged by the limited main memory size, which is the primary bottleneck of in-memory computing. In this paper, we introduce a novel Content Aware Hybrid DRAM-PCM memory system framework—CAHRAM, which exploits deduplication to improve line sharing with high memory efficiency. It reduces write traffic to hybrid memory by removing unnecessary duplicate line writes, thereby further enhancing the write endurance of PCM. And it also substantially extends available free memory space by coalescing redundant lines in hybrid memory. We also design a reference-based page migration technique to minimize the access overheads caused by the performance gap between DRAM and PCM. Compared with the state-of-the-art in a hybrid memory simulator, our experiment results show that CAHRAM can achieve the highest I/O performance and the longest PCM lifetime with the competitive efficiencies in space and energy.

As multiple software components with different safety-criticality levels are integrated on a shared computing platform, a real-time embedded system becomes a mixed-criticality (MC) system, which should provide timing guarantees at all different levels of assurance to software components with different criticality levels. In the real-time systems community, the concept of an MC system is regarded as a promising, emerging solution to solve an inherent challenge of real-time systems: pessimistic reservation of computing resources, which yields a low resource-utilization for the sake of guaranteeing timing requirements. Since a timing guarantee should be provided before a real-time system starts to operate, its feasibility has been extensively studied for single-criticality systems; however, the same cannot be said for MC systems. In this article, we develop necessary feasibility tests for MC real-time embedded systems, which is the first study that yields non-trivial results for MC necessary feasibility on both uniprocessor and multiprocessor platforms. To this end, we investigate characteristics of MC necessary feasibility conditions, and identify new challenges posed by the characteristics. By addressing those challenges, we develop two collective necessary feasibility tests and their simplified versions, which are able to exploit a tradeoff between capability in finding infeasible task sets and time-complexity. The simulation results demonstrate that the proposed tests find a number of additional infeasible task sets for both uniprocessor and multiprocessor platforms, which have been proven neither feasible nor infeasible by any existing studies.

The rapid growth of the globalized integrated circuit (IC) supply chain has drawn the attention of numerous malicious actors that try to exploit it for profit. One of the most prominent targets of such parties is the third-party intellectual property (3PIP) vendors and their circuit designs. With the increasing number of transactions between vendors and system integrators, the threat of IP reuse and piracy has become a significant consideration for the IC industry. What is more, the correctness of 3PIP designs should be verified before integration, imposing another challenge for 3PIP vendors since they have to prove the functionality of their designs to system integrators while protecting the privacy of the circuit implementations. To eliminate this deadlock, we utilize the cryptographic technique of “zero-knowledge proofs” to enable 3PIP vendors to convince system integrators about various functional properties of a circuit (e.g., area, power, frequency) without disclosing its netlist (i.e., in zero-knowledge). Our approach comprises a circuit compiler that transforms arbitrary netlists into a zero knowledge-friendly format and a library of modules that provide cryptographic guarantees for various properties of the netlist while hiding the actual gates. We evaluate our method using combinational and sequential circuits from the ISCAS and ITC benchmark suites.

Data protection is a severe constraint in the heterogeneous IoT era. This article presents a Hardware-Software Co-Simulation of AES-128 bit encryption and decryption for IoT Edge devices using the Xilinx System Generator (XSG). VHDL implementation of AES-128 bit algorithm is done with ECB and CTR mode using loop unrolled and FSM-based architecture. It is found that AES-CTR and FSM architecture performance is better than loop unrolled architecture with lesser power consumption and area. For performing the Hardware-Software Co-Simulation on Zedboard and Kintex-Ultra scale KCU105 Evaluation Platform, Xilinx Vivado 2016.2 and MATLAB 2015b is used. Hardware emulation is done for grey images successfully. To give a practical example of the usage of proposed framework, we have applied it for Biomedical Images (CTScan Image) as a case study. Security analysis in terms of the histogram, correlation, information entropy analysis, and keyspace analysis using exhaustive search and key sensitivity tests is also done to encrypt and decrypt images successfully., Comment: The manuscript is accepted in IEEE Consumer Electronics Magazine . 6 pages in double column format. A total of 4 figures

Stack-based memory corruption vulnerabilities have been exploited, allowing attackers to execute arbitrary code and read/write arbitrary memory. Although several solutions have been proposed to prevent memory errors on the stack, they are either limited to a specific type of attack (either spatial or temporal attacks) or cause significant performance degradation. In this paper, we introduce SaVioR, an efficient and comprehensive stack protection mechanism. The key technique involves randomization of the stack layout to reduce its predictability and exploitability. SaVioR isolates an individual object from spatially and temporally adjacent vulnerable objects and randomizes each object's location, which prevents attackers from predicting the stack layout and thus reduces the likelihood of memory errors being exploited. We implemented SaVioR based on the LLVM compiler framework and applied it to the SPEC CPU2006 benchmarks and real-world applications. Our security evaluation showed that SaVioR provides a high degree of randomness in the stack layout and thus reduces the likelihood of successful exploitation of spatial and temporal memory errors on the stack. Our performance evaluation also demonstrated that it incurs a modest performance overhead (13%) with the SPEC CPU2006 benchmark suite, which improves performance compared to the state-of-the-art stack protection while achieving a comparable security level.

In this paper, we propose PUF-RAKE, a physically unclonable function (PUF) based lightweight, highly reliable authentication and key establishment scheme. The proposed PUF-RAKE is robust against masquerade, brute force, replay, and modeling attacks. In PUF-RAKE, we introduce an inexpensive yet secure stream authentication scheme inside the device which authenticates the server before the underlying PUF can be invoked. This prevents an adversary from brute forcing the device's PUF to acquire challenge-response pairs (CRPs) essentially locking out the device from unauthorized model generation. Additionally, we also introduce a lightweight CRP obfuscation mechanism involving XOR and shuffle operations. The security of PUF-RAKE has been formally verified. A prototype of the protocol has been implemented on two Xilinx Zynq 7000 system-on-chips. Observations, security analysis and results verify that the PUF-RAKE is secure against a probabilistic polynomial time adversary under both the unauthenticated link and authenticated link adversarial models while providing ~99% reliable authentication. In addition, PUF-RAKE provides a reduction of 60% and 72% for look-up tables (LUTs) and register count, respectively, in the programmable logic (PL) part of the Zynq 7000 as compared to a recently proposed approach while providing additional advantages.

The security of computers is at risk because of information leaking through their power consumption. Attackers can use advanced signal measurement and analysis to recover sensitive data from this side channel. To address this problem, this paper presents Maya, a simple and effective defense against power side channels. The idea is to use formal control to re-shape the power dissipated by a computer in an application-transparent manner---preventing attackers from learning any information about the applications that are running. With formal control, a controller can reliably keep power close to a desired target function even when runtime conditions change unpredictably. By selecting the target function intelligently, the controller can make power to follow any desired shape, appearing to carry activity information which, in reality, is unrelated to the application. Maya can be implemented in privileged software, firmware, or simple hardware. In this paper, we implement Maya on three machines using privileged threads only, and show its effectiveness and ease of deployment. Maya has already thwarted a newly-developed remote power attack.

International audience; Since several decades, fault tolerance has become a major research field due to transistor shrinking and core number increasing in System-on-Chip (SoC). Especially, faults occurring to Network-on-Chips (NoCs) of those systems have a significant impact, due to the high amount of data, crossing the NoC, for the communication among Intellectual Properties (IPs). Furthermore, existing fault tolerant approaches cannot efficiently deal with several permanent faults, which occur in NoC routers. To address these limitations, we propose the Bit Shuffling meThod (BiSuT) for fault tolerant NoCs that reduces the impact of faults on data communications. To achieve that, the proposed approach exploits, at run-time, the position of permanent faults and changes the order of bits inside a flit. Our method reduces, as much as possible, the impact of faults by transferring the faults on Least Significant Bits (LSBs), instead of keeping them on Most Significant Bits (MSBs). The results obtained by extensive evaluations show that BiSuT can reduce the impact of multiple permanent faults, with low hardware costs, compared to existing approaches, like Hamming code.

The cost of transferring data between the off-chip memory system and compute unit is the fundamental energy and performance bottleneck in modern computing systems. Furthermore, with the advent of emerging data-intensive applications and technology scaling, this bottleneck has continuously increased. To overcome these difficulties, Near Memory Processing (NMP) based on 3D die stacking becomes a potential technology to transform the computation-centric system towards memory-centric system. In this work, we explore the feasibility and efficacy of a NMP architecture based on an emerging Non-Volatile Memory technology (NVM) for data-intensive applications and compare it with the conventional 3D-stacked NMP architecture based on DRAM. We demonstrate the effectiveness of our approach with experimental results.

With the development of computer architecture, even for embedded systems, GPU devices can be integrated, providing outstanding performance and energy efficiency to meet the requirements of different industries, applications, and deployment environments. Data analytics is an important application scenario for embedded systems. Unfortunately, due to the limitation of the capacity of the embedded device, the scale of problems handled by the embedded system is limited. In this paper, we propose a novel data analytics method, called G-TADOC, for efficient text analytics directly on compression on embedded GPU systems. A large amount of data can be compressed and stored in embedded systems, and can be processed directly in the compressed state, which greatly enhances the processing capabilities of the systems. Particularly, G-TADOC has three innovations. First, a novel fine-grained thread-level workload scheduling strategy for GPU threads has been developed, which partitions heavily-dependent loads adaptively in a fine-grained manner. Second, a GPU thread-safe memory pool has been developed to handle inconsistency with low synchronization overheads. Third, a sequence-support strategy is provided to maintain high GPU parallelism while ensuring sequence information for lossless compression. Moreover, G-TADOC involves special optimizations for embedded GPUs, such as utilizing the CPU-GPU shared unified memory. Experiments show that G-TADOC provides 13.2× average speedup compared to the state-of-the-art TADOC. G-TADOC also improves performance-per-cost by 2.6× and energy efficiency by 32.5× over TADOC.

In-memory computing is recognized as one of the most promising architecture solution to realize energy-efficient neural network inference. Amongst many memory technology, Resistive RAM (RRAM) is a very attractive device to implement the IMC-based neural network accelerator architecture, which is particularly suitable for power-constrained IoT systems. Due to the nature of low leakage and in-situ computing, the dynamic power consumption of dot-production operations in RRAM crossbars dominates the chip power, especially when applied to lowprecision neural networks. This work investigates the correlation between the cell resistance state and the crossbar operation power, and proposes a State-Aware RRAM Accelerator (SARA) architecture for energy-efficient low-precision neural networks. With the proposed state-aware network training and mapping strategy, crossbars in the RRAM accelerator can perform in a lower-power state. Furthermore, we also leverage the proposed RRAM accelerator architecture to reduce the power consumption of high-precision network inference with both single-level or multi-level RRAM. The evaluation results show that for binary neural networks, our design saves 40.53% RRAM computing energy on average over the baseline. For high precision neural networks, the proposed method reduces 11.67% computing energy on average without any accuracy loss.

Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6x logic density, 1.5x energy efficiency, and 1.4x operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.

Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch non-cacheable SDRAM transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today’s countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, today’s countermeasures that count the frequency of activation of memory rows cannot identify the IP that launches the attack from the FPGA. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes 6.3% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA, when multiple IPs are monitored.

Code analysis has discovered that memory leaks are common in the C programming language. In the literature, there exist various approaches for statically analyzing and detecting memory leaks. The complexity and diversity of memory leaks make it difficult to find an approach that is both effective and simple. In embedded systems, costly resources like memory become limited as the system’s size diminishes. As a result, memory must be handled effectively and efficiently too. To obtain precise analysis, we propose a novel approach that works in a phase-wise manner. Instead of examining all possible paths for finding memory leaks, we use a program slicing to check for a potential memory leak. We introduce a source-sink flow graph (SSFG) based on source-sink properties of memory allocation-deallocation within the C code. To achieve simplicity in analysis, we also reduce the complexity of analysis in linear time. In addition, we utilize a constraint solver to improve the effectiveness of our approach. To evaluate the approach, we perform manual scanning on various test cases: link list applications, Juliet test cases, and common vulnerabilities and exposures found in 2021. The results show the efficiency of the proposed approach by preparing the SSFG with linear complexity.

In this paper, we present a main memory system for improving the lifetime and security of phase-change main memories. Storing encrypted data increases the bit flip rates in memory cells which adversely affects the lifetime of the phase-change memory cells. Thus, to improve the lifetime and security, the proposed system reduces the bit flip rates by introducing two techniques. The first technique is a memory side encryption which provides security against DIMM stealing attacks. To prevent unauthorized accesses, in this technique, the encrypted data is not saved in the main memory. As the second technique, we suggest an adaptive partial encryption approach which makes use of behavior tracking of the application in the CPU side to minimize the latency overhead of the first technique. Additionally, it prevents the loss of data against application-based attacks. This technique uses recurrent neural network (RNN) to do sequence classification and detect malicious applications. In addition, an auxiliary method called Periodic Encryption (PE), which overcomes the security loss in some applications induced by the low accuracy of the employed neural network, is presented. The efficacy of the proposed method is evaluated using gem5 simulator and some benchmarks. Compared to DEUCE and Crypto-Comp methods, the results for the lifetime evaluation show an average bit flip rate reduction of 11%. In addition, the security improvements against the DIMM stealing and application-based attacks are about 100% and 92.5%, respectively.