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The superior electrical and thermal characteristics of SiC MOSFETs bring major challenges to its short-circuit reliability. To fully understand its short-circuit mechanism, estimate its safe operating area, and provide guidance for circuit design, it is crucial to establish a theoretical model to quantize the relationship between circuit parameters and short-circuit behavior of SiC MOSFETs. A temperature-dependent analytical model considering the parasitic inductances, nonlinear junction capacitances, and temperature dependence of the channel current is proposed in this paper, which only uses the parameters in the datasheet or provided by manufacturers. The proposed model is established based on the analysis for each short-circuit stage in both single-device configuration and half-bridge configuration, and the quantitatively analytical results of the transient short-circuit waveforms, energy loss, and junction temperature rise can be calculated by solving the model. The accuracy of the analytical model is verified by comparing the analytical results with the experimental results. Furthermore, the effects of varied parameters on the short-circuit behavior are evaluated by the proposed analytical model. And the corresponding circuit design guidance for higher short-circuit reliability is given.

This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

Emotional intelligence plays an important role in artificial intelligence. The brain circuitry of emotion mainly includes the prefrontal cortex, the amygdala, hippocampus and et al. Many brain emotional learning models were proposed in recent years, the existing brain emotional learning models failed to consider the contextual information in practical applications, and do not discuss the corresponding circuit implementation. In this paper, a context-dependent emotional learning network and its memristive circuit implementation are introduced. The added context-dependent module is used to process the contextual information, which makes the network context-dependent when receiving the same input signals. For circuit implementation, the memristive circuit design mainly contains the amygdala module and orbitofrontal cortex module, which imitates the emotion learning process in the brain. Besides, a multi-input multi-output memristive circuit of the context-dependent emotional network is applied to multi-task classification. PSPICE simulation results verified the adaptability and flexibility of the context-dependent emotional learning network.

This paper presents design and evaluation of a Quadratic Buck Converter (QBC). A step-by-step procedure to select the converter’s component values and semiconductor device ratings is demonstrated. A prototype QBC with a simple closed loop output voltage control is constructed and experimentally evaluated. It is shown that the converter performs well within the design specification, has good output voltage regulation and fast transient response, and achieves the highest efficiency of 82%.

In view of low conduction loss and low cost, thyristors are good candidates for configuring solid state circuit breakers (SSCBs). However, due to the half-controlled characteristic of thyristors, it is difficult for the thyristor-based SSCBs (TCBs) to achieve a fully controllable current breaking capability. In this paper, a novel bidirectional TCB is proposed, which can fully control the current breaking process with simple structure and control strategy. Besides, the proposed TCB can break current without creating current surges to the source and load, thereby enhancing the reliability of direct current (dc) systems. Typical advantages of high power efficiency and low cost can also be obtained from the novel topology. Operation process and circuit design of the proposed TCB are presented. The effectiveness of the proposed solution is verified by experimental results.

Turbulent flow over a wall-mounted cube presents an important canonical problem with applications in circuit design, urban building design, or aerodynamics. Flow over a cube placed in a fully devel...

Quantum-dot Cellular Automata is a nanotechnology based circuit design technology to design efficient circuits. Serial-Parallel Multiplier is an efficient hardware circuit used in different applications ranging from simple arithmetic circuits, filters to complex cryptographic systems. In this work, an architecture that can be used for realizing Serial Parallel Multiplier in QCA is discussed. Based on that architecture, an efficient four bit serial-parallel multiplier is implemented in Quantum-dot cellular automata. The proposed multiplier is also realized using efficient shift registers and adders. Parallel and serial shift registers are introduced in the circuit to store the inputs and outputs to increase the reliability of the circuit. The proposed work is first of its kind to implement serial-parallel multiplier with shift registers to store input and output in QCA. The proposed multiplier without shift registers is efficient and at least 66% faster compared to existing designs. The 4-bit multiplier with shift registers has 2271 cells covering an area of 7.74 μm2 with 25.25 clock cycle latency. To showcase, the scalability a serial adder is also realized using Universal, Scalable and Efficient Clocking scheme.

An equivalent electrical circuit of a microstrip line (MSL) with a magnetic film was proposed. The estimation method of its circuit parameters was investigated in order to clarify a design guideline for noise suppression sheet (NSS) which was placed on the traces in electronic devices. Firstly, the effect of the complex permeability of the magnetic film on the circuit parameters was investigated by magnetic circuit analysis of the cross section of the line. Secondly, an MSL with a Co-Zr-Nb film was designed as a test bench considering the impedance matching in the signal frequency range (below 1 GHz). Then, its transmission coefficients and the conducted noise suppression was estimated. The result shows that impedance matching was successfully maintained below 1 GHz. The estimated transmission coefficients and the conducted noise suppression almost agreed with the measured ones below the effective FMR frequency of the Co-Zr-Nb film. The results indicate that the proposed equivalent circuit has the potential to estimate circuit parameters and transmission characteristics of the MSL with the magnetic film at the circuit design stage. It is also useful to clarify the design guidelines for NSS placed on the traces in electronic devices.

Approximate computing is an emerging computing paradigm offering benefits in hardware metrics, such as design area and power consumption, by relaxing the requirement for full accuracy. In circuit design, a major challenge is to synthesize approximate circuits automatically from input exact circuits requiring minimal expert input. In this work we present a method for approximate logic synthesis based on Boolean matrix factorization, where an arbitrary input circuit can be approximated in a controlled fashion. Our methodology enables automatic computation of the dominant elements, bases, of the truth table of the circuit, and later combining the bases to approximate the original truth table. Such compression can reduce the complexity of the hardware implementation significantly, while introducing variable degrees of error. Furthermore, in our approach, the factorization algorithm can be fine tuned as required by the application, to effectively improve control over degree of approximation. In this work, we provide a unified approach enabling the factorization algorithm to utilize semi-ring algebra, field algebra, and a combination of both for truth table factorization. In addition, we provide an automatic circuit partitioning approach and a design space exploration heuristic to navigate the search space. We implement our methodology using a full stack of open-source tools, and thoroughly evaluate our methodology on a number of representative circuits showcasing the benefits of our proposed methodology for approximate logic synthesis. Finally, we compare our methodology against an existing library of approximate designs and demonstrate state-of-the-art performance.

This brief presents a general technique for achieving the highest possible RO oscillation frequency accompanied by lower phase noise in an enhanced circuit design utilizing novel delay cells. The circuit architecture has the delay cells’ inputs separated by an optimized skew offset. Skew-offset optimization is attained by integrating a pre-charge/discharge auxiliary feed-forward loop into the separately driven delay cells. This technique reduces the transition time when Supply and GND are simultaneously connected/disconnected to the delay cell’s output node. When these delay cells are connected in loops to form a Ring Oscillator, they provide high performance, even/odd multi-phase signals. The proposed methodology is validated in commercial 65nm and 180nm CMOS technologies. The post-layout simulations show that the proposed designs improve the performance by modulating the delay cell output node’s charging and discharging. The operating frequency of the proposed design, e.g., for odd stage 5/7 and even stage 4/8/16 stage, is almost 50%/40%, (80%/30%/20%) higher than that of the MSSRO (Multi-Loop Skew based Single-ended Ring Oscillator) with the same number of stages. Additionally, the designs proposed for the targeted phase noise and center frequency consume around 8–20% (odd stages)/ (6–28%) (Even stages) lesser power, a lower supply sensitivity up to 9%, and lower PVT variability up to 6% compared to its equivalent stages MSSRO (3-stages single-ended RO) counterparts in 180 nm CMOS Technology.

This article is to study the system structure scheme based on Zigbee wireless transmission, and complete the overall design of the system scheme on this basis. Human motion capture systems are widely used in the creation of film and television works, motion analysis, video games, rehabilitation medicine and other fields. This article discusses the design and implementation of a human motion capture system based on MEMS sensors and Zigbee networks. The system can be installed on the human body Multiple sensor nodes in various parts obtain the movement information of the human body, and use sensor network technology to aggregate these data and upload them to the host computer. First, this article introduces the characteristics of angular velocity sensors, acceleration sensors, magneto resistive sensors and Zigbee networks. Then, this article explains the overall structure of the system, and from a theoretical point of view, explains how the system uses angular velocity sensors, acceleration sensors, magneto resistive sensors and Zigbee networks to achieve human motion capture. This part focuses on including vector observation methods and angular velocity Two posture capture methods including the integration method, and their advantages and disadvantages are analyzed. To achieve the complementary advantages of the two algorithms, a data fusion algorithm based on complementary filtering is introduced and optimized appropriately. In addition, this article also introduces the networking principles and optimization schemes of the Zigbee network in this section. After this, this article explains in detail the system hardware structure, chip selection scheme, circuit design scheme, software workflow and implementation of core programs Method. Finally, this article shows the effect of the actual work of the system, and compares it with the theory to verify the feasibility of the theory. Based on the research of MEMS sensor measurement unit and algorithm, a Zigbee-based wireless transmission test system was established. LabVIEW software with functions of data reception, attitude angle calculation, trajectory calculation, eigenvalue extraction, BP neural network recognition, display and data saving was designed and tested the whole system functions. The test results show that the wireless data transmission of Zigbee network is normal, the data detection and processing programs of the host computer are stable, and the correct identification of the human body’s motion state can be realized. The results show that compared with the existing research, our research has increased its efficiency by 10%, and its accuracy has increased by nearly 15%.

This article proposes a universal zero-voltage switching (ZVS) circuit design method for a family of interleaved dual boost diode-capacitor (IDBD) step-up converters with different voltage multiplier cell (VMC) structure and number. By utilizing one small inductor and two resonant capacitors, all the power devices in the hard-switching (HS) IDBD converters can achieve soft-switching. Besides, the increment of voltage and current stresses imposed on the semiconductor devices and passive components is minimized in comparison to the HS counterparts with the conventional SS design. Due to the voltage-clamped ability of the diode-capacitor network, the voltage stress of one switch in the constructed topologies is less than the output voltage and decreases further when the VMC number increases. Hence, the low on -state resistance switches can be used to further reduce the conduction loss. Consequently, the constructed ZVS topologies demonstrate improved efficiency with low cost and small volume. Furthermore, the high voltage gain, low-input current ripple, and low-voltage stress characteristics of the HS IDBD converters are also conserved. Finally, a 320 W prototype is built and tested to verify the theoretical analysis and efficiency improvement.

Multiphase interleaved boost diode-capacitor (MIBD) converters, as the combination of multiphase interleaved input and voltage multiplier cells (VMCs), provide a preferred solution for both high voltage gain and high-efficiency application. This article proposes a universal zero-voltage transition (ZVT) circuit design method for a family of MIBD converters with different VMC structure and cell number. Compared with other soft-switching (SS) design methods, there is no extra voltage stress for all the semiconductor devices. An auxiliary circuit consisting of two low-voltage rating switches, two diodes, two capacitors, and one small inductor is integrated into the hard-switching (HS) two-phase interleaved boost diode-capacitor (TIBD) converters to provide zero-voltage switching (ZVS) turn- on and turn- off for the main switches and zero-current switching (ZCS) turn- off for all the diodes. Besides, the auxiliary switches turn on under ZCS. All the SS is accomplished within a wide duty cycle and power rating. From the comprehensive comparison, the constructed converters’ performance exceeds that of ZVS converters published in the recent literature. Furthermore, the extendable high voltage gain, low input current ripple, low voltage stress, and simple parameter design characteristics of HS MIBD converters are also conserved. Finally, a 320-W laboratory prototype is implemented to validate the theoretical analysis.

Recently, single-phase power-decoupled current source inverters (PD-CSIs) have been proposed to eliminate the use of electrolytic capacitor (E-cap) having a short lifespan. This type of inverter also features a high-efficiency and compact circuit design via multiplexing use of circuit components. However, it is found in this paper that component sharing inevitably renders coupled switching states for incorporating charging and discharging phases of decoupling buffers, e.g. film and ceramic capacitors. The resultant effect will be a significant increase in common-mode voltage, which may lead to unpleasant leakage current. In this paper, a generalized modulation technique is proposed for the PD-CSIs to perform active power decoupling (APD) operation without generating much leakage current. The generic operating principles of the PD-CSIs are analyzed synthetically. The formation of leakage current in the coupled switching states is analyzed. The design of the proposed modulation technique, as well as the power-decoupling controller is provided. Simulation and experimental results of typical types of PD-CSIs in an 110 V AC grid are performed to verify the effectiveness of the proposed modulation scheme. With the proposed modulation scheme, the leakage current of the PD-CSI can be reduced by 56%.

The existing Pavlov associative memory circuit only realizes the simple conditioned reflex process, secondary conditional reflex can make the simple conditioning process more complicated and make the circuit more bionic, but there is a lack of relevant circuit implementation. In this paper, a Pavlov associative memory circuit with secondary conditional reflex is proposed by utilizing the memristor. The proposed circuit can respond to a conditional stimulus after initial learning and have two kinds of forgetting process. Besides, this circuit can indirectly establish conditioned reflexes through conditioned stimuli, instead of directly establishing conditioned reflex with unconditioned stimulus. The realization of secondary conditional reflex is confirmed in the PSPICE simulation results. Meanwhile, an extended classification circuit based on secondary conditioned reflex is proposed. Based on the features of objects as input, the output of the circuit is used to achieve the function of classification. The accuracy of application circuit proposed in this paper can be verified by the simulation results in PSPICE.

Piezoelectric transducers provide a bidirectional channel for converting energy from mechanical form to electrical or in the opposite direction. Various applications were developed with either of these two energy-flow processes. For example, energy harvesters take advantage of the energy flow from mechanical to electrical domains, while vibration exciters utilize that from electrical to mechanical domains. However, few designs have integrated the bidirectional energy-flow processes in a single device in the past. Such an integration is beneficial to some multifunctional applications. The key obstacle of integrated bidirectional design results from the interface circuit design, rather than the transducer. This article makes a breakthrough by proposing a bidirectional energy conversion circuit (BECC) solution for the time-sharing energy harvesting and vibration exciting purpose. It is realized by developing a new control strategy on the synchronized triple bias-flip (S3BF) piezoelectric interface circuit, which was formerly used for energy harvesting enhancement. The control logic for energy harvesting and vibration exciting modes are discussed in detail. The time-sharing multi-functional ability is validated in experiments. It is the first time to realize a compact and integrated self-excitable energy harvester by using a single interface circuit. Experiments are carried out for validating the feasibility of the BECC toward future versatile engineering designs.

Several automatic analog integrated circuit (IC) sizing tools have been proposed and successfully applied to multi-objective circuit design problems over the last two decades. However, rendering those tools yield-aware has not been fully addressed yet since inclusion of variability analysis to the optimization loop is still a bottleneck due to the tremendous trade-off between accuracy and efficiency of the synthesis process. Conventional Monte Carlo (MC) based approaches are quite accurate, but, they are highly inefficient due to cumbersome simulation effort. Even though employing enhanced sampling techniques, e.g., Latin Hypercube Sampling (LHS), exhibits slightly better efficiency, the accuracy of such approaches is still less than Monte Carlo. To palliate this problem, in this paper, we propose a novel Deep Neural Network (DNN) aided MC simulation framework for yield-aware analog circuit sizing. In the developed tool, the DNN is leveraged to develop circuit models during the optimization, which are then used to estimate the effects of variations in device dimensions without any simulation effort while some additional simulations are concurrently carried out for V t h variations. Finally, once DNN based circuit models are obtained, the simulator is replaced by those models during the MC analysis, which enables performing expanded MC for accurate yield estimations without running any simulations. To demonstrate the developed tool, three analog circuits were optimized, a single stage-active loaded amplifier, a two stage amplifier, and a voltage comparator. According to the synthesis results, the proposed approach can achieve up to 96.61% reduction in overall execution time (29x speed-up).

The design process of analog circuits is a challenging issue due to the nonidealities. Thus, analog IC design must be automated to shorten the design time and must be optimized to improve the important performance criteria, such as power dissipation, estimated chip occupation area, etc. In this work, a genetic algorithm (GA)-based approach is proposed for the low-pass filter design of IEEE 802.11n Wireless LAN. The performance criteria of OTA and CCII are modeled with an artificial neural network and transistor sizes of those blocks are determined with GA to improve the performance and to satisfy the constraints. The advantage of the proposed methodology is to eliminate infeasible solutions before starting circuit design by modeling the design constraints according to the transistor sizes allowed by production technology. The performance of the proposed method is tested with 0.18- $\mu \text{m}$ technology in CADENCE environment.

An effective overmoded circuit is proposed to support efficient interaction with two beams for the development of high power extended interaction oscillators (EIOs) toward sub-terahertz (THz) and higher frequency. The circuit design focuses on the effect of the frequency-determining parameter on mode characteristics of the $\mathrm{TM}_{{1} {n}}$ sequence. Frequency equivalence between $\mathrm{TM}_{{1} {n}}$ modes with different ${n}$ supports the mode selection for two-beam interaction. Accordingly, the TM13 mode is selected to duplicate the dispersion relation around the axial mode of $2\pi $ and ohmic loss of conventional TM11 mode used in conventional single-beam circuits. On this basis, the overmoded circuit is formed with two beams based on the TM13 mode. In order to verify its effectiveness, a 0.22-THz EIO is designed with the overmoded circuit and, most importantly, the effect of the uniformity of two beams on the EIO performance is simulated. When the current of one beam is assumed to be constant and that of another beam is increased, the power is increased linearly and then tends to be saturation. This shows good capability of the EIO in interacting with nonuniform two beams, which is critical for its stable operation. Simulation results have shown the achievement of the average power of 0.22-THz wave over 1.26 kW with double beams at 23 kV and each current of 0.2 A.

In this article, a new freewheeling circuit with a junction field-effect transistor (JFET) structure is developed to replace the traditional high voltage diode for freewheeling in the high voltage monolithic IC for the first time. The JFET structure has its pinch -off voltage lower than 40 V, and it can sustain the reverse voltage higher than 500 V in off -state. Adopting the new freewheeling circuit, the reverse recovery charge (QRR) and the peak reverse recovery current (IRRM) is decreased boffy about 89.5% and 33.6%, respectively, when the load current is 0.5 A. Based on the proposed freewheeling circuit, a deadtime control circuit is also developed in this article. By employing that control circuit, it is no need to detect the output signal state of the counter channel before controlling the deadtime, therefore the deadtime could be designed as small as possible to decrease the freewheeling loss. In this article, the high voltage monolithic IC is implemented by thick layer silicon on insulator technology. All the new devices and circuits are compatible with the technology for the traditional monolithic IC without any additional process.

For the first time, a deep learning (DL) algorithm is presented to study the effect of the source of variability on the performance of semiconductor nanodevice. This paper reports the possibility of an alternative solution of device simulation in order to optimize the source variation. It is based on the statistical distribution of work function fluctuation (WKF) on the metal gate depending on the orientation and location of metal grains. It has been revealed that the WKF of a metal gate can lead to different fluctuations in electrical characteristics. Therefore, an emerging DL algorithm, artificial neural network (ANN) is utilized to identify the appropriate WKF patterns on the metal gate that can reduce the impact of characteristic fluctuation, i.e., $\sigma V_{TH}, \sigma I_{ON}$ and $\sigma I_{OFF}$ , simultaneously. The application of the DL-ANN algorithm to multichannel gate-all-around silicon nanosheet MOSFETs is explored to suppress the effect of WKF on the characteristic fluctuation. Consequently, it can be further utilized to investigate the implication of WKF for the process variation, modeling the nanodevices and analysis of circuit design. Notably, this technique can be extended to study the diverse random sources and process variation effects for emerging nano-CMOS devices and can effectively accelerate the device simulation and optimization.

THEPURPOSE.To consider the features of development and exploitation of DC-DC power supplies for Arctic conditions, to show the key problems and existing methods of solving them, to identify prospective directions in the design of this type of devices.METODS.Theworkismainlyanover-viewwiththequestionsofconstruction,circuitdesign,controlprinciples,maintainingthermalequilibrium,choosingofelectricelementsandminiaturization.Thefirstpartofthearticleisdevotedtothereviewofscientificpublicationsandpatents,in the second part the idea of using a parallel architecture in frost-resistant power supplies is considered, giving an opportunity to adapt modular principle of device construction.RESULTS.Thearticleexaminestheissuesofadaptingthemodularapproachtothespecificsoffrost-resistantpowersupplies.Inthiswayyoucanbuilda self-healing, configurable, easy-to-repair power supply of wide application. With modular construction principle the entire electrical complex consists of parallel-connected cells, placed in one hermetic and heated case (a case with connectors on the surface, as well as the control and display units).CONCLUSION. Parallelconnectionofthecellsallowstoprovidea significant power reserve in the power supply, to perform a quick replacement of faulty modules without interrupting the power supply process, to increase/reduce the system power easily by changing the number of working cells. The system acquires special advantages, if the output voltage levels of the cells are adjustable. In this case, it is possible to build a universal configurable power supply of wide application,whichisa novelty on the market. If you group the cells on the output, you can use one power supply for several different consumers. The spare parts for the power supply are as simple as possible and consists of ready-made cells and connecting wires. The obtained results can be used in development of fault-tolerant secondary DC-DC power supplies for hard operating conditions.

Flexible electric heating elements can be integrated into cloths to provide warm for people’s working and living in low-temperature environments and can also provide hyperthermia for elderly and patients. Due to its low energy consumption, reusable, environment friendly, and pollution free, electric heating cloths have a broad market prospect. In this research, a facile method, screen printing, is used to prepare the heating element. Silver paste heating fabric with low resistivity could heat rapidly under low loaded voltage. The Ansys finite element software is used to simulate the Joule heating behavior. The results of the experiment and simulation were highly consistent. Through experiments, theoretical derivation, and simulation analysis, we found that the silver paste heating fabric has a good Joule heating behavior, and the simulation can be applied to the circuit design, implying that it will have a broad application prospect in electric heating clothing fields.

Contact-controlled devices, such as source-gated transistors (SGTs), deliberately use energy barriers at the source, and naturally, the positive temperature dependence (PTD) of drain current can be utilized for temperature sensing. We exploit the difference in drain current activation energy, which arises with contact doping in polysilicon n-type contact-controlled transistors, to demonstrate output current with either a PTD or negative temperature dependence (NTD). The range over which output current varies linearly with temperature, as well as the sensitivity, can be tailored by the choice of reference current magnitude and relative source contact properties within the current mirror. The sensing scheme simplifies the circuit design because it relies solely on thin-film transistors and it has inherent immunity to output voltage variation. This ability to tune the sign of temperature dependence allows facile integration in applications requiring homeostasis via feedback, e.g., electronic skin, in a minimal layout area and potentially with convenient reduction of patterning steps during fabrication.

Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. However, the existing solutions have been mostly constrained to linear analog signal processing, which largely limits the achievable power efficiency. In this article, we show that tasks like voice activity detection and keyword spotting can well accommodate analog feature extractor's high nonlinearity, which arises from electronic device physics and circuit design constraints. Applying this principle to a 65-nm CMOS chip implementation, we demonstrate high classification accuracy with nonlinear analog feature extraction consuming only 50 nW. At the end of digital scaling, this study may shed light on the possibility of exploiting the largely relaxed degree of freedom, i.e., linearity, in analog circuit design in the pursuit of extreme power efficiency for designing future inference sensing systems.

Memristor is considered as a promising synaptic device for neural networks because of its tunable and non-volatile resistance states, which is similar to the biological synapses. In this article, a novel network circuit based on memristor synapses is proposed for bidirectional associative memory with in-situ learning method. An analog neuron circuit is designed to emulate the cubic activation function of neural networks. A memristive synapse circuit is constructed to map both positive and negative weights on a single memristor. Moreover, an in-situ learning circuit fitting memristor's nonlinear characteristic is proposed. Feedback control strategy is incorporated in this learning circuit to adjust the resistance of the memristor and avoid the encoding error of the memristor's write voltage. The performance of the proposed network circuit is verified by the training and recalling simulations. The comparison between the proposed approach and related works is analyzed to demonstrate the advantage of the proposed circuit design.

Hardware security remains as a major concern in the circuit design ow. Logic block based encryption has been widely adopted as a simple but effective protection method. In this paper, the potential threat arising from the rapidly developing field, i.e., machine learning, is researched. To illustrate the challenge, this work presents a standard attack paradigm, in which a three-layer neural network and a naive Bayes classifier are utilized to exemplify the key-guessing attack on logic encryption. Backed with validation results obtained from both combinational and sequential benchmarks, the presented attack scheme can specifically accelerate the decryption process of partial keys, which may serve as a new perspective to reveal the potential vulnerability for current anti-attack designs.

In recent technology, the demand for 3D multiple-gate MOSFETs such as FinFETs increase. In this paper, FinFETs are explored and reviewed. The scaling of planar MOSFET below 32nm technology increases the short channel effects (SCE). To improve the concert in low-power VLSI logic circuits and reduced the SCEs, we need enhanced gate controlling over the channel by using multigate technology. Here, we have discussed numerous architecture of FINFET, the threshold voltage (Vth) and supply voltage (Vdd) optimization, optimization of fin configuration, and low power technique for FinFET domino circuits.

Domino logic circuits occupy a prominent circuit design space in the VLSI regime. The primary attributes of the domino circuits, such as high-performance operation, lesser area and lower power consumption, are found to be limited by leakage current, charge sharing and process parameter variations. Various domino logic structures have been presented in the literature to cater to the threats and thereby improve the performance. These design solutions of domino logic are found oriented toward reduction in leakage current, lowering static and dynamic power dissipation, prevention of charge sharing, increase in operating speed and robustness. These metrics are normally achieved through better keeper control mechanism or by restructuring the pull down network or by reducing the redundant switching transitions of the output. This paper sketches the domino logic style-keeper circuit designs found in the literature and reviews them in terms of the techniques employed for performance improvement. These reconfigurations of the basic domino logic circuit keeper structure reports high performance with reduced power consumption and/or improved robustness. The circuit designs and analysis have been carried out using Cadence® Virtuoso using 180 nm technology library.

This article presents a method for modeling high- ${Q}$ resonant-fin transistors with focus on circuit design simulations. The model is implemented for simulations in a SPICE-like design environment and is based on two basic properties of the resonator device: the mechanical spectral behavior and the electro-mechanical-transfer function. The spectral model operates in the mechanical pressure regime, while the mobility model converts this pressure into a mobility change inside the channel of the transistor and is hence, generating an ac current at the output of the device. The model also includes the electrical transistor characteristic for the input and the output of the resonator. This enables accurate and fast circuit simulations with a standard SPICE simulator, e.g., for the design of frequency synthesizer circuits. The model is validated against finite element method (FEM) simulations at an artificially damped quality factor of ${Q} =500$ . Also, simulation results for a quality factor of ${Q} =50$ 000 are shown, to prove the full functionality of the electrical model.

Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight for advanced technology nodes. Thus, reliability-aware circuit design is urgently needed. In this article, a new framework to perform aging-aware static timing analysis (STA) is presented for reliability analysis. The key parts of aging-aware STA flows are workload analysis and aged delay/transition calculation. For the workload analysis, a new analytical stress probability (SP) calculation model is proposed, which considers the floating effect and signal correlations. For aged delay/transition calculation, a new aging-aware model is developed, which is accessible to large industrial libraries. The results show that the proposed model achieves high accuracy in the degradation estimation and aged-path-delay calculation. Due to its high accuracy and scalability, the proposed framework is a promising solution that is compatible with commercial Electronic Design Automation (EDA) tools.

Modern microprocessors contain several special function units (SFUs) such as specialized arithmetic units, cryptographic processors, etc. In recent times, applications such as cloud computing, web-based search engines, and network applications are widely used, and place new demands on the microprocessor. Hashing is a key algorithm that is extensively used in such applications. Hashing can reduce the complexity of search and lookup from O( $N$ N ) to O( $N/n$ N / n ), where $n$ n bins are used. Hashing is typically performed in software. Thus, implementing a hardware-based hash unit on a modern microprocessor would potentially increase performance significantly. In this article, we propose a novel hardware hash unit (HU) design for use in modern microprocessors, at the microarchitecture level and at the circuit level. First, we present the design of the HU at the microarchitecture level. We simulate the HU to compare its performance with a software-based hash implementation. We demonstrate a significant speedup (up to 15×) for the HU. Furthermore, the performance scales elegantly with increasing database size and application diversity, without increasing the hardware cost. Second, we present the circuit design of the HU for use in modern microprocessors, using a 45nm technology. Our proposed hardware hash unit is based on the use of a content-addressable memory (CAM) to implement each bin of the hash table. We simulate the HU circuit and compare it with a traditional CAM design. We demonstrate an average power reduction of 5.48× using the HU over the traditional CAM. Also, we show that the HU can operate at a maximum frequency of 1.39 $GHz$ G H z (after accounting for process, voltage and temperature (PVT) variations and accounting for wiring parasitics). Furthermore, we present the delay, power and area trade-offs of the HU design with varying hash table sizes.

Conventional analog-to-information converter (AIC) frameworks employ a discrete-time synthesis sparse model to deal with analog signals, which, however, induces a challenging basis mismatch problem. In this paper, we propose a novel AIC framework, called generalized AIC (G-AIC), to tackle this issue. In the new method, an analysis sparse model is taken, for the first time, as the prior information of analog signals being sampled at sub-Nyquist rate. Through the joint optimization for the discretization operator and its analysis sparse operator, the G-AIC removes the model error between an analog signal and its equivalent discrete samples. To validate the G-AIC framework, we design a single channel G-AIC system based on switched-capacitor (SC) circuits. The circuit design is presented at the theoretical-level, the system-level, and the transistor-level. Numerical simulations demonstrate the G-AIC system can well restore an analog signal from its sub-Nyquist measurements, even though its sparse basis is unknown. Compared with two state-of-the-art AIC systems, the new design can achieve at least $2dB$ reconstruction gain. In brief, the proposed method provides a promising alternative to exploit analog signals in sub-Nyquist sampling systems.

Transistor compact model (TCM) is the key bridge between process technology and circuit design. Typically, TCM is desired to capture the nonlinear device electronic characteristics and their high-order derivatives. However, for the novel devices in advanced and future technologies, establishing TCM based on analytical equations and extracting model parameters becomes tedious. The model fitting capability for device outputs’ high-order derivatives is also limited. These drawbacks hinder fast and accurate device to circuit evaluation cycles. We develop a TCM based on multigradient neural network (MNN) using computational graph in the PyTorch framework. This MNN model is able to simultaneously capture the transistor dc/ac characteristics, such as ${I}-{V}/{Q}-{V}$ , their derivatives ( ${G}-{V}/{C}-{V}$ ), and higher order derivatives accurately. Moreover, the model architecture can be widely adapted to various device types. Based on this model scheme, software is developed to enable the automated model generation for standard SPICE simulation. Finally, the model and software are validated for novel gate-all-around (GAA) Si cold source field-effect transistors (CSFET), and 19-stage ring oscillator and two-stage operational amplifier circuit simulations have also been demonstrated. This work reduces the cycle of novel device compact model creation and circuit benchmark simulation from months or weeks to hours. In addition, it enables more precise circuit simulation for analog and RF circuits, and it provides a rapid solution for early stage design technology cooptimization (DTCO).

This paper presents new analog circuits realised using switched-capacitor technique. New phase-shifter, low-pass filter and integrator circuits are proposed employing only a single positive type cu...

The article presents a new method for diagnosing the technical condition of radio-electronic components, combining the methods of thermal diagnostics with the technologies of artificial neural networks. The structure of the method is shown, and the composition of the functional blocks is determined. The implementation of the method is a symbiosis of technologies for mathematical and simulation modeling of the technical state of a radio-electronic device with its physical tests and research of characteristics. When developing the method, specialized software tools for design and circuit design were actively used, such as Altium Designer CAD, SolidWorks, NI Multisim, the FloTHERM PCB thermal analysis module, as well as the MATLAB mathematical modeling and calculation package. With the help of these tools, a number of studies were carried out, including sets of numerical values of the power of circuit elements and temperature indicators of the printing unit, both for the correct state of the device and in states with artificially introduced defects. They, in turn, became the basis of the database of electronic node failures. To implement diagnostic procedures and identify the technical condition, an artificial neural network based on selforganizing Kohonen maps was created, its structure, parameters and algorithms of functioning were determined. The diagnostic procedure is based on the analysis of information from the fault database and its comparison with experimental data obtained as a result of a physical experiment. The results of the study showed that the network automatically classifies the characteristic defects of electronic components using the algorithms embedded in it. The list of characteristic defects in the proposed diagnostic method is limited to a discrete set of the most common faults, because, as their number increases, the use of the self-organizing Kohonen network for automatic classification becomes much more complicated and ineffective in terms of performance and reliability of identification. Among the advantages of this technology, it should be noted that the Kohonen network has the ability to convert largedimensional input data into a two-dimensional array. So, the results are easy to visualize and convenient to use when generating reports and recommendations for subsequent decision-making about the possibility of using an electronic device.

Low-power is a paramount concern in the design of ‘digital signal processor’ (DSP) for the next generation portable electronic gadgets. The quest to achieve low-power with required speed has made the researchers look into various low-power circuit design techniques. In more recent years, reversible logic (RL) has emerged as an alternative and promising technique in the design of low-power DSPs for multimedia applications. The RL finds vast applications in the fields of nanotechnology, low-power CMOS circuit design, approximate computing, optical computing, and quantum computing, etc. The full adder (FA) being a primitive element of DSP plays a significant role in the contribution of the overall power of the system under consideration. This paper presents the design and comparison of state-of-the-art 1-bit FA architectures (FAAs) using standard reversible logic gates (RLGs). The designed FAAs herein referred to as ‘Reversible-logic based FAs’ (RFAs). The functionality of RFAs has been verified through Verilog HDL based simulations using Cadence’s NC simulator. The quantum merits of each RFA have also been assessed through the quantum gate metrics (QGMs).

The paper proposes a new structure of the receiving coil, which features horizontal and vertical position detection of inspection robot, which eliminates the system dependence on complex detection control circuit and simplifies the circuit design of the receiving end. The proposed design obtains the position information by comparing the induced voltage difference of the four-coil sets. Besides, the receiving coil is optimized in terms of the shape, dimension and the magnetic shielding structure by finite element analysis. Finally, the effectiveness of the receiving coil position detection is verified by the experiment with misalignment disturbance. The results illustrate the effectiveness of the four-coil system to detect the load position and the position adjustment by the adjustment control system.

Neuromorphic and bio-inspired circuits have reached considerable attention since Moore's Law is coming to its limitations. Information processing in mammalian brains takes place in a far more energy-efficient manner and significantly faster than in the best computing architecture nowadays. We propose an approach to bring those benefits to a superconducting information processing circuit. Since the computation in a neuronal network is considered as analogue and the computation as digital, the design is grown around a Josephson comparator with its inherent non-linearity in the transfer function as the central information processing unit. Furthermore, a modified version of the Josephson Transmission Line is used to realize an adaptable coupling between neuron cells. This circuit design benefits of the noise in a 4.2 K environment and is therefore more resilient to noise and switching errors than conventional digital circuits. The proposed circuit behavior in a 2-neuron configuration and the integration in a network topology will be investigated.

This article presents the investigation of circuit modelling, design, and optimization of the class-E rectifier to achieve a near-resistive impedance during a large load-range. Based on circuit modelling and impedance depiction, a circuit design concept of impedance compensation to achieve near-resistive impedance is proposed, and we selected the series inductor as the compensation network for class-E rectifiers. After an optimized design, a 6.78-MHz wireless power transfer prototype was built with applying the proposed concept and tested. The experimental results match well with the circuit modelling and validate the impedance shift can be optimized by the proposed circuit design concept. The experimental prototype achieves 87.2% dc–dc efficiency at the rated 220-W output and the phase angle shift is lower than 10 $^ \circ$ during the load decreasing from 220-W rated output to the 40-W light-load output. We also discuss the circuit design considerations and the hardware implementation of the prototype for the proposed design concept.

To improve the accuracy of astronomical data analysis, an increase in the number of output bits from the A/D converter is effective. We investigated a single-flux-quantum (SFQ) autocorrelator and an integrator that supports multiple-bit signal output from an SFQ A/D converter for astronomical data processing. The SFQ binary counter was used as the integrator that decimates the output from the SFQ autocorrelator for communication with equipment at room temperature. We designed the test circuits composed of 2-bit inputs, an autocorrelator, and an integrator that contains 5631 Josephson junctions using the 10 kA/cm^2 Nb process. We confirmed the correct operation of the test circuit with a normalized bias voltage margin of 102%–114% by the low-speed test. We obtained its correct high-speed operation up to a 55.1 GHz clock frequency. In terms of circuit design, scaling up the test circuit is easy. These results indicate the effectiveness of a high-precision and large-bandwidth radio astronomical observation using SFQ circuit technology.

In this paper, we systematize architectural and circuit design solutions applicable in the design of digital parts of multispeed transceivers of serial channels. Such variants of solutions, which allow using most of the possibilities of available technology for expanding this range, especially in its high-frequency part, are substantiated. The SpaceFibre multi-speed serial channel transceiver was designed by CMOS technology using the proposed solutions. The manufactured transceiver operates in the range of bit rates from 5 Mbps to 3.125 Gbps and, in terms of the set of measured parameters, is not inferior to the closest foreign analogs.

Security against Hardware Trojans (HT) is an important concern in integrated circuits (IC) design and fabrication. Most of the current HT detection methods are based on the golden model of circuit design. Further, some approaches require test pattern for HTs activation. In this paper, we propose SC-COTD (Sequential/Combinational Controllability and Observability features for hardware Trojan Detection), an effective hardware Trojan detection to get rid of both golden chip and test pattern limitations. SC-COTD uses both sequential and combinational testability measures to detect and locate HT signals by a machine learning approach. This method deploys an ensemble classifier based on k-means clustering. The clustering models have diverse variety in testability features along with size of clustering which inspect and reveal different aspects of netlist conventional for a collaborative scheme. The clustering results are filtered and then fed into a decision-making procedure based on majority voting to eliminate the limited flaws of each model. The evaluation results on TrustHUB benchmarks demonstrate that, SC-COTD can detect and locate HTs with 100% without any false negative, i.e., Recall = 1. Although our method has a limited number of false positive, it has the best performance in comparison to well-known previous approaches.

PURPOSE: A ratio adjustable power splitter (RAPS) circuit was recently proposed for add-on RF shimming and array-compressed parallel transmission. Here we propose a new RAPS circuit design based on off-the-shelf components for improved performance and manufacturability. THEORY AND METHODS: The original RAPS used a pair of home-built Wilkinson splitter and hybrid coupler connected by a pair of connectorized coaxial cables. Here we propose a new hybrid-pair RAPS (or HP-RAPS) circuit that replaces the home-built circuits with two commercially available hybrid couplers and replaces connectorized cables with interchangeable microstrip lines. We derive the relation between the desired splitting ratio and the required phase shifts for HP-RAPS and investigate how to generate arbitrary splitting ratios using paired meandering and straight lines. Several HP-RAPSs with different splitting ratios were fabricated and tested on the workbench and MRI experiments. RESULTS: The splitting ratio of an HP-RAPS circuit has a tan or cot dependence on the meandering line’s additional length compared to the straight line. The fabricated HP-RAPSs exhibit accurate splitting ratios as expected (

The different design trajectories have been analyzed in the design space on the basis of the new system design methodology. Optimal position of the design algorithm start point was analyzed to minimize the CPU time. The initial point selection has been done on the basis of the before discovered acceleration effect of the system design process. The geometrical dividing surface was defined and analyzed to obtain the optimal position of the algorithm start point. The numerical results of the design of passive and active nonlinear electronic circuits confirm the possibility of the optimal selection of the starting point of the design algorithm.

High level, network programming languages, like P4, enable students to gain hands-on experience in the structure of a switch or router. Students can implement the packet processing pipeline themselves, without prior knowledge of circuit design. However, when choosing a P4 programmable target for use in the classroom, instructors face a lack of options. On the one hand, software solutions, such as the behavioral model (BMv2) switch, are overly simplified and offer low performance. On the other hand, existing hardware solutions are closed source and expensive. In this paper, we present P4Pi, a new, low-cost, open-source hardware platform intended for networking education. P4Pi allows students to design and deploy P4-based network devices using the Raspberry Pi board, which has a price tag of less than many academic textbooks. We describe the high-level design of the P4Pi platform, offer some suggestions for how P4Pi could be used in the classroom, and present some additional use-cases for applications and functionality that could be developed using P4Pi.

The increase of within-die random variation accompanying continuing advancement of the semiconductor technology necessitates variation-aware approaches in circuit design and analysis. Statistical circuit modeling becomes an important means of realizing such approaches. In this article, analytical models for the within-die random variation of the inverter, NAND and NOR circuits are developed. To analyze random variation, the effective current concept is employed wherein circuit delay is approximated by the product of the load capacitance and supply voltage over two times the effective current. The standard deviation and mean of the circuit delay are expressed as functions of the standard deviation and mean of the effective and linear transistor currents. The developed model delivers easy means of evaluating delay variation of basic circuits. The model is verified by comparison to Monte-Carlo circuit simulations for 7-nm state-of-the-art FINFET technology. Relative error for NAND2 fall/NOR2 rise mean delay is less than 9% and for standard deviation is less than 6%. Relative error for inverter rise/fall mean delay is within 8%, however, error is larger for inverter delay standard deviation. The model is convenient for analyzing the dependence of the circuit delay standard deviation on the transistor width and the supply voltage and is useful for improving technology development efficiency in achieving target circuit performance.