6 results on '"Yin, Xiumei"'
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2. A robust and simple two-mode digital calibration technique for pipelined ADC
- Author
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Yang Huazhong, Yin Xiumei, Sekedi Bomeh Kobenge, and Zhao Nan
- Subjects
Spurious-free dynamic range ,Computer science ,Calibration (statistics) ,Successive approximation ADC ,Hardware_PERFORMANCEANDRELIABILITY ,Converters ,Condensed Matter Physics ,Electronic, Optical and Magnetic Materials ,law.invention ,Capacitor ,Integral nonlinearity ,law ,Hardware_INTEGRATEDCIRCUITS ,Materials Chemistry ,Electronic engineering ,Operational amplifier ,Sensitivity (control systems) ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering - Abstract
This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC). The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom (PN) sequence injection capacitors at the ADC initialization, while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation. The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain, but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors. The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology. The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process. Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage, the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB, respectively. With the calibration, the maximum integral nonlinearity (INL) of the ADC reduces from 4.75-LSB to 0.65-LSB, while the ADC core consumes 82-mW at 3.3-V power supply.
- Published
- 2011
3. A 10-bit 100-Msps low power time-interleaved ADC using OTA sharing
- Author
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Xu Lai, Yin Xiumei, and Yang Huazhong
- Subjects
Engineering ,Offset (computer science) ,business.industry ,Clock signal ,Dynamic range ,Skew ,Electrical engineering ,Linearity ,Hardware_PERFORMANCEANDRELIABILITY ,Condensed Matter Physics ,Electronic, Optical and Magnetic Materials ,law.invention ,Capacitor ,Intermediate frequency ,law ,Hardware_INTEGRATEDCIRCUITS ,Materials Chemistry ,Electronic engineering ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,business ,Communication channel - Abstract
A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers, and OTA is shared among the channels for low power dissipation. Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing, increasing the accuracy of each channel and global passive sampling respectively. The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement. The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply. Fabricated in a 180-nm CMOS process, the core of the prototype occupies an area of 2.5 × 1.5 mm2, achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.
- Published
- 2010
4. An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB
- Author
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Yin Xiumei, Yang Huazhong, Fan Hua, Wei Qi, and Kobenge Sekedi Bomeh
- Subjects
Spurious-free dynamic range ,Differential nonlinearity ,Comparator ,Computer science ,Analog-to-digital converter ,Successive approximation ADC ,Condensed Matter Physics ,Electronic, Optical and Magnetic Materials ,law.invention ,Effective number of bits ,Least significant bit ,Integral nonlinearity ,law ,Hardware_INTEGRATEDCIRCUITS ,Materials Chemistry ,Electronic engineering ,Electrical and Electronic Engineering ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION - Abstract
This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC) with a novel time-domain comparator design for wireless sensor networks. The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process. The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz. With the Nyquist input frequency, 68.49-dB SFDR, 7.97-ENOB is achieved. A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout. The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.
- Published
- 2010
5. A low power 12-b 40-MS/s pipeline ADC
- Author
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Wei Qi, Xu Lai, Yang Huazhong, and Yin Xiumei
- Subjects
Engineering ,Spurious-free dynamic range ,business.industry ,Pipeline (computing) ,Amplifier ,Transconductance ,Analog-to-digital converter ,Linearity ,Condensed Matter Physics ,Electronic, Optical and Magnetic Materials ,Power (physics) ,law.invention ,law ,Hardware_INTEGRATEDCIRCUITS ,Materials Chemistry ,Electronic engineering ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,business ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION ,Electrical efficiency - Abstract
This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages, particularly, 3-bit/stage architectures are used to improve the ADC's linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.
- Published
- 2010
6. A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR
- Author
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Wei Qi, Yang Huazhong, Han Dandan, and Yin Xiumei
- Subjects
Physics ,Spurious-free dynamic range ,Differential nonlinearity ,business.industry ,12-bit ,Electrical engineering ,Analog-to-digital converter ,Condensed Matter Physics ,Electronic, Optical and Magnetic Materials ,law.invention ,Effective number of bits ,Sine wave ,Integral nonlinearity ,law ,Materials Chemistry ,Electronic engineering ,Trimming ,Electrical and Electronic Engineering ,business - Abstract
This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious free dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3.1 × 2.1 mm2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.
- Published
- 2010
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