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In this paper, the laser radiation model is built up with TCAD (Technology Computer Aided Design) tool. And a PN junction is chosen for simulating the Single Event Effects (SEEs) induced by the pulsed laser as well as heavy ions. The transient current responses related with SEEs are simulated, and also the distributions of the electrostatic potential and carrier generation inside the device are plotted. Simulation results demonstrate that the pulsed laser can simulate single event effects effectively in spite of the different mechanisms responsible for generating electron-hole pairs between pulsed laser and heavy ions. And it is indicated that the pulsed laser simulation with TCAD is significant for the laser experiments.

In this paper, a laser radiation model based on TCAD is built up. With this model, some simulations of laser irradiating semiconductor material are presented. And also simulations of gamma ray irradiating semiconductor material are given. By comparing the simulation results the relationship between laser intensity and gamma dose rate is obtained. The results demonstrate that the laser radiation model is practicable in TCAD for reliability analysis and the laser simulation technique is reliable to simulate dose rate effect.

Heavy ions induced single event upset (SEU) sensitivity of three-dimensional integrated SRAMs are evaluated by using Monte Carlo sumulation methods based on Geant4. The cross sections of SEUs and Multi Cell Upsets (MCUs) for 3D SRAM are simulated by using heavy ions with different energies and LETs. The results show that the sensitivity of different die of 3D SRAM has obvious discrepancies at low LET. Average percentage of MCUs of 3D SRAMs rises from 17.2% to 32.95% when LET increases from 42.19 MeV cm2/mg to 58.57MeV cm2/mg. As for a certain LET, the percentage of MCUs shows a notable distinction between face-to-face structure and back-to-face structure. For back-to-face structure, the percentage of MCUs increases with the deeper die. However, the face-to-face die presents the relatively low percentage of MCUs. The comparison of SEU cross sections for planar SRAMs and experiment data are conducted to indicate the effectiveness of our simulation method. Finally, we compare the upset cross sections of planar process and 3D integrated SRAMs. Results demonstrate that the sensitivity of 3D SRAMs is not more than that of planar SRAMs and the 3D structure can be become a great potential application for aerospace and military domain.

As technology down scales, single event transient (SET) is more vulnerable than before in combinational circuits. This paper proposes a novel layout technique to mitigate the SET effect in combinational circuits. Based on 65nm CMOS process, technology computer aided design (TCAD) SET simulations are conducted on conventional layout, source-isolation layout, dummy transistor layout and the proposed layout. Heavy ions with different liner energy transfer (LET) values, inject angles and striking locations are simulated. The results indicate that, the proposed layout have considerable effect on decreasing the SET pulse width than other layouts. Compare with dummy transistor the proposed enhance dummy transistor have no additional area cost.

VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. h mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation.

This paper first introduce the H.264 video codec standard briefly, then analyze the inter-frame motion estimation in H.264. After that we propose an optimaized algorithm and the corresponding architecture. A pipeline-architecture was proposed with scaled searching algorithm based on the analysis to the previous work and the consideration of the system requirement between chip area and performance. A pipelined architecture with two 1-dimension interpolation for fractional pixe ME was proposed to meet the needs of SHD(2160P) video encoding, resulting in lower complexity and more throughout. Synthesized with Charted 0.13μm process, the design consumed 174.3K logic gates, with peak frequency of about 200MHz, and consumed less than 20mW at the power supply of 1.20V.

Single input change (SIC) test sequence has been investigated in recent years because it is effective to reduce the test power consumption. Deterministic built-in self-test (BIST) can achieve the high fault coverage with relatively short test application time and low test cost. In this paper, seeds selection scheme of SIC sequences based on deterministic ATPG test patterns is proposed for decreasing the test power consumption and test application time with high test fault coverage. Proper selection of SIC seeds is the key aspect to a successful low power deterministic BIST technique. Furthermore, simulated annealing algorithm is used to optimize the numbers of seeds. A simple hardware structure can implement the generation of SIC sequences. Experimental results based on ISCAS'85 benchmark circuits demonstrate that the proposed algorithm can reduce the number of SIC seeds. Test application time and average power can be decreased, and test fault coverage also keep high compared to random SIC (RSIC) test sequences.

High temperature during system-on-chip (SoC) test often suffers from critical problems such as timing errors, decrease in reliability and even potential damage to chip under test. Thermal-aware test scheduling is an efficient method for ensuring thermal safe during test. The temperature evaluation is a significant research work during thermal-aware test scheduling. A simple and effective temperature estimation model based on numerical heat transfer theory is proposed that no more requires material physical parameters. A thermal-aware test scheduling algorithm based on genetic algorithm (GA) is also presented that evaluate temperature using the proposed temperature model. Experimental results using SoC d695 of ITC'02 benchmarks show that, with this thermal estimation model, the proposed scheme can not only achieve convergence of temperature, but also obtain optimal test application time.

Fast soft error sensitivity characterization technique is essential for the soft error tolerance optimization of modern VLSI circuits. In this paper, an efficient soft error evaluation technique based on syntax analysis and state probability propagating technique is developed, which can automatically analyze the soft error rate of combinational logic circuits and the combinational part of sequential circuits in verilog synthesized netlist within a few seconds. We implemented the idea in a software tool called HSECT-ANLY, which use verilog syntax analysis to automate the soft error rate evaluation procedure and state propagating technique to speed up the analyzation process. By using HSECT-ANLY, experiments are carried out on some ISCAS'85 and ISCAS'89 benchmark circuits implemented with TSMC 0.18 µm technology and results are obtained. The result comparison with the traditional test vector propagating technique shows that the introduced method is much faster (2–3 magnitudes speeding up) with some accuracy losses, and be very suitable for the reliability optimization as the sub-algorithm of the optimization algorithms such as genetic algorithms to evaluate the fitness (soft error rate) rapidly.

An oscillation based BIST scheme for ADCs was proposed. A novel technique was used to timing output codes of ADCs by digital mode. In the BIST structure, the test signal was controlled by the feedback circuit to oscillate between two transition edges of ADCs. The rising and falling time of the test signal during oscillation period was in direct proportion to the code width of ADCs under testing. By timing the rising or falling time and comparing it with an ideal time, the offset error, differential non-linearity (DNL), integral non-linearity (INL) and gain error can be achieved.

The SoC (system-on-chip) based on reusable embedded IP (Intellectual Property) introduces new challenges for the test, since the SoC integrator may not know the implementation of the IP cores that are usually embedded in chip deeply. IEEE P1500 standard for embedded core test (SECT) is a standard-under-development that aims at improving ease of testing SoC. The SECT standardizes the core wrapper and the core test language (CTL), and leaves the design of test access mechanism (TAM) to the SoC integrator. The TAM-bus we proposed is a P1500 compliant TAM. This paper describes the control of TAM-bus. With a novel interface to the chip level JTAG test access port (TAP), the TAM control module can provide the control of the TAM and wrappers. The final test architecture is flexible and configurable. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The hardware overhead increases only 0.17% due to the TAM-bus and the TAM controller. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.

This paper proposes a configurable TAM-Bus, a P1500 compliant Test Access Mechanism (TAM), and the TAM-Bus controller (TAM-controller) that is interfaced with JTAG at chip level of chip. All IP (Intellectual Property) cores' test can be controlled through the TAP under the control of the TAM-controller. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The overhead increases only 0.17% due to TAM. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.

In this paper, a behavioral model of the QPSK digital communication system is presented using VHDL-AMS. The whole system can be divided into several parts. So, on the basis that the behavioral models of the parts are established first, the behavioral model of the system can be accomplished with the top structural description. Then the models can be verified by simulation.

Capable and efficiency simulators are in demand for designing complex analog and mixed-signal circuits and systems. With the standardization of VHDL-AMS, the demand is being realized. VHDL-AMS is an Analog and Mixed-Signal Extensions to VHDL. This paper introduces a mixed-signal simulator for it. The simulator was developed on the original VHDL digital simulation environment. An analog kernel has been integrated into the environment for the simulation of the continuous behavior of a model. The paper presents the algorithms adopted in the analog kernel and the synchronization of the digital and analog executions. The performance of the simulator is examined by mixed-signal examples.