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This paper details a time-domain (TD) test to visualize impacts on the double-li microstrip circuit behavior of its bandpass (BP) negative group delay (NGD). To determine the central frequency and the bandwidth of the input signal to use during the TD test, a frequency domain (FD) S-parameter analysis of the circuit has been done. This preliminary analysis, carried out first with the aid of simulations and then with the aid of measurements, shows a NGD for a frequency band of 15 MHz (resp. 8 MHz) around 2.345 GHz (resp. 2.364 GHz). To observe in the TD the NGD impact around 2.345 GHz, TD experimentations have been performed using a 2.345 GHz sine carrier shaped by Gaussian pulses. During these TD tests, the BP NGD signature was verified thanks to the output envelopes which presents rising and falling edges in time-advance compared to the input ones. It was also experimentally shown that the output is normally delayed when the input sine carrier is outside of the li-circuit NGD frequency bands.

International audience; This paper develops an original design method of high-pass (HP) negative group delay (NGD) integrated circuit (IC). The considered HP-NGD IC is based on a passive topology which is essentially composed of resistor-inductor (RL) network. The paper presents the first time that an unfamiliar HPtopology is designed in miniaturized circuit implemented in 130-nm CMOS technology. The theory of unfamiliar HP-NGD topology based on the voltage transfer function (VTF) analysis is elaborated. The design equations with synthesis formulas of the resistor and inductor are established. The HP-NGD IC CMOS design methodology is introduced. The feasibility of the miniature NGD IC implementation is approved by design rule check (DRC) and layout versus schematic (LVS) approaches. The HP-NGD passive IC is designed in 130-nm CMOS technology. The HP-NGD topology is constituted by RL-network based on CMOS high Ohmic unsalicided N + poly resistor and symmetrical high current spiral inductor. Then, the schematic and layout simulations are presented. The validity of the 130-nm CMOS HP-NGD design is verified by the investigation of 225 µm × 215 µm chip two different miniature circuit proofs-of-concept (POC). The HP-NGD behavior is validated by comparison between the calculated, and schematic and post-layout simulations of the HP-NGD POCs carried out by a commercial tool. As expected, the group delay and VTF magnitude diagrams are in very good correlation. HP-NGD optimal value, NGD cutoff frequency and attenuation, of about (−31 ps, 141 MHz, −3 dB) and (−47 ps, 204 MHz, −5 dB) are obtained from the miniature POCs. INDEX TERMS 130-nm CMOS technology, design method, negative group delay (NGD), high-pass (HP) NGD function, HP-NGD theory, integrated circuit (IC) design, synthesis equation, RL-network passive topology, miniature circuit.

The miniaturization and application development are the expected challenges on the today engineering design research on bandpass (BP) type negative group delay (NGD) circuit. To overcome this technical limit, an innovative contribution on integrated circuit (IC) design method of BP-NGD application to design constant phase shifter (PS) in 130-nm BiCMOS technology is developed in the present paper. The BP-NGD PS microwave passive IC is topologically consisted of cascade of CLC- and RLC-resonant networks. After the S-matrix modelling, the synthesis design equations enabling to calculate each lumped component values constituting the BP-NGD PS BiCMOS are established. The design equations are expressed knowing the targeted specifications as phase shift and operating frequency. The BiCMOS design methodology including the key steps as design rule checking (DRC), layout versus schematic (LVS) and post-layout simulation (PLS) is described. The miniaturized BP-NGD PS design feasibility is verified with schematic and layout simulations with IC CMOS standard commercial software tool. A proof-of-concept (POC) of 130-nm BiCMOS BP-NGD PS operating at the center frequency f(0) = 1.9 GHz and bandwidth Delta f = 0.1 GHz is designed and simulated. After DRC, the chip layout of miniaturized BP-NGD PS POC presents 0.407 mm(2) size. The BP-NGD PS POC exhibits constant phase shift notable value of about phi(0) = -90 degrees +/-0.4 degrees under S-21(f(0)) = -6+/-1 dB transmission coefficient with good flatness and reflection coefficients (S-21(f(0)) and S-21(f(0))) widely better than - dB. The design robustness is confirmed by 1000-trial Monte Carlo uncertainty analyses with PLS results. Because of the potential integration in wireless sensor networks (WSNs), the BP-NGD PS under study is a promising candidate for the improvement of the future 5G and 6G transceiver design. Web of Science 10 93103 93084

This paper explores an original study of bandpass (BP) negative group delay (NGD) robustness applied to the ring-stub passive circuit. The proof of concept (PoC) circuit is constituted by a ring associated with the open-end stub implemented in microstrip technology. An innovative experimental setup of a temperature room containing the NGD PoC connected to a vector network analyzer is described. Then, the electrothermal data of S-parameters are measured by varying the ambient or room temperature range from 20 to 60°C, i.e. 40°C maximal variation. The empirical results of the group delay (GD), transmission and reflection coefficient mappings versus the couple (temperature, frequency) highlight how the temperature affects the BP NGD responses. An innovative electrothermal calibration technique by taking into account the interconnection cable influence is developed. The electrothermal robustness analysis is carried out by variations of the NGD center frequency, cut-off frequencies and value in function of the temperature.

Editor’s note: This article presents a type of negative group delay (NGD) circuit based on transmission line resonators. To obtain the circuit’s S-parameters, this article uses a combination of ABCD and Z-parameters. Analytical design equations are presented, which are verified using circuit simulations. — Binoy Ravindran, Virginia Tech

The charge-pump Phase-Locked Loop (CP-PLL) is a widely used subsystem in wireless communication and smart system applications to perform the function of frequency synthesizer. Since the CP-PLL is a mixed-signal system, it is more complex to analyze the system behavior, especially when a voltage switched charge-pump-PLL (VSCP-PLL) is used. A more robust approach is required for such a non-linear pulse width modulated system, where the overall gain of the loop is varying due to non-constant pump current. To analyze the sampled behavior of a VSCP-PLL, the Event Driven (ED) model based on discrete-time phase equations is one of the powerful and resource efficient tool. In this brief, an autonomous ED model (time-independent and linear to fixed point) is developed for a second order VSCP-PLL by modifying the ED approach. The developed Autonomous ED-model is validated using the ED simulations in the locked state.

Nowadays, the speech signal processing is still challenging with the multimedia ubiquity. Classical signal processing techniques as filtering were developed for the speech enhancement to overcome unintentional effects as the propagation channel. However, the delay effect remains an open challenge for audio signal processing engineers. A voice/song signal (VSS) prediction is investigated theoretically and experimentally in this paper. This VSS engineering allows to predict an arbitrary waveform signal by using a lowpass negative group delay (NGD) function. This outstanding function presents the VSS advance properties when its parameters are matched with the operated signals. This NGD engineering analytical approach is described with the audio signal processing. The low-pass NGD analysis and property are deeply investigated with two NGD RC-and RL-passive cells. NGD transient study is performed with parametric analytical signals presenting raised cosine waveform. The introduced VSS NGD sensoring is verified with experimental real-time tests of microphone VSS generator. VSS time-advance of approximately 50 μs was observed with a good agreement between simulations and measurements.

International audience; This paper investigates an innovative negative group delay (NGD) theory of ''li'' geometrical shape topology. The li-topology is an outstandingly simple and fully distributed circuit comprised of a coupled line (CL). The li S-parameter model taking into account the CL coupling coefficient, delay and attenuation is established. The NGD analysis showing the possibility to generate NGD condition with respect to the li topology parameters is developed. The NGD characteristics as NGD value, center frequency, bandwidth, transmission and reflection coefficient are expressed. The li-NGD theory is validated with two proofs-of-concept implemented in microstrip technology. Calculated models, simulations and measurements are in good correlation. As expected, bandpass NGD presenting center frequency at approximately 2.56 GHz and 0.92 GHz with NGD level of approximately −0.9 ns and −3.7 ns were realized with the small and large li prototypes. Outstanding time-domain analyses explaining the bandpass NGD meaning, with innovatively low attenuation output, were also presented. The time-domain results highlight li-output pulse signal envelopes in time advance without violating the causality. INDEX TERMS Distributed circuit, li-topology, microwave theory, negative group delay (NGD), S-matrix modelling.

In this paper, new bridged-T network operating with bandpass (BP) negative group delay (NGD) function is introduced. The circuit design is innovatively based on an inductorless passive RCnetwork. The innovative bridged-T topology is implemented with a R-shunt configuration. The analytical transfer function of voltages and equivalent impedance-matrix are carefully calculated. The BP NGD analysis and design of the bridged-T topology is developed. The BP NGD properties and specifications are analytically investigated. A proof of concept of R-shunt bridged-T prototype with a surface-mounted device printed circuit board is designed, fabricated, and measured to verify the BP NGD behavior from theoretical equations and simulations. As expected, the theoretical, simulation, and measurements results are in very good agreement. From measurement results, the fabricated BP NGD C-shunt bridged-T reaches a delay of about ?45 ns and a center frequency of about 0.5 MHz over a ?3 dB attenuation.

This paper develops a cancellation method of cable delay. The proposed method is based on the low-pass negative group delay (NGD) function. The NGD circuit is constituted by a resistor and RC-parallel network mounted in L-cell and a non-inverter amplifier. The design equations of the NGD circuit are established in function of the cable delay and the operated signal bandwidth. The feasibility of the delay cancellation method is verified with simulations of network constituted by three parallel cables with 2 m, 4 m and 6 m physical lengths. Due to the low-pass NGD function, time-domain results show the cable delay cancellation effect. The cable outputs are synchronized with the pulse input signal with 0.25 µs duration.

This paper deals with an innovative technique of propagation delay reduction. The technique is based on the use of bandpass negative group delay (NGD) function. The principle of the propagation delay reduction is introduced by considering a simple scenario of Tx multi-wireless sensors communicating with a single Rx sensor. With the consideration of bandpass NGD function, it is shown that the differential between the propagation delay can be reduced considerably. The feasibility of the technique is confirmed with group delay diagram by considering microstrip NGD prototype measured S-parameters.

International audience; The charge pump phase locked loop (CP-PLL) is widely used subsystem in modern mixed-signal electronic systems that are utilized in digital and wireless applications such as clock generation, synchronization and frequency synthesis. In the classical mode, the combination of a current switched charge pump and a digital phase and frequency detector (CP-PFD) circuits produces an ideal pulse width modulated constant current during one sampling period, which permits a suitable transient performance. Nevertheless, many commercially used CP-PLL chips (e.g., 4046 family) have a voltage switched charge pump (VSCP) because the design of the constant voltage source is easier than the constant current generator and it is a low cost solution. However, the VSCP delivers a non-constant pump current, which varies during one sampling period related to the electrical load of the loop filter (LF). This effect results in a varying gain of the control system affecting significantly its tracking ability. Furthermore, due to its hybrid structure, the simulation of the CP-PLL at high frequencies is challenging and the analysis of its transient characteristics during its non-linear acquisition procedure is not easy. In this paper, a first ever exact and nonlinear model based on the phase equations of the second order voltage switched charge pump phase locked loop (VSCP-PLL) is established by using an event driven (ED) technique. This exact model is then simplified by using a step-wise quasi-constant current approximation during one sampling period to obtain the analytical phase equations. The derived ED-model is validated at transistor level simulations using 130 nm CMOS process. Furthermore, some typical nonlinear features of the VSCP-PLL are explored and the developed ED-models are compared with the quasi-time-continuous (QTC) theory.

A particle detection chain based on a CMOS SOI VCO circuit associated to a matrix of detection is presented. The solution is optimized for the recognition and tracking of various particles. Two ions are considered: an alpha and an aluminum. These two ions were chosen because there are very different in terms of energy and LET variations.

A fully differential and split-length transistors (SLT) CMOS two-stage operational transconductance amplifier (OTA) is presented. The proposed amplifier is designed in a CMOS 65 nm process with a 1.2 V supply voltage. The main advantage of this proposed amplifier is the use of both positive feedback technique and the split-length transistors to enhance its DC-gain without affecting the stability, unity-gain bandwidth (UGBW), output voltage swing and power dissipation of the conventional two-stage amplifier. The DC-gain is increased by about 40 dB. The two-stage OTA has been successfully verified and a comprehensive analysis has been provided for common mode gain, differential-mode gain, power supply rejection ratio, input-referred noise and the effect of using SLT on DC-gain sensitivity. The proposed two-stage OTA is used in a flip-around sample-and-hold amplifier (SHA) circuit. A total harmonic distortion of about 0.0018% is obtained for the output spectrum of the SHA circuit.

The design of an energy-efficient tunable ultra-wideband (UWB) pulse generator which complies with FCC regulations, without the need for shaping filter, is presented. The proposed pulse generator is based on carrier architecture. A new baseband UWB wavelet is used to modulate digital input data, ensuring better spectral efficiency. By using digital implementation technique, the proposed UWB pulse generator can adjust both the pulse width and the pulse amplitude, allowing more flexibility for use with different UWB technique. The design was simulated by a standard 65-nm CMOS technology. Simulation results show that the consumed energy by pulse is 19.8pJ decreased proportionally as bandwidth spectrum is higher. This shows a very good agreement with the low-power, low-cost UWB systems. The tuning spectrum complies with 3.1–5 GHz regulations.

National audience; An oscillator concept developed for particle detection and tracking is presented. The methodology used to characterize the currents generated by the particle is detailed. A Design Of Experiment (DOE) analysis is used to correlate the circuit oscillations with the current characteristics after particle detection. To validate the concept, an application example is developed to validate the detector capability to track a striking particle.

This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on a PMOS transistor in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. This evaluation compares the triple-well structure to a classical Psubstrate-only structure of PMOS transistor. It reveals the possible activation of the bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

A transistor level implementation of the analog block of a readout system on SOI process is presented here. This system is dedicated to the signal conditioning of a neutron detector in harsh environment. The different parts of the readout circuits are defined. The harsh environment constraints (crossing particle effect, high temperatures) are also detailed and modeled in the circuit in order to test and evaluate the characteristics of the designed block when working under these conditions.

International audience; — This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on an NMOS transistor in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. This evaluation compares the triple-well structure to a classical Psubstrate-only structure of an NMOS transistor. It reveals the possible activation change of the bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

A 2.45 GHz Multi-Controlled Oscillator (MCO) has been designed using a CMOS 0.28 ?m STMicroelectronics technology for use in frequency synthesizer and open loop FSK modulation circuit in multi-band IEEE 802.15 Wireless Personal Area Network (PAN) applications. Simple structure allowing multiple frequency control has been adopted so that the VCO maintains its center frequency and tuning range throughout ?40°C to 120°C by the way of a Proportional To Absolute Temperature (PTAT) biasing scheme. Simulations and measurements show the sensitivity of the VCO center frequency has been reduced from 1300 ppm/°C to 73 ppm/°C, while a phase noise of ?96 dBc/Hz @ 1 MHz offset with a power consumption of 18 mW have been achieved.

The original publication of the article contains an error in the author Dr. Loulou’s biography. The correct version of the biography is given below.

Optimization of CMOS circuits is essential to reduce power consumption and improve phase noise performance. A novel method to optimize voltage-controlled oscillator VCO is proposed using a current reuse technique. In this paper, three VCO topology for 2.4 GHz application are designed in 0.13μm CMOS process and are simulated using Cadence Spectre. The improvement of the VCO topology is described and analyzed. The traditional current reuse with a tuning range of 14.8% is presented in the first topology. It consumes about 0.267mW from 1V supply voltage. For the second topology, NMOS cross-coupled pair is added to speed up the oscillation and stability .The tuning range and power consumption are 28% and 0.366 mW respectively. It has a high performance of phase noise @ 1MHz with -120 dBc/Hz. The current-reuse oscillator with source degeneration resistance is presented in the third topology. The total power consumption is 0.234mW under 1V supply voltage and the frequency tuning range is 21.8%.

A way of improvement of an oscillator concept, dedicated to detection and tracking of low energy particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a VCO response. In order to improve the correlation between the input current and the oscillator response, a new way of VCO implementation is proposed. The new output parameter variations are analyzed.

A low-cost auto-calibration technique of Radio-Frequency (RF) Passive Polyphase Filter (PPF) for high image rejection in low Intermediate Frequency receiver is presented. The resistance values of the filter are process and temperature dependent with great mismatch constraints especially in the RF domain. That can severely impact the circuit performances if not controlled. In order to overcome this limitation, an in-line auto-calibration of the PPF resistance values, based on Design Of Experiment (DOE) methodology, is presented. Using DOE, a model is derived from thermal and process deviations of the chip responses. This approach results in a robust and low-cost solution.

In this paper, a comparison between the DCG-FGT (Dual-Control-Gate Floating-Gate Transistor) and its equivalent circuit composed of standard components is proposed. We demonstrate the DCG-FGT advantages with measurement and simulations under electrical simulator (ELDO). It is not easily to reproduce the DCG-FGT operating mode with standard MOS technology.

A Dual Control Gate Floating Gate Transistor (DCG-FGT) is a new device used in the circuit design. This component is a floating gate transistor. In this paper, we propose a retention study of floating gate charge. We demonstrate experimentally that the floating charge loss over time is very low.

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages VTH- (low switching voltage) and VTH+ (high switching voltage).

A new tunable control system for frequency modulation atomic force microscope (FM-AFM) using novel high frequency force sensors is presented. It is based on a phase locked loop (PLL) to detect the frequency shift that is used for the tip-surface distance control in FM-AFM. Furthermore, an amplitude proportional integral controller (APIC) was implemented to drive the cantilever at its resonance frequency. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.

This paper presents a low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuit is introduced to provide flexibility to program the hysteretic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger has been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and independently adjustable switching voltages V TH- (low switching voltage) and V TH+ (high switching voltage).

A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.

In this paper operation of an LC oscillator in two distinct frequency bands, dedicated respectively to Zigbee standard (2.4GHz–2.483GHz) and RFID standard (860MHz–960MHz) is presented. To perform low power consumption and low silicon area, an LC quadrature controlled oscillator using an active inductance has been used. The proposed topology has been simulated under 1.2V supply voltage using the typical model parameters of the 0.13μm CMOS process from STMicroelectronics. At the two separated frequency bands the phase noise is lower than −83dBcHz with frequency offset of 1MHz. At the same simulation condition the total power consumption is 5.5mW only.

This paper presents the design of a CMOS integrated circuit dedicated to the hybrid integration of a three-axis inertial smart-sensor with digital interface. Inertial sensing is achieved with an innovative low-cost technology that implements piezoresistive detection in MEMS devices with single-crystal silicon nanowires. The circuit includes a custom-designed analog front-end that achieves the bias and readout of the sensor, and an analog-to-digital converter with oversampling and integrated digital decimation. The obtained smart-sensor features a reduced output data rate that is suitable for a wireless sensor network with direct transmission of the raw data to a remote base station.

Polyphase filters are widely used in radio frequency (RF) receivers either to generate accurate quadrature signals or to reject the image. Analytical modeling of passive polyphase filter suitable for RF front-end applications is exposed. This analytical study has been used to calibrate the optimal values of passive components in order to obtain the maximum image rejection ratio (IRR). Component matching and parasitics reduction techniques have been taken into account. Tunable RC polyphase filter, suitable for multi-standard applications, has been fabricated in 0.13-µm CMOS technology.

Voltage controlled oscillator (VCO) is one of the key elements in radio frequency (RF) transceivers. A VCO working at 2.4 GHz and designed in CMOS technology is presented. It is suitable for low-cost and low-noise applications using wireless standards such as ZigBee, Bluetooth, Wi-Fi and WPAN (Wireless Personal Area Network). The noise characteristics of this RF VCO are investigated. Noise measurements, especially, phase noise are achieved under different environmental conditions.

Piezoresistive sensors convert a physical value into a resistance variation. Often four resistive elements are connected together in a Wheatstone bridge to provide electrical variations of sensors. When this structure is biased with a fixed voltage source or a current source the topology provides a differential output voltage. To exploit information a conditioning circuit is associated to the bridge. In most cases it consists of an instrumentation amplifier followed by a data converter to obtain very quickly a digital representation of information. Due to the high input impedance of the instrumentation amplifier, bridge sensitivity is preserved. A filter may be added to avoid aliasing or a continuous time sigma-delta modulator that includes filtering feature. This study is concerning the conditioning structure for piezoresistive sensors bridge especially fully integrated microphones for biomedical application. The bridge signal to noise ratio is set by biasing the amplifier stage by current. The noise performance becomes the limiting factor of the read-out circuit. Current mode topologies drive amplifiers design where inputs are the main noise contributor. Modeling noise contribution is a key point in the design of the conditioning circuit. The current consumption leads noise performances too. A proposed architecture was implemented in a 65nm CMOS standard technology for performance measurement and evaluation with nanowire based microphone dedicated to hearing aids application.

The feasibility of low noise sensitivity 2.4-GHz Phase Locked Loop for use in wireless communications as well as in clock generation circuit is demonstrated. The system uses low- gain-multi-band Voltage Controlled Oscillator which achieves a phase noise of -98 dBc/Hz @ 1MHz offset while a lock time of 150 - mus has been obtained from the PLL loop. The design has been implemented on standard CMOS technology.

This paper presents an analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. The relationships of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL is described in detail and a prototype 50 MHz PLL in a 0.18 - mum CMOS technology is tested.

Polyphase filters are an efficient solution for high image rejection and great accuracy quadrature generation in radio frequency (RF) receivers. Analytical modeling of passive polyphase filter suitable for RF front-end applications operating in 2.4 GHz frequency band is dealt with. This analytical analysis has been used to calibrate the optimal values of passive components in order to obtain the maximum image rejection ratio (IRR). Component sizing as well as judicious placement of the basic cell composing the filter has been taken into account during the layout process. Multi-stage RC network has been implemented in 0.13-μm CMOS technology.

Polyphase filters are an efficient solution for high image rejection and great accuracy quadrature generation in radio frequency (RF) receivers. Analytical modeling of passive polyphase filter suitable for RF front-end applications operating in 2.4 GHz frequency band is dealt with. This analytical analysis has been used to calibrate the optimal values of passive components in order to obtain the maximum image rejection ratio (IRR). Component sizing as well as judicious placement of the basic cell composing the filter has been taken into account during the layout process. Multi-stage RC network has been implemented in 0.13-mum CMOS technology.

The design of a low cost, low power multifunction phase-locked loop (PLL) for homeRF application is presented. This PLL is used in reception mode, as frequency synthesizer and in a direct conversion transmitter as a frequency shift keying (FSK) modulator in the transmit mode. Experimental results showing the circuit performances are presented. All the circuits, including the loop filter capacitance, have been fully integrated on chip using 0.13 mum CMOS technology.direct conversion transmitterfrequency shift keying modulatorloop filter capacitance,CMOS technology.