1. A Survey on Low Power Design Approaches in Nanoscale Regime
- Author
-
Siniprasad Pooja, Sposato Fausto, Kumar Sharma Vijay, Sisto Milito, Narayana Badiadka, Rytilä-Manninen Minna, Balasubramaniam Vaisali, Petraglia Géraldine, Courossé Swen, De Rocquigny Hélène, Ruiz Cairó Marta, Sadanandan Prashanth, Bisio Cecilia, Chandra Kodandoor Sharath, Haravuori Henna, Jessica Plessen Kerstin, Giovanna Spadafora Maria, Legoux Céline, Redmond Tomos, Osheroff Neil, Nair Bhagyalakshmi, Holzer Laurent, Kunhanna Sarojini Balladka, Krishnan Namboori Puliyapally, Marttunen Mauri, Oleksyszyn Józef, Guignet Boris, Pomillo Angelo, Urben Sébastien, Caspani Vivien, Reghu Nath Lekshmi, M. Savilahti Emma, Terren Morgane, Glorious Lobo Anupam, Brigida Mattia, Perricelli Alessia, and Vittala Salian Vinutha
- Subjects
Materials science ,Building and Construction ,Nanoscopic scale ,Engineering physics ,Power (physics) - Abstract
Background: The increased demand for battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality, and faster response at lower technology nodes. The applied power supply and the threshold voltage of the individual device are scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design. Results: 3 input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques. Conclusion: INDEP approach is the most effective approach to reduce the leakage current and to improve the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.
- Published
- 2021