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Archives of electrical engineering 69(1), 187-202 (2020). doi:10.24425/AEE.2020.131767, Published by Versita, Warsaw

With superb device characteristics, gallium nitride (GaN) power transistors facilitate fast and efficient power conversion and delivery in modern power circuits. To take full advantage of these devices, high switching frequency ( $f_{{SW}})$ operation is highly desirable. However, the lack of GaN compatible high-speed, efficient, and reliable gate drivers has been a formidable design hindrance. In this article, we address three critical design challenges faced in GaN power gate driving, namely bootstrap (BST) level-shifting, switching slew rate (SR) control, and active deadtime $t_{{dead}}$ control. We first propose a BST dynamic level-shifting technique to enable sub-nanosecond $t_{{delay}}$ at high $f_{{SW}}$ . Meanwhile, a dual-SR switching technique is introduced to retain both low switching power and noise. Compared with traditional constant $t_{{dead}}$ controls, the $t_{{dead}}s$ in this design are regulated actively for high efficiency. To validate these techniques, a four-phase GaN-based switching power converter was designed and implemented on a 0.35 μm high-voltage (HV) BCD process. At a $f_{{SW}}$ of 20 MHz and a $V_{{IN}}$ of 20 V, it delivers a maximum power of 8.4 W and a peak efficiency of 84.9%. The gate drivers are fully integrated including all BST capacitors and active BST switches. It achieves regulated rise and fall $t_{{dead}}s$ of 3.2 and 4.7 ns, respectively, for a load range from 50 mA to 1.2 A. The gate switching rise time $t_{R}$ is reduced to 1 ns with a maximum switching SR of 48 V/ns. The converter employs a HV synchronized hysteretic control, which works with the proposed gate drivers seamlessly to demonstrate a dynamic voltage scaling (DVS) Vo up- and down-tracking speeds of 0.33 μs/V and 0.47 μs/V, respectively.

This paper presents a slew-rate booster and frequency compensation circuit for automotive LDOs. The proposed circuit addresses three major LDO design challenges: frequency compensation for a wide range of output currents and load capacitors, fast response to load transients and reduced sensitivity to the supply variations. It was used to implement an LDO that provides a 5V output voltage and up to 50mA output current over a wide range of supply voltages - from 5.25V to 40V - and temperatures, -40°C to +150°C, while burning as little as 30μA. The slew-rate booster ensures that the output voltage overshoot and undershoot caused by load jumps of 50mA/μs remain below 4% of the nominal Vout value. Moreover, the LDO meets the E-06 test requirements within the LV124 automotive standard: the output voltage varies within 10% of its nominal value when sinusoidal voltages with amplitudes up to 20V peak-to-peak and frequency varying between 15Hz and 100kHz are injected into the LDO supply line. This feature is achieved while using a capacitor of only 1μF at the output, up to 10 times smaller than the decoupling capacitors used by similar LDOs reported previously.

An in-depth analysis on the load transient operation of a buck converter with auxiliary current control is presented in this article. The analysis quantifies the effects of nonideal characteristics, such as the equivalent series resistance, inductor current and output voltage ripples, time delay, and slew rate of the load current, on the fluctuation of the output voltage in a practical implementation. The analysis results reveals that some of the non-idealities may cancel each other out and become negligible in the implementation. A design considering the nonidealities can achieve the transient-wise capacitor charge balance of the output capacitor and minimize the output voltage deviation during the load transient. The agreement between the simulation and experimental results validates the effectiveness and precision of the proposed analysis and design.

In this article, a monolithically integrated driver fabricated by 12-V depletion mode gallium nitride (dGaN) and enhanced mode GaN (eGaN) driver is proposed. The proposed driver features an internal temperature-compensated (T-compensated) controller to drive an integrated 650-V eGaN power switch. Due to T-compensated characteristics, a slew-rate enhancement driver can be well-controlled by the fast turn-on (FTO) technique which is supplied by an on-chip regulator with reference voltage circuit. Therefore, the Miller plateau voltage can be tracked correctly by the proposed controller so that the switching frequency can be raised up to 50 MHz and the $\textit {dV}_{\mathrm {DS}}$ / dt slew rate can reach 118.3 V/ns for high efficiency and high switching operation.

A new structure for improving the performance of recycling folded cascode (RFC) operational transconductance amplifier (OTA) is presented. The improvement has been achieved using two current recycling stages. The first current recycled stage acts as an adaptive biasing current source for the second stage. Compared to the RFC OTA, the proposed OTA shows a significant improvement in slew rate (SR), gain-band-width (GBW), and DC gain. Simulation results in 0.18 µm standard CMOS technology exhibit that the proposed OTA achieves an about three times improvement in SR, 12.4 dB DC gain enhancement, and approximately two times increase in gain bandwidth compared to the RFC OTA. The proposed OTA consumes 433 µW @1.8 V which makes it appropriate for low-power applications.

In this article, a new nonisolated full soft-switching step-up dc/dc converter is introduced with a continuous input current for renewable energy applications. The use of a three-winding coupled-inductor (TWCI) along with a voltage multiplier, enables the proposed converter to enhance the voltage gain with lower turns ratios and duty cycles. Also, a lossless regenerative passive clamp circuit is employed to limit the voltage stress across the power switch. In addition to zero current switching performance at the turn- on instant of the power switch, the turn- off current value is also alleviated by adopting a quasi-resonance operation between the leakage inductor of the TWCI and middle capacitors. Moreover, the current of all diodes reaches zero with a slow slew rate, which leads to the elimination of the reverse recovery problem in the converter. Soft-switching of the power switch and all the diodes in the proposed converter significantly reduces the switching power dissipations. Therefore, the presented converter can provide a high voltage gain ratio with high efficiency. Steady-state analysis, comprehensive comparisons with other related converters, and design considerations are discussed in detail. Finally, a 160 W prototype with 200 V output voltage is demonstrated to justify the theoretical analysis.

Gallium-nitrideenhancement-mode high-electron-mobility transistors (GaN HEMTs) help to achieve high-power-density converter circuits due to their superior efficiency, higher switching speed, and small package size. However, increased switching speed results in a sharp increase in short-circuit (SC) current under a shoot-through fault with respect to other type of devices. GaN HEMTs can withstand the SC current only for several hundred nanoseconds. Therefore, fast SC protection solutions are critical for protecting power circuits. In this article, the voltage induced by high slew rate of SC current on the high-frequency power loop inductance resulting from the printed circuit board (PCB) layout is sensed to implement an ultrafast short-circuit protection technique. The proposed technique does not increase circuit parasitics and provides flexibility in layout design that makes it suitable for parallel-connected GaN HEMTs, which requires symmetric layout design for equal current sharing. A multipulse test is conducted under 1.56-MHz switching frequency, 400-V dc- bus voltage, and 40-A load current by using parallel-connected GaN HEMTs in a half-bridge configuration to verify the robustness and reliability of the proposed protection technique. Experimental results show that the proposed protection technique can detect SC fault within 40 ns and fault is completely cleared with a soft turn-off in 250 ns.

This paper addresses a novel robust gain-scheduling(GS) state-feedback (SF) H ∞ (induced L 2 ) control method for uncertain continuous-time(CT) systems having actuators with hard rate and magnitude bounds. The proposed method relies on acceleration form representation of the uncertain CT system. The technique enables the user to represent the control signal and its slew rate as auxiliary outputs along with the main controlled output. Two different norms, namely the induced L ∞ and L 2 are used to control the system effectively. While the L ∞ gain from the exogenous disturbance inputs to the control signal related outputs is used to deal with actuator saturation problem, L 2 gain from the disturbance inputs to the performance outputs is utilised in attenuation of the effects of the disturbances. To achieve these goals with minimal conservatism, we develop new forms of dilated Matrix Inequality (MI) conditions for peak-to-peak gain and L 2 gain with no additional conservatism. Then, we propose a novel robust GS control methodology to deal with the problem via dilated MIs and a modified full block S-procedure method (MFBSPM). The utilisation of MFBSPM ensures that the robust control design method of this note applies to any uncertain system having rational parameter dependence. Finally, the efficiency of the presented method is portrayed through extensive simulations of the responses of a marine vessel to wave excitations in which the vessel model is assumed to have magnitude and rate limited active fin stabiliser.

The active magnetic bearing technology is widely utilized for large turbomachinery. This research paper starts with a systematic review on the design and optimization of active magnetic bearing, by using bibliometric analysis. The salient research findings are summarized using the network analysis feature therein. Similarly, using cluster analysis, the major outcomes of research pursuits pertaining to active magnetic bearing (AMB) systems are also mapped. In this context, three performance parameters are usually evaluated, i.e., force slew rate, overall bearing volume, and total losses (copper and iron losses). In this study, optimization is carried out for a rotational speed of 22,000 rpm using multi-objective genetic algorithm so as to minimize the overall bearing volume, maximize the force slew rate, and also minimize the total losses. The optimum values of the design parameters related to the AMB geometry and electromagnetic actuator are determined.

A low output resistance and high slew rate class-AB flipped voltage follower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding transistor which provides the extra gain to the feedback loop and leads to the low output resistance while the bulk-driven transistor acts as an adjustable current source to increase the current driving capability and slew rate. The proposed FVF cell offers numerous advantages such as low output resistance, high current driving capability, wide bandwidth, high symmetrical slew rate and occupies less chip area. The proposed circuit has been designed using Cadence virtuoso tool in 0.18 µm CMOS technology and the post-layout simulation results are presented to validate its performance. To show the performance under extreme conditions, the analysis of the proposed circuit at various corners has also been presented.

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier’s specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18- $\mu \text{m}$ CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation.

A thermally actuated, single-axis, bidirectional translation stage is designed and constructed. To increase the temperature of the thermal actuator, induction heating is used while air-water-mist cooling is used to decrease the temperature. An automated control strategy comprising PID closed loop control (for heating) and On/Off switching between air and mist control (for cooling) is described. The translation stage of this study produces a displacement range of 100 μm and 200 μm (using 240 W and 480 W power sources) in the presence of preloads up to 1 kN. Dependent on the power source used, the root mean square (rms) controller error at steady-state is within 15 nm (240 W) and 35 nm (480 W). No significant variation in the rms controller error was measured in the presence of the different preloads. Dynamic performance is evaluated from step responses over the full range of the actuator as well closed-loop frequency responses. The non-linear, asymmetric aspects of heating and cooling are discussed. Further observations of the system behavior and the preload effect are presented with discussion covering the slew rate, magnitude of overshoot, and controller settling time.

A four-stage Operational transconductance amplifier (OTA) used in an infrared temperature sensor adopting the proposed Feed-forward Gm-stage and segmenting nested Miller compensation technique is presented. The purpose of the proposed segment compensation is primarily to make more amplifier stages concatenated. The circuit linked several transconductance stages to form a segment, and linked several segments to form a large multistage amplifier. For example, a two-stage amplifier linked with a three-stage amplifier can realize a five-stage amplifier, two three-stage amplifiers linked can realize a six-stage amplifier. A four-stage amplifier in the form of 2+2 (two stages and two stages) was used as an example to verify this compensation method. The proposed OTA is designed in the 180nm complementary metal oxide semiconductor process. It consists of two parts which ensure the stability and improve the bandwidth performance. The first part is a feed-forward transconductance stage, and the second part is the two-segment transconductance stages with the Miller compensation techniques employed within and between the two segments. Based on the small-signal model, stability analysis and theoretical derivation are performed in theory. On condition of a 2-pF load capacitance, a direct current gain of 109dB and a gain-bandwidth of 240MHz with a phase margin of 50° can be achieved. The proposed design consumes 2.19mW in a 1.8-V supply voltage. The transient simulation indicates that the settling time of the output is 19ns with the settling error being 1%, and the slew rate is 114V/μs.

This article reviews electromagnetic bearings with power electronic control for high-speed machinery, which are termed active magnetic bearings (AMBs). AMB is a contactless-type bearing, which uses magnetic force to support the rotor. This is suitable for high-speed applications, harsh operating conditions, and also clean environments. However, the AMB has nonlinear characteristics and is inherently unstable. Due to recent advancements in fast-switching power devices, high-switching-frequency power converters, high-bandwidth current control, nonlinear control strategies, advanced digital controllers, and sensors, AMBs have become promising for high-speed aerospace, industrial, and energy applications. This article contains a brief tutorial on the AMB, covering its operating principle, system-level block diagram, magnetic-circuit-based analysis, dynamic load due to rotor mass unbalance, load capacity, force slew rate, and response to large force disturbance. Furthermore, a design example of an eight-pole AMB with four excitation coils is presented to achieve a load capacity of 180 N. A preliminary design, based on magnetic circuit analysis, is seen to fall short in terms of load capacity. Iterative changes to the AMB dimensions achieve the required load capacity, but the characteristics are still nonlinear. Finite-element analyses bring out the effects of magnetic saturation on load capacity, linearity between force and current, force slew rate, and relationships between maximum force generated and AMB dimensions. An improved design procedure is presented to achieve both desired load capacity and linear characteristics, while balancing the compactness requirement. The improved design also achieves the desired slew rate besides faster response and improved stability.

A proposed ultra-high slew rate current recycling folded cascode operational transconductance amplifier (OTA) working in the subthreshold region is presented. By employing adaptive biasing and the ...

A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The design...

This paper introduces two high-performance single-stage bulk-driven (BD) operational transconductance amplifiers (OTA) in weak-inversion with rail-to-rail input and output voltage ranges suited for the excessively low-voltage of 0.5 V supply. The strategy depends on adopting a modified bulk-driven non-tailed input core to achieve high input core transconductance with a minimum power supply and an enhanced input common-mode range. Moreover, a partial positive feedback loop provides an overall improved DC gain and effective transconductance further. The input core of OTA1, named composite class-AB OTA, comprises two combined non-tailed differential pairs as composite differential pairs. The proposed OTA2, named composite super class-AB BD-OTA, exploits a matched bulk-input Flipped voltage follower (FVF) pair to adaptively bias the input core used in the composite class-AB BD OTA. As a result, a significant increase in large-signal input current to the output side due to super class-AB behavior improves the slew rate. The post-layout simulation results using the Cadence Spectre simulator with UMC 0.18 µm process technology confirm that the proposed OTAs have improved small-signal and large-signal performances over the conventional OTA driving a high capacitive load of 5 nF. The proposed composite class-AB and super class-AB BD OTA deliver 2.29 times, and 3.77 times open-loop DC gain, 10.6 times, and 117 times unity-gain bandwidth with 2 times, and 12.03 times slew rate at the expense of almost 0.52 times and 1.21 times power consumed over conventional counterpart, respectively.

Objectives: To present a power efficient Universal Biquad Operational Transconductance Amplifier circuit. Methods: OTA (operational transconductance amplifier) based Biquad filter is analyzed using three different simulated tools three different tools (CADENCE, XILINX, ORCAD and MATLAB tools) are used for designing the circuit. The 0.18mm CMOS technique is used using the Cadence tool for plan and reproduction. The same circuit has been implemented on ORCAD tool as well as Xilinx tool. Findings: The proposed Biquad filter improves the frequency response, power dissipation and provides vary of the KHN biquadratic filter circuits it uses minimum numbers of Operational Transconductance phenomenon Amplifier (OTA) to realize an equivalent. The assorted parameters specifically Center frequency, dcgain, Bandwidth, Power Dissipation and Quality issue are all electronically tunable. OTA based Biquad filter is simulated in CADENCE Virtuoso tool. Opamp-RC Biquad filter offers a bandwidth of 425 kHz, pass band gain of zero DB, whereas Gm-C measuring system based mostly filter offers 85MHz, passband gain of zero DB. Over-all power dissipation of the Biquad filter is 4.3mW with 1.8V DC Supply has basing current of 50mA with gracefully voltage 2.5v. by keeping the supply voltage, bias current and load capacitor as 2.5V, 50mA and 10pFrespectively, it has been seen that the power is reduced using the CADENCE virtuoso tool. Novelty : This study presents a Universal Biquadratic filter having less power dissipation. The circuit was optimized for gain, GBP, slew rate, areas, voltage offset, phase margin, power area etc. compared to all the previous filter circuits (OTA GMC filters, OTA type-C filters) designed with the help of OTA. Keywords: OTA; CMOS; CADENCE Virtuoso; Static Power; Dynamic Power; MOSFET

Driving solutions for power semiconductor devices are experiencing new challenges since the emerging wide bandgap power devices, such as silicon carbide (SiC), with superior performance become commercially available. Generally, high switching speed is desired due to the lower switching loss, yet high $dv/dt$ and $di/dt$ can result in elevated electromagnetic interference (EMI) emission, false-triggering, and other detrimental effects during switching transients. Active gate drivers (AGDs) have been proposed to balance the switching losses and the switching speed of each switching transient. The review of the in-existence AGD methodologies for SiC devices has not been reported yet. This review starts with the essence of the slew rate control and its significance. Then, a comprehensive review categorizing the state-of-the-art AGD methodologies is presented. It is followed by a summary of the AGDs control and timing strategies. In this work, using AGD to reduce the EMI noise of a 10-kV SiC MOSFET system is reported. This work also highlights other capabilities of AGDs, including reliability enhancement of power devices and rebalancing the mismatched electrical parameters of parallel- and series-connected devices. These application scenarios of AGDs are validated via simulation and experimental results.

Non-destructive measurements of nA beam currents in particle beam storage rings by detecting the azimuthal magnetic field generated by moving charged particles with a Cryogenic Current Comparator (CCC) are well established. The detection of beam currents with small amplitudes with a CCC in a storage ring demands a high slew rate which is caused by the rapid change of the beam current exceeding the operational limit of the SQUID in flux-locked loop mode. Previous solutions to increase the slew rate used a LCR first-order low-pass filter were a small resistor, unfortunately, dominated the current noise of the CCC. In this work we present a novel take by adding a second resonator into the CCC which in turn allows for higher resistances of the LCR low-pass filter and therefore lower thermal current noise. A second challenge connected with this CCC approach is the residual magnetization of the highly permeable magnetic core and the resulting shielding currents in the superconducting circuits of the CCC. The timing of a storage ring in the range of minutes opens a way to reduce these DC currents using a LR high-pass filter. Using serial sub-micro ohm resistors, time constants in the hour range can be achieved to improve the stability and performance of the CCC system.

This brief presents a more detailed model for the slewing behavior of self-biased ring amplifiers and outlines the factors which affect the large signal operation. A set of analytical expressions derived for the self-biased ring amplifier are presented which are valid for a larger portion of a design space than prior expressions. The equations presented are well matched with simulation results and the accuracy of the derived equations is reported. Finally, the paper examines the proposed equations and simulation results to provide insight about design parameter dependence.

A high-gain two-stage class A–AB operational amplifier (Op-Amp) is presented. A boosted recycling folded cascode with more than four cascode transistors compared to the conventional structure is used in the first stage of the proposed Op-Amp. The AB class output stage is constructed using a quasi-floating-gate MOSFET and a bootstrap capacitor. Indirect feedback compensation is utilized, leading to smaller compensation capacitors and, therefore, higher slew rate (SR) and bandwidth. The proposed circuit is simulated by using a 180-nm 1.8-V CMOS process standard technology. Simulation results with a 50-pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 121.6 dB, 45.3 MHz, 66.2 V/μS, 29.7 nS, and 65.6°, respectively. The PM and SR reduce to 65.6° and 51.9 V/μS, respectively, when driving a 100-pF capacitance load. The proposed Op-Amp consumes 1.59 mW @ 1.8 V, which makes it a high-current-efficiency two-stage amplifier.

The high peak current withstand capability of thyristors makes them extremely suitable for pulsed power applications. Silicon carbide (SiC) thyristors provide significant efficiency advantages compared with their silicon counterparts due to their very fast switching transitions. This article presents the development and characteristics of 3 kV SiC thyristors. A novel current-source gate driver is proposed to enhance their switching speed and, hence, maximize their benefits in pulsed power applications. The proposed driver provides a very high gate current slew rate while limiting the peak of the current pulse. The higher gate current slew rate achieves faster and, thus, more efficient device switching transition. Gate driver circuit description, variant topologies, and experimental results for a 3 kV SiC thyristor for a pulsed power application are presented to verify the proposed concepts.

A study of the reset transient of charge-sensitive amplifiers operating with a pulsed switch in parallel to the feedback capacitance is presented. Analytical models have been developed for amplifiers in both linear and slew rate regimes during the reset phase. The models predict the time interval required to reset the amplifier that, in most cases, significantly differs by the simple discharge of the feedback capacitance through the switch resistance and strongly depends on the open-loop gain and bandwidth of the core amplifier and on the input capacitance. The models also quantitatively predict spurious voltage transients at the preamplifier’s input and possible ringings at the output, as a function of the main general parameters of the circuit. A case application study of the presented model is proposed for low-capacitance detectors, such as semiconductor drift detectors or small pixel detectors.

In this paper, operational amplifier circuit is designed using model parameters of high-k FinFET in 22nm technology. The conventional design expressions for MOSFET based OPAMP design are fine tuned to design FinFET based OPAMP. The OPAMP design is suitable for use as sub circuit in ADC design as it supports low voltage, high speed and low power dissipation. The transistor geometries are identified so as to achieve high performance and energy efficient OPAMP. Schematic capture is carried out using Cadence tool. From the simulation studies, the designed OPAMP has a unity gain bandwidth of 100 GHz and slew rate is equal to 1V/μS. The maximum power dissipation of differential amplifier circuit is 800nW and hence suitable for all low power analog and digital circuits.

Purpose This paper aims to investigate the attitude control pointing improvement for a small satellite with control moment gyroscopes (CMGs) using the active force control (AFC) method. Design/methodology/approach The AFC method is developed with its governing equations and integrated into the conventional proportional-derivative (PD) controller of a closed-loop satellite attitude control system. Two numerical simulations of an identical attitude control mission namely the PD controller and the PD+AFC controller were carried out using the MATLAB®-SimulinkTM software and their attitude control performances were demonstrated accordingly. Findings Having the PD+AFC controller, the attitude maneuver can be completed within the desired slew rate, which is about 2.14 degree/s and the attitude pointing accuracies for the roll, pitch and yaw angles have improved significantly by more than 85% in comparison with the PD controller alone. Moreover, the implementation of the AFC into the conventional PD controller does not cause significant difference on the physical structure of the four single gimbal CMGs (4-SGCMGs). Practical implications To achieve a precise attitude pointing mission, the AFC method can be applied directly to the existing conventional PD attitude control system of a CMG-based satellite. In this case, the AFC is indeed the backbone for the satellite attitude performance improvement. Originality/value The present study demonstrates that the attitude pointing of a small satellite with CMGs is improved through the implementation of the AFC scheme into the PD controller.

A fast-transient, current-efficient low-dropout regulator (LDO) with super transconductance cell (STC) is proposed in this paper. By adopting advanced current amplifier (CA) and dynamic biasing (DB) techniques for the error amplifier (EA), the feedback loop bandwidth can be significantly extended without increasing much quiescent power, which reduces output voltage spikes and response time greatly. Moreover, dynamic reference control (DRC) with robust loop stability is embedded in the LDO to adaptively adjust voltage reference during transient so as to further enhance the slew rate of EA, realizing significant enhancement for the transient performances. This circuit has been implemented in a $0.35\mu \text{m}$ CMOS process and occupies an active chip area of $456\times 278 \mu \text{m}^{\mathbf {2}}$ . Experimental results show that it is able to provide 100mA load current at 200mV dropout voltage, with current efficiency of 99.88%. The output voltage spike under maximum load current change in 20ns edge time is less than 11.2mV with a $0.054\mu \text{s}$ response time. The power-supply rejection (PSR) at 100kHz is −75.6dB.

An efficient implementation of low-voltage low power two stage fully differential transconductance amplifier using CMOS technology is proposed. In this work, the dynamic threshold voltage MOSFET (D...

In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer’s first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm $$\times$$ 59 μm).

This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 $\mu \text{m}$ HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of $\text{d}{V} _{\mathrm {SSF}}$ /dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM1 and FoM2 of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

The increased power and voltage ratings of semiconductors fosters the use in medium voltage components, such as ac–dc converters. With a bipolar medium frequent rectangular (MF RECT) voltage, the converter size can be reduced and the efficiency increased. Possible insulating materials for medium voltage transformers are oil and insulation paper. The breakdown voltage of insulation materials is depending on the frequency and the shape of the voltage curve. Until today, only a few investigations of the breakdown voltage of insulating materials at sinusoidal and RECT voltages up to a few tens of kilohertz have been published. To design and optimize MF transformers at RECT voltages, further investigations are necessary. Therefore, a test bench for measuring the breakdown voltage at RECT voltages in the frequency range between one and ten kilohertz up to several tens of kilovolts is developed. The test bench is inspired by a Marx generator, which is a high voltage source for impulse voltages. By substituting resistances and spark gaps by IGBTs and adding galvanically insulated power sources, a medium frequent bipolar voltage can be generated. The test bench is characterized with respect to slew rate, input power, frequency, and voltage amplitude. Its usability is shown in first breakdown voltage measurements of insulation papers, used for transformer insulation.

The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising a flip voltage follower is used which boosts the dynamic current and gain-bandwidth product of OTA. Conventional current mirrors are replaced with source degenerated non-linear current mirrors to achieve a better slew rate. The conventional and proposed RFC structures are designed and simulated in a standard 180 nm CMOS process at 1 V supply voltage. The proposed RFC OTA demonstrates a significant enhancement in the performance parameter as 11 dB improvement in the gain as well as 290% more GBW and achieves a slew rate that is nine times better compared to the conventional RFC.

High-power isolated bidirectional dc–dc converters with wide voltage range are attracting increasing attention in many applications. The bidirectional three-phase current-fed dc–dc converters are known to be suitable for wide voltage range applications compared to dual active bridge based converters, having advantages of reduced device current ratings and prevention of transformer saturation due to high impedance nature. However, when the duty cycle becomes lower than 0.33 or higher than 0.66, power transfer capability is limited, and the efficiency is significantly reduced due to increased circulating current, which has rarely been discussed so far. In this article, a hybrid dual-asymmetrical pulsewidth modulation (DAPWM) and pulsewidth modulation plus phase-shift (PPS) switching method is proposed for efficiency improvement of the bidirectional three-phase push–pull converter with very wide voltage range. A seamless mode change method between PPS and DAPWM is also proposed for minimizing the transient state. Further, through current waveform and power flow analysis, the leakage inductance along with transformer turn ratio are designed to minimize the root mean square (rms) current of devices, while having the capability of transferring the desired power and limiting the slew rate of transformer winding current under wide voltage range operation. Experimental results from a 22-kW prototype are provided to validate the proposed concept.

In this paper, the surface discharge current pulses of PEEK (polyether-ether-ketone) under positive repetitive square voltage are measured. The effects of voltage rise time and fall time on pulse parameters of discharge current, instantaneous voltage of discharge and time-lag of discharge are analyzed in detail. The results show that the amplitude of discharge current and the instantaneous voltage of discharge decrease, and the time-lag of discharge and the dispersion of time-lag increase with the increase of voltage rise time. With the increase of voltage fall time, the amplitude of discharge current decreases and the instantaneous voltage of discharge, the time-lag of discharge and the dispersion of time-lag increase. To analyze the influence mechanism of voltage rise time and fall time on surface discharge, the accumulation of surface charge under repetitive square voltage is regarded as a periodic process. Besides, the correlation between forward discharge and back discharge in the process of discharge is analyzed, and the development of discharge is analyzed by using the time-lag theory. Furthermore, the relationship between instantaneous discharge voltage and voltage slew rate is revealed, and the surface charge accumulation processes under different voltage rise times and fall times are compared to reveal the influence mechanism of rise time and fall time on the surface discharge under positive repetitive square voltage.

Ever since the reliability issues caused by I/O (input/output) compatibility among chips fabricated using different processes were raised during mid-2000, on-silicon mixed-voltage I/O buffer with wide voltage tolerance has been considered a better solution than using signal level converters to shrink PCB size, number of discretes, and power consumption. However, various external voltages on I/O pad result in body effect, leakage, hot-carrier degradation, and gate-oxide overstress in stacked transistors of mixed-voltage I/O. What even worse is that slew rate (SR) was also found deteriorated by PVT (Process, Voltage, Temperature) variations. A complete mixed-voltage I/O buffer design flow using nano-scale CMOS processes will be introduced in this tutorial based on previously developed buffers. Besides circuit design methodology, the reliability design consideration for the buffers, including ESD, PVT detection, and slew rate auto-adjustment will be discussed as well.

This article presents a resonant switched-capacitor (RSC) dc–dc converter for visible light communication (VLC) applications operating as both high-efficiency power converter and fast-response data transmitter. By operating under soft switching, the topology allows for higher switching frequency and higher slew rate so that the VLC functionality can be embedded into the power stage without an auxiliary switch. In the literature, this additional switch has been presented as a viable implementation of on–off-keying (OOK) and variable pulse position modulation (VPPM) for data transmission yet, at the same time, is a major efficiency bottleneck for higher transmission rates due to its inherent hard-switching operation. This justifies new efforts in enabling pulse-based transmission (PBT) without this additional switch. A 10-W prototype was built to demonstrate such feasibility, operating at a switching frequency of 500 kHz, resulting in nominal efficiency of 85% during data transmission under the VPPM scheme, achieving up to 100 kb/s for various brightness levels, over a distance up to 1m.

In this paper, a class-AB flipped voltage follower cell with high current driving capability is proposed. The proposed flipped voltage follower (FVF) cell offers increased current sourcing capability and large input/output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between output and ground terminals to increase the current sinking capability and to reduce the output resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.

This paper proposes a modified version of recycling folded cascode amplifier. A comparative study, modelling and analysis of the proposed design along with conventional folded cascode and recycling folded cascode have been presented in this work. The design is intended for use as a preamplifier in an epileptic neurostimulator circuit, which ensures high gain, low noise low power trade-off and smaller bandwidth (lower than 500 Hz) as the primary criteria. An adaptive biasing technique is implemented to enhance the key performance parameters like intrinsic gain, slew rate and gain-bandwidth product. Also, the proposed device works in weak inversion region to ensure ultra-low power consumption. There are various neurostimulators categorized as Deep Brain Stimulation and Vagus Nerve Stimulation reported in the literature so far. However the proposed design considers high-frequency oscillations (HFO) as the biomarker of focal epileptic seizures, owing to its occurrence in higher frequencies, thereby asserting a bandwidth less than 500 Hz. The simulations for the designed structures are carried out in Cadence Virtuoso using SCL 180 nm technology, with an operating voltage 0.6 V. The simulation results illustrate the improvement in several parameters: intrinsic DC gain by 14 dB with a consumed power of 1.782 µW, and an input-referred noise of 10.97 µV/√Hz @1 Hz, establishing that the design works with ultra-low power consumption. Analytical modelling and comparative analysis of the proposed as well as conventional designs have been performed. Additionally comparison has been drawn between the pre-layout and post layout simulation results which shows close matching between each other. Furthermore, Monte Carlo analysis has been performed on the proposed design to validate its consistency and dependability.

SiC metal–oxide–semiconductor field-effect transistor (MOSFET) has a fast switching speed and high slew rate. However, its ultrashort switching time approximates the rise time and propagation delay of the measurement instruments, which results in an inaccurate assessment of the switching loss and challenges the thermal design of the power converter. In this article, aiming to reveal the principles of accurate measurement for the switching behavior of SiC MOSFET, insightful models are proposed for baseline probes and transient trajectories to characterize the measurement error of the switching losses. By using the Gaussian function, the mathematical models for the rise time, bandwidth, and propagation delay of the measurement instruments are achieved, which is also confirmed by the surveyed specifications of commercial probes. Concerning the accurate measurement, the turn-on and turn-off losses of the SiC MOSFET influenced by the rise time and propagation delay of probes are comprehensively modeled and characterized. With respect to different current probes, voltage probes, and gate driver resistances, extensive experiments are demonstrated to confirm the validity of the proposed models. The experimental findings are in line with the conducted predictions of the proposed models. It is found that, due to the very fast switching transients of the SiC MOSFET, the limited bandwidth and inevitable propagation delay of measurement instrument may result in a prominent error of the switching loss and impede the widespread implementation of the SiC MOSFET.

Triangular-current-mode (TCM) modulation guarantees zero-voltage-switching across the mains cycle in AC-DC power converters, eliminating hard-switching with a minor ${\approx} {30}{\%}$ penalty in conduction losses over the conventional continuous current mode (CCM) modulation scheme. TCM-operated converters, however, include a wide variation in both switching frequency and switched current across the mains cycle, complicating an analytical description of the key operating parameters to date. In this work, we derive an analytical description for the semiconductor bridge-leg losses in a TCM AC-DC converter, including the rms current and/or conduction losses, switching frequency, and switching losses. For SiC mosfets, we introduce a new loss model for switching losses under zero-voltage-switching, which we call “residual ZVS losses”. These losses include the constant $C_\text{oss}$ losses found in previous literature but must also add, we find, turn-off losses that occur at high switched currents. The existence and modeling of these turn-off losses, which are due to currents flowing through the Miller capacitance and raise the inner gate source voltage to the threshold level and accordingly limit the voltage slew rate, are validated on the IMZA65R027M1H 650V SiC mosfet. The complete loss model – and the promise of TCM for high power density and high efficiency – is validated on a 2.2 kW hardware bridge-leg demonstrator, which achieves a peak 99.6$\%$ semiconductor efficiency at full load. The proposed, fully-analytical model predicts bridge-leg losses with only 12$\%$ deviation at the nominal load, accurately including residual ZVS losses across load, modulation index, and external gate resistance.

An optical sensor IC in 0.35- $\mu \text{m}$ CMOS is presented containing a single-photon avalanche diode (SPAD) and a fast quadruple-voltage quenching circuit (QVQC). The QVQC features a fast active quenching time of 0.93 ns, a total quenching time of 1.9 ns, and an adjustable total dead time (8.6–200 ns) to reduce the afterpulsing probability (APP). To verify the quenching performance, the circuit was integrated with a 40- $\mu \text{m}$ diameter SPAD. Experiments show the reduction of afterpulsing by a low detection threshold and by fast quenching with a slew rate of 13.8 GV/s. Thus, an APP of 3.2% at 27-ns dead time, a peak photon detection probability (PDP) of 67.6% at 652 nm, and a PDP of 34.7% at 854 nm were measured at 13.2-V excess bias.

A circuit with a low-power low-noise amplifier and a Gm-C ultra-low-power filter is proposed in this paper for portable electroencephalogram (EEG) acquisition applications. The proposed circuit contains a two-stage chopper-stabilized fully recycling folded cascode (TSRFC) amplifier and a second-order continuous-time Gm-C low pass filter (LPF) with ultra-low-power consumption. The noise and input offset are reduced using the chopper-stabilized technique. A two-stage amplifier that consists of composite transistors and a recycling structure is proposed for the amplifier. Compared to a typical folded cascode CMOS amplifier, the proposed design has higher DC gain and slew rate as well as lower input-referred noise. This circuit has an adjustable second-order Gm-C LPF with very low power consumption. The amplifier achieves a midband gain of 70 dB and a −3dB bandwidth in the range 0.1–212 Hz. Moreover, the amplifier is designed in 0.18- $\mu \text{m}$ CMOS process and the chip area of the proposed circuit with pads is $450\times 450\,\,\mu \text{m}^{2}$ . The adjustable LPF has a 100 Hz cut-off frequency. The proposed circuit has an input-referred noise of $0.7~\mu $ Vrms, (0.1 ~ 100Hz) and a power consumption of 380 nW at 1 V supply.

This work proposed a binary-weighted Digital-to-Analog Converter (DAC), which is designed to be used in Asynchronous successive approximation register (SAR) based Analog-to-digital converters (ADCs) specifically and in other relevant operations .The design has yielded an improved slew rate, and it is less prone to noise as the size of capacitors is taken in accordance with KT/C noise calculation. For achieving all mentioned goals, and to restrict the size of DAC, within suitable dimensions charge scaling DACs are used. One more advantage of this design is its accuracy, further it does not require op-Amps for its operation. Results of statistical simulation and mathematical consideration are published which depicts the supremacy of the design. A high-resolution DAC designed for this specific purpose has to have special consideration for the effect of local mismatch, parasitic and matching of the capacitors, for that, the common-centroid approach has been followed. This design has displayed a high resolution with small unit capacitances and that too without expensive factory calibration.

This brief presents a novel adaptive slew-rate ring amplifier. The proposed technique enhances the linearity, without stability degradation, using a rail-to-rail controlled feed-forward path used in parallel with the main ring amplifier. It offers additional degrees of freedom to improve the linearity/power consumption trade-off proposed in other reported slew-rate enhancement techniques. The proposed design has been implemented and simulated in a low-cost CMOS 65 nm technology. Operating from a single 0.9 V power supply, it consumes $186~\mu \text{A}$ for switching frequency of 210MHz. For the same current consumption, it achieves an improvement of 10 dB in the total harmonic distortion (THD) compared to state-of-the-art.

The emergence of fast switching wide-bandgap (WBG) power devices offers clear potential to implement higher power density and more efficient motor drives. However, the high voltage slew rate $(dv/dt)$ of switching transients brought significant challenges that can hamper the wide adoption of WBG devices in motor drive applications. Specifically, the aggravated motor overvoltage oscillation, due to reflected voltage phenomenon under high $dv/dt$ , is one of the most considerable challenges that degrade the motor lifetime. With filter networks acting as the mainstream mitigation method, the advantages of WBG-based motor drives are compromised due to additional size and power loss of the filters. This letter proposes a novel quasi-three-level pulsewidth modulation scheme as a software solution to eliminate motor overvoltage oscillations in cable-fed drives. The proposed scheme adopts a brief zero-voltage state, with a predetermined time, in the midway of each pole-to-pole voltage transition. This allows the voltage reflections along the cable to significantly discontinue after two propagation cycles, securing the motor operation at prescribed voltage levels. The proposed scheme is applicable to two-level voltage-source inverters (VSIs). In this letter, the scheme is presented on a single-phase two-level VSI motor drive, supported with theoretical and experimental proof of concept.

Ultrafast and isolated gate drivers advance the development of pulse and very high frequency power electronics for applications that include LiDAR, space systems, miniaturized hardware, and testing of emerging ultrafast devices. The isolated ultrafast gate driver in this letter achieves a gate voltage slew rate above 12 GV/s with rise and fall times below 260 ps with the proper choice of components. Magnetic isolation provides transient immunity and positive feedback enables dynamic dc restoration to allow arbitrarily long on - and off -times and preserve variable duty cycles. With the isolated ultrafast gate driver, an EPC 2038 GaN FET achieves a drain voltage slew rate of over 37 GV/s when hard-switching and improves total efficiency by 8% (including gating loss) with a careful choice of logic inverters in a symmetric 100 MHz current-mode class D (CMCD) wireless power transfer system. The ultrafast gate driver with isolation and positive feedback was implemented with a commercial radio frequency signal transformer and discrete logic inverters and validated in a hard-switching double pulse test, a narrow pulse test repeating at 165 MHz, and a 100 MHz soft-switching CMCD resonant converter.

Since the CMOS technology moving forward swiftly, digital data exchange between chips fabricated using different generations of technologies becomes a problem when the size of printed circuit board-based systems is critical for mobile or wearable devices. To achieve better performance, smaller size, and power efficiency, a 2 $$\times $$ VDD output buffer featured with process, voltage, and temperature detection and the integration of dual-Vth and standard Vth transistors optimized by W/L sizing is proposed. Slew rate (SR) self-adjustment and power–delay product reduction are also verified by Monte Carlo simulations to achieve at least 27.8% improvement and 37.6% reduction. The prototype of this investigation fabricated by a typical 28-nm CMOS process is measured on silicon to attain at least 7.6% SR improvement.