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Full-rate bang-bang phase detectors (BBPDs) and bang-bang frequency detectors (FDs) are presented for continuous-rate clock and data recovery (CDR) circuits. The proposed BBPDs have only six latches, so they save the power and area. Their symmetric architecture minimizes the clock skew caused by the nonsymmetric layout. The proposed unilateral FDs have a wide detectable frequency range. The theoretical analysis for the proposed FDs is given. Two continuous-rate CDR circuits using the proposed BBPDs and FDs have been fabricated in a 0.18-mum CMOS process. They recover the NRZ data of a 231-1 PRBS from 622 Mbps to 3.125 Gbps. All of the measured bit error rates are less than 10-12.

A 40 nm CMOS transceiver supports 10 bands of HSPA+ and quad-band GSM/EDGE occupying 6.2 mm 2 of a Modem SoC. The TX supports up to 11 Mb/s HSUPA with minimal analog filtering and 42dB SNR for receive levels >-60 dBm.

In this research, we study the influence of the electrode pattern design on turn-on voltage and conversation efficiency in light emitting diodes (LEDs). We found that some relationships existing between the pattern design of electrode and characteristics of samples. We designed several electrode patterns in the fixed sized LEDs. In our research, we found that the reduction of turn-on voltage is related to the increasing total length of P-electrode and N-electrode. Furthermore, we found that the reduction of turn-on voltage is also related to the parallel length of P electrode and N electrode. Base on the experiment results, we estimated the reduction of turn-on voltage is proportion to the total length of P electrode and N electrode. For conversation efficiency, we found it proportion to the area which deduct P electrode area from transparent conduction layer (TCL) and the area of P electrode paralleling N electrode.

A half-rate bang-bang phase and frequency detector (BBPFD) is presented for continuous-rate clock and data recovery (CDR) circuits. The proposed half-rate BBPFD not only preserves the advantages of conventional BBPDs, but also has the infinite unilateral frequency detection range. To verify the proposed circuit, a continuous-rate CDR circuit with the proposed BBPFD has been fabricated in a 0.18um CMOS process. It can recover the NRZ data with the bit rate ranging from 622 Mbps to 3.125 Gbps. The measured bit-error rate is less than 10-12. The core area is 0.33 x 0.27 mm2 and the power consumption is 80 mW from a 1.8 V supply.