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A 2.8μm 4-tap global shutter pixel has been realized for a compact and high-resolution time of flight (ToF) CMOS image sensor. 20,000 e- of high full-well capacity (FWC) per a tap is obtained by employing a supplementary MOS capacitor. 36% of high quantum efficiency (QE) has been achieved by backside scattering technology (BST) and thick silicon process. In addition, demodulation contrast (DC) is improved to 86 % by additional deep photodiode doping process for static potential gradient in a photodiode.

We propose a method of forming metal nanoparticles or layers on the oxide by tunnelling current of the EOS (electrolyte–oxide–silicon) system. Electrical characteristics of the metal layer and particles obtained experimentally by the proposed method are compared with the electrolyte–metal–oxide–silicon and the metal–oxide–silicon systems. Also, it is shown that the instability of the EOS system is caused by the H+ penetration into the oxide and is largely cured by applying alternative voltage to extract the H+ ions from the oxide. We show that the proposed technique can selectively deposit extremely thin metal layers on the active sites of the silicon surface in a self-alignment manner.

A new concept of device structure that can selectively change the injection carrier type through a thin energy band engineering layer is proposed and demonstrated using the device simulation. As an example, the structure is applied to achieve the n-type field-effect transistor using carbon nanotube network (CNN). Tin oxide (SnO2) layer placed between an Au electrode and a CNN channel is used as an energy band engineering layer for enhancing an electron injection. By just adding the band engineering layer in the conventional p-type device, the n-type characteristics with -40 to +40 V bottom gate sweep is successfully demonstrated experimentally without other manipulations.

Heteroepitaxial MgO films have been grown on SiC-buffered Si(0 0 1) substrates by chemical vapor deposition using a single source in an ultrahigh vacuum chamber. The crystallinity of the MgO films deposited in the temperature range 600–850°C has been investigated by reflection high-energy electron diffraction (RHEED) and X-ray diffraction (XRD). RHEED patterns showed ordered spot structures with twin spots for the films grown in the temperature range 700–850°C, and ring structures for the films grown below 600°C. XRD patterns, rocking curve measurements, and pole figure analysis have also indicated that the films are grown partly epitaxially in the [1 0 0] direction at growth temperatures between 700°C and 850°C.

Seeded vapour-phase free growth of ZnSe single crystals at T g = 1100–1250°C in 〈1 0 0〉 direction was studied. The 〈1 0 0〉 growth process was found to be more sensitive to the temperature profile in a furnace than the 〈1 1 1〉 direction. The problem that seed attachment to a support pedestal is followed by a generation of high dislocation density was solved by use of a reverse temperature gradient along the axis of the furnace between the seed and the pedestal and by optical monitoring of the attachment process during the growth. Seeds with dislocation density of 10 4 –10 5 cm −2 and 2–4 cm 2 area selected from single crystals grown in 〈1 1 1〉 direction were used for the first growth processes in 〈1 0 0〉 direction. To increase the diameter of the grown crystals, a tangential growth regime was developed. Twin free ZnSe single crystals of 51 mm diameter and of 15 mm height were grown in helium. The average dislocation density was about 10 4 cm −2 and the full-width at half-maximum (FWHM) of the X-ray rocking curve was as small as 16 arcsec.

Silicon dioxide thin films are widely used as dielectric layers in microelectronics and can also be engineered on silicon wafers. It seems counterintuitive that electrochemical reactions could occur on such an insulator without relying on tunnelling current. Here we report electrochemistry based on electron transfer through a thin insulating layer of thermally grown silicon dioxide on highly n-doped silicon. Under a negative electrical bias, protons in the silicon dioxide layer were reduced to hydrogen atoms, which served as electron mediators for electrochemical reduction. Palladium nanoparticles were preferentially formed on the dielectric layer and enabled another hydrogen-atom-mediated electrochemistry, as their surfaces retained many electrogenerated hydrogen atoms to act as a 'hydrogen-atom reservoir' for subsequent electrochemical reduction. By harnessing the precisely controlled electrochemical generation of hydrogen atoms, palladium-copper nanocrystals were synthesized without any surfactant or stabilizer on the silicon dioxide layer.

The influence of growth rate, vertical temperature gradient and crystal rotation rate on the interface shape between melt and crystal was investigated to grow high-quality LiNbO 3 single crystals. The growth rate and the vertical temperature gradient affected the growth of the planar interface. The crystal rotation rate strongly affected the generation of the cracking defect. Above the critical rotation rate, the shape of the melt/crystal interface changed from convex to concave. The critical rotation rate was inversely proportional to the diameter of the crystal. The experimental data on the critical rotation rate have been compared with the calculated values. A high-quality LiNbO 3 single crystal with 80 mm diameter was produced by effective control of growth conditions, especially crystal rotation rate.

A 1.4 μm-pitch pixel of CMOS image sensor, which is the smallest to date, has been successfully developed and integrated into 8M density for the first time. To overcome the crucial degradation of the saturation charge and sensitivity, a novel photodiode structure extended under transfer gate and an elaborate optical design including very thin tungsten pixel routing with 65 nm-grade design rules are introduced, which result in enhanced electrical and optical performance.

Crosstalk of CMOS Image Sensor (CIS) causes degradation of spatial resolution, color mixing and leads to image noise. Crosstalk consists of spectral, optical and electrical components, but definition of each component is obscure and difficult to quantify. For the first time, quantifiable definition of each component is proposed to perform crosstalk analysis in this paper. Contribution of each component to the total crosstalk is analyzed using opto-electrical simulation. Simulation is performed with an internally developed 2D finite difference time domain (FDTD) simulator coupled to a commercial device simulator. Simulation domain consists of set of four pixels. Plane wave propagation from micro-lens to the photodiode is analyzed with FDTD and the optical simulation result is transformed into the photo-current in the photodiode using electrical simulation. The total crosstalk consists of 43% of spectral crosstalk, 14% of optical cross talk, and 43% of electrical crosstalk at the normal incident light. Spectral crosstalk can be suppressed through careful selection of color filter materials with good selectivity of color spectrum. Characteristics of crosstalk and photosensitivity show contrary trend to one another as a function of color filter thickness. Therefore, the crosstalk target is fixed and simulation is performed to determine the minimum color filter thickness that satisfies the crosstalk target. By color filter material and thickness optimization, 10% increase in photosensitivity and 7% decrease spectral crosstalk were obtained. Electrical crosstalk showed 11% and 9% improvement through applying to new implantation process and stacking multi-epi layer on the p-type substrate, respectively.

Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera (DSC) application

5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed

In this work, we present the results of three-dimensional CMOS image sensor cell simulation. Electrical characteristics of the device are represented comprehensively. The methodology, describing saturation, charge-voltage conversion, and image lag of a CIS cell in a single simulation analysis, is expected to play a key role in future CMOS image sensor cell development.

The effects of low temperature deuterium annealing on plasma process induced damage were examined for devices with a thin gate oxide. The devices were exposed to the plasma during poly-Si gate or metal processes, and the device characteristics were monitored by charge pumping and current-voltage measurements. It was observed that the metal process induced more plasma damage than the poly-Si gate process. The deuterium (D/sub 2/) annealing had little effect on oxide damage, but it was very effective in reducing the interface damage. After D/sub 2/ annealing, the devices showed a very low level of interface states, and the strength to withstand electrical stress was also enhanced. To maximize D/sub 2/ annealing effects, it is suggested that the D/sub 2/ annealing should be conducted without any H/sub 2/ annealing.

The latent damage induced by plasma processes has been investigated by applying polarized constant current stress to the gate electrode of n- and p-MOSFETs. By optimizing the stressing conditions to effectively monitor the plasma damage, deuterium sintering is found to be very efficient at reducing plasma damage by suppressing the regeneration of interface states.