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Multilevel thresholding is widely used in brain magnetic resonance (MR) image segmentation. In this article, a multilevel thresholding-based brain MR image segmentation technique is proposed. The image is first filtered using anisotropic diffusion. Then multilevel thresholding based on particle swarm optimization (PSO) is performed on the filtered image to get the final segmented image. Otsu function is used to select the thresholds. The proposed technique is compared with standard PSO and bacterial foraging optimization (BFO) based multilevel thresholding techniques. The objective image quality metrics such as Peak Signal to Noise Ratio (PSNR) and Mean Structural SIMilarity (MSSIM) index are used to evaluate the quality of the segmented images. The experimental results suggest that the proposed technique gives significantly better-quality image segmentation compared to the other techniques when applied to T2-weitghted brain MR images.

On pure and metal, non-metal, co-doped rutile TiO2, DFT simula- tions are performed. For the stability study of doped materials, the defect formation energies of non-metal (S), metal (Fe), and metal and non-metal (Fe/S) co-doped materials are determined. A Ti- rich environment is preferable over an O-rich environment. With values of 2.98 eV, 2.18 eV, 1.58 eV, and 1.40 eV, the bandgap for pristine, S-doped, Fe-doped, and Fe/S co-doped materials is found to be direct. The effective masses (m*) and ratios (R) of charge carriers are also examined, and it is discovered that Fe/S co-doped material has the lowest charge carrier recombination rate. The maximum static dielectric constant is found in the Fe/S co-doped material. Doped material’s absorption spectra shifted into the vis- ible region. Additionally, using SCAPS-1D simulation software, a complete solar cell device study using these materials as ETL is performed for the first time. The absorber layer and the ETL settings have been tweaked to perfection. Current-voltage (IV) characteristics, quantum efficiency (QE), capacitance-voltage (CV) characteristics, and capacitance-frequency (Cf) character- istics are provided for optimize solar cells.When the smallest degree of defect for each layer is taken into account, the solar cell with Fe/S co-doped ETL has the highest efficiency of 34.27%.

A split gated silicon nanotube field-effect transistor (FET) biosensor has been proposed for the label free detection of the biomolecules for the first time in literature. The sensitivity of the sensing device has been analysed considering the on current (I ON) and the threshold voltage (V th) variation. Sub-threshold regime has been considered here to detect the charged/neutral biomolecules. Extensive simulations have been done using the SILVACO ATLAS. Sensitivity analysis has been carried out by considering half-filled and full-filled nanogaps with the neutral or charged biomolecules inside the cavity. Significant sensitivity and excellent reduction in short-channel effects has been observed in proposed biosensor.

Multilevel thresholding is a widely used image segmentation technique. However, multilevel thresholding becomes more and more computationally expensive as the number of thresholds increase. Therefore, it is essential to incorporate some suitable optimization technique to make it practical. In this article, a modification is proposed to the Moth-Flame Optimization (MFO) algorithm and then it is applied to multilevel thresholding for image segmentation. Cross entropy is used as the objective function to select the optimal thresholds. A set of benchmark test images are used to evaluate the proposed technique. The Mean Structural SIMilarity (MSSIM) index is used to measure the quality of the segmented images. The results of the proposed technique are compared with the original MFO, PSO, BFO, and WOA. Experimental results and analysis suggest that the proposed technique outperforms other techniques in terms of segmentation quality images and stability. Moreover, computation time required for multilevel thresholding is also reduced to a manageable level.

For computational arithmetic, a full adder is the primary logic units in VLSI applications. A new full adder circuit design has been presented in this article which is based on input switching activity pattern and gate diffusion input (GDI) technique. The adder has been designed in two stages. The first stage is an XOR–XNOR module, whereas, the final stage is for the required outputs. By using the switching activity pattern of inputs and GDI techniques at each stage, the switching activities of the transistors have been minimized. This improves delay, power consumption and computational complexity. The adder has been designed and evaluated by using the synopsis tool and compared with different existing adder cells found in the literature. It is found that the presented adder shows an improvement at least 72.86% and 66.67% in terms of speed and energy consumption, respectively. Extensive performance analyses of the full adder have also been evaluated at 32 nm CMOS and 32 nm CNFET technology node which shows promising performances in both the technology nodes.

In this paper, a novel method is proposed for the first time to achieve multiple threshold voltage (VT) for Silicon Nanotube FET. Using TCAD simulator, it is shown that threshold voltage can be varied by tuning the halo doping and tube diameter of Silicon Nanotube FET. The typical method to attain multiple threshold voltages is to select the pertinent gate work-function for individual devices. But this is not practically feasible due to the difficult process complexity. In this work, the tuning of halo doping and nanotube diameter can be elected to provide three possible values of VT at 14-nm technology node. Furthermore, short-channel effect like Drain Induced Barrier Lowering (DIBL) is also found to be reduced with HALO doped region at source side. It is also observed that the threshold voltage decreases while increasing the tube diameter. Moreover, HALO doping at drain side is found showing a significant improvement in analog/RF performances of the device which eventually makes the device more suitable for radio-frequency integrated circuit applications.

Classifications of eight different varieties of rice grain are discussed in this study based on various texture models. Four local texture feature extraction techniques are proposed and three sets of texture features (SET‐A, SET‐B and SET‐C) are formed, for the classification task. Performances of the proposed feature sets are compared with the existing techniques based on, run length matrix, co‐occurrence matrix, size zone matrix, neighbourhood grey tone difference matrix and wavelet decomposition, towards classification of rice grain using a back propagation neural network (BPNN). The proposed techniques are also tested against publicly available data from Brodatz's texture data set and their results are compared with other techniques. The classification accuracy by the BPNN classifier is also compared with other statistical classifiers namely, K‐nearest neighbour, linear discriminant classifier and Naive Bayes classifier. It is found that, the proposed feature sets yield better classification results on both rice data and Brodatz's data. Results show that, feature SET‐B, is able to classify rice grain with an average classification accuracy of 99.63% with a minimum of six features.

Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

In this manuscript, the impact of dielectric pocket on analog/radio-frequency (RF) performances of SOI-TFET is investigated. The inclusion of a dielectric pocket to SOI-TFET has been found to have ...

This paper describes the classification of four different varieties of rice grain based on four sets of features, namely morphology, colour, texture and wavelet. The classification is carried out on single rice kernel using image pre-processing steps followed by a cascade network classifier. The performance of the classifiers based on the above feature sets is also compared. It is found that morphological feature is more suitable for the classification of rice kernels, as compared to other features. The number of input features is reduced by a feature selection process using statistical analysis system (SAS) software. The classification accuracy based on selected features is compared with that of original features using different classifiers. It is found that the selected features are able to provide classification accuracy very close to the original features. The performance of the proposed cascade classifier is also tested against standard datasets from the University of California, Irvine (UCI), and the results are compared with other classifiers. The results show that the proposed classifier provides better classification accuracy as compared to other classifiers.

This paper describes a newly-created image database termed as the NITS-IQA database for image quality assessment (IQA). In spite of recently developed IQA databases, which contain a collection of a huge number of images and type of distortions, there is still a lack of new distortion and use of real natural images taken by the camera. The NITS-IQA database contains total 414 images, including 405 distorted images (nine types of distortion with five levels in each of the distortion type) and nine original images. In this paper, a detailed step by step description of the database development along with the procedure of the subjective test experiment is explained. The subjective test experiment is carried out in order to obtain the individual opinion score of the quality of the images presented before them. The mean opinion score (MOS) is obtained from the individual opinion score. In this paper, the Pearson, Spearman and Kendall rank correlation between a state-of-the-art IQA technique and the MOS are analyzed and presented.

A new tubular field effect transistor (FET) device named silicon nanotube tunnel field effect transistor (Si-NTTFET) has been proposed which is emerged out of structural engineering and the gate dielectric engineering. The proposed structure offers better immunity towards short channel effects (SCEs) because of the combined effect of minimal doping at the drain side and control of channel region due to the double gate. The tunnelling probability is also improved due to narrow energy band variation. The high k dielectric material such as HfO 2 enhances the ON current by a factor of 3 and 14 as compared to Si 3 N 4 and SiO 2 gate dielectric, respectively.

A new multilevel thresholding based image segmentation technique is developed which utilizes Masi entropy as an objective function. Thresholding is an important image segmentation technique. It may be divided into two types such as bi-level and multilevel thresholding. Bi-level thresholding uses a single threshold to classify an image into two classes: object and the background. For an image containing a single object in a distinct background, bi-level thresholding can be successfully used for segmentation. But in case of complex images containing multiple objects, bi-level thresholding often fails to give satisfactory segmentation. In such cases, multilevel thresholding is generally preferred over bi-level thresholding. However, computational complexity of multilevel thresholding increases very rapidly with increasing number of thresholds. Metaheuristic algorithms are generally used to optimize the threshold searching process to reduce the computational complexity involved in multilevel thresholding. In this paper, Particle Swarm Optimization (PSO) along with Masi entropy is proposed for multilevel thresholding based image segmentation. The proposed technique is evaluated using a set of standard test images. The proposed technique is compared with the recently proposed Dragonfly Algorithm (DA) based technique that uses Kapur’s entropy as objective function. The proposed technique is also compared with PSO based technique that uses minimum cross entropy (MCE) as objective function. The quality of the segmented images is measured using Mean Structural SIMilarity (MSSIM) index and Peak Signal-to-Noise Ratio (PSNR). The experimental results suggest that the proposed technique outperforms Kapur’s entropy and gives very competitive result when compared with the MCE based technique. Further, computational complexity of multilevel thresholding is also greatly reduced.

Multilevel thresholding is widely used in brain magnetic resonance (MR) image segmentation. In this article, a multilevel thresholding-based brain MR image segmentation technique is proposed. The image is first filtered using anisotropic diffusion. Then multilevel thresholding based on particle swarm optimization (PSO) is performed on the filtered image to get the final segmented image. Otsu function is used to select the thresholds. The proposed technique is compared with standard PSO and bacterial foraging optimization (BFO) based multilevel thresholding techniques. The objective image quality metrics such as Peak Signal to Noise Ratio (PSNR) and Mean Structural SIMilarity (MSSIM) index are used to evaluate the quality of the segmented images. The experimental results suggest that the proposed technique gives significantly better-quality image segmentation compared to the other techniques when applied to T2-weitghted brain MR images.

This paper presents an analysis on electronic, mechanical and optical properties of cubic titanium dioxide using Orthogonalized Linear Combinations of Atomic Orbitals (OLCAO) basis set under the framework of Density Functional Theory. The structural property, namely lattice constant ‘a’, and the electronic properties such as, the band diagram, density of states (DOS) have been studied and analyzed. Whereas, the mechanical properties like, bulk moduli, Shear moduli, Young’s Moduli, poison’s ratio have also been investigated thoroughly. Moreover, optical properties such as refractive index, extinction co- efficient, reflectivity, absorption coefficient have been studied and analyzed thoroughly. The results are compared with previous theoretical and experimental results. It is found that, DFT based simulation produces results which are approximation to experimental results, whereas, the calculated values of elastic constants are better than the previous theoretical and experimental values.

The impact of high- k dielectric pocket (DP) on the ambipolar conduction of tunnel field-effect transistors (TFETs) is demonstrated using two-dimensional Technology Computer Aided Design (TCAD) simulations. In the proposed structure of TFETs, an optimised portion of the upper drain region is replaced with a high- k DP at the channel-drain interface. It is demonstrated that due to the enhancement of the depleted drain region under DP, the minimum tunnelling width at channel-drain interface increases, and attains a maximum value for an optimum length and thickness of DP. Eventually, this increment in the minimum tunnelling width leads to a significant reduction in ambipolar conduction in TFETs. Furthermore, it is shown that performance parameters including the ON-state current, subthreshold swing and output characteristics are not affected by the presence of the proposed DP. Even, the gate-to-drain capacitance is reduced with the inclusion of DP at the channel-drain interface, thus leading to an improved cut-off frequency of TFETs. Moreover, it is also demonstrated that only a 10 nm of gate-on-drain overlapping along with this DP is capable of eliminating the ambipolarity completely for even a higher gate voltage of -0.8 V.

Enhancing solar cell efficiency is one of the most challenging and demanding topics for PV researchers. An ab initio study is done here on the structure of crystal, formation energies, electronic structure, the density of states, effective mass, and optical properties of pure and S-doped, Fe-doped, and Fe-/S-doped anatase TiO2. Co-doping causes a significant reduction in the bandgap, suppresses the charge carrier’s recombination rate, and shifted absorption spectra from UV to the visible region. Hence, co-doped anatase TiO2 with Fe and S is more favorable as a buffer layer of the solar cell compared to S-doped and Fe-doped TiO2. The forecasted values of all quantities will benefit researchers to examine these materials for further photovoltaic applications.

The compressor is a useful element that is widely used in VLSI circuits and systems. It is generally used as a processing element. In this work, a 4-2 compressor has been designed with XOR-XNOR module and multiplexer module. The XOR-XNOR module is consists of six transistors and the multiplexer is consists of transmission gate. The compressor has been designed and simulated in Synopsys tool by using 90 nm CMOS technology. Average power dissipation, worst case delay and power delay product are computed. The same has been observed by varying the supply voltage. A study of the performance comparison has been carried out with existing compressors. It is found that the proposed compressor has low power consumption and the best PDP.

This paper presents a study and analysis applicable to structural, electronic, optical and mechanical properties of one of rare variant of Titanium dioxide (TiO 2 ) i.e. brookite using self-consistent Orthogonalized Linear Combination of Atomic Orbitals method (OLCAO) under the framework of Density Functional Theory (DFT). Structural, electronic and mechanical properties are investigated using Generalized Gradient Approximation (GGA) with Perdew-Burke-Ernzerhof (PBE), Perdew-Burke-Ernzerhof solid (PBES), Becke-Perdew86 (BP86), Perdew Wang91(PW91) and Becke88-Perdew Wang91 Correlation(BPW91) as exchange-correlation. Correlation of electronic and optical properties are performed using GGA-PBES and Meta-gga(MGGA)-Tran and Blaha(TB09). The observed data are match up with the previously reported computational as well as experimental data. Obtained lattice parameters using GGA-PBES, Bond length between Ti and O using PBE and BPW91, bandgap value using MGGA-TB09 and bulk modulus using PW91 and BPW91 matches very well with the experimental values. Comparision using GGA-PBES and MGGA- (TBO9) shows that calculated dielectric constant and refractive index as obtained using GGA-PBES are higher than MGGA approach and optical absorption for brookite TiO 2 occurs in UV region while absorption spectrum using MGGA shifts the wavelength towards the lower energy band of EM spectrum.

To remove simultaneously the ambipolar conduction and enhance HF performances, we propose a promising configuration of DG-TFET with asymmetric gate–drain overlap (ASGDO DG-TFET) in which only back gate is overlapped with drain region. This proposed structure of DG-TFET removes the trade-off between ambipolarity and HF performances by taking the merit of gate–drain overlap in terms of reduction in ambipolarity and suppressing its demerit with reduced gate–drain parasitic capacitance. Using 2-D simulation, it is observed that ambipolar conduction can be suppressed to a large extent in DG-TFET with only 20 nm of back gate–drain overlap, thus not limiting the scaling of drain region compared to symmetric gate–drain overlap DG-TFET (SGDO DG-TFET). Due to the presence of enhanced depletion layer in the drain region caused by a large vertical electrical field, tunneling width at drain–channel interface is found to be maximum in the proposed device, which eventually prevents the charge carriers to tunnel. Furthermore, ASGDO improves the HF performance parameters such as cutoff frequency and gain–bandwidth product compared to SGDO due to reduction in gate–drain parasitic capacitance, and this improvement is found to be consistent while scaling down the channel length.

Structural, electronic, and optical properties of ferroelectric material, Lithium niobate (LiNbO3) are explored and studied using two different techniques namely, OLCAO-MGGA-TB09+c and OLCAO-GGA-PBES + U under the framework of density functional theory (DFT). The electronic properties such as band diagram, the effective mass of charge carriers, the total density of state (TDOS), and partial density of state (PDOS) are investigated in depth. Band gap values obtained using MGGA-TB09+c is 3.79 eV whereas, it is 3.78 eV for GGA-PBES + U. Furthermore, several optical properties such as dielectric constant, reflectivity, refractive index, optical conductivity, loss function, and absorption coefficient have also been extracted. It is seen that the results so obtained are consistent with experimental data which shows the soundness of our calculations. From the statistical analysis, it is found that both the techniques provide very good results on electronic and optical properties of LiNbO3 compared to existing computational work as both give an approximation of experimental data. The methods presented here will be useful for researchers to get accurate results on structural, electronic, and optical properties of other materials.

In this paper, the effect of pressure on various properties of brookite and rutile TiO2 has been investigated along with a phase transition study. It is seen that brookite gets transformed to rutile TiO2 at 5 GPa pressure. The band gap of brookite and rutile TiO2 are direct in nature with values of 3.41 eV and 2.98 eV. Pressure-dependence of the Elastic compliance coefficients, elastic stiffness coefficients, bulk modulus, shear modulus, Young modulus, Poisson's ratio, B/G ratio, Vickers hardness, Lame constant has been calculated at 0, 3, 5 GPa pressures for brookite TiO2 and at 0,5,10,15, and 20 GPa pressures for rutile TiO2. The shear anisotropy factors (A100, A010, and A001) along {100},{010}, and {001} planes have been estimated at different pressure for brookite TiO2 as well as the shear anisotropic factors along {100} and {001} shear planes is estimated for rutile TiO2. Moreover, anisotropy factors (AB),(AG), and (AU) have been estimated at different pressure for brookite TiO2 and rutile TiO2. Furthermore, the dielectric constant is determined to investigate other optical properties for both the structures at different pressures. A pretty good agreement has been obtained between our findings and experimental data.

In this work, the impact of interface trap charges (ITCs) on electrical characteristics of dielectric pocket SOI-TFET (DP SOI-TFET) proposed for the reduction of ambipolar conduction and improvement of high-frequency (HF) performances has been demonstrated in details. The reliability of DP SOI-TFET has been examined by analysing the impact of varying polarity and density of ITCs on dc and analog/HF performances of the proposed device. Through TCAD simulations, it has been shown that donor and acceptor ITCs existing at the interface between drain region and dielectric pocket (i.e. Si/DP) have significant impact on the parameters such as OFF-state current, ambipolar conduction, parasitic capacitances, output resistance, and cut-off frequency of DP SOI-TFET. Furthermore, a comparative analysis has been carried out between the conventional and DP SOI-TFET under influence of traps, and it has been found that performances of the proposed device are further improved by the existence of acceptor ITCs at higher negatively biased gate. Even though, the existence of donor ITCs at Si/DP interface has been found degrading the performances of the proposed DP SOI-TFET, simulation results suggest that dc and analog/HF figure of merits are still superior in the proposed device as compared to those in the conventional SOI-TFET.

Multilevel thresholding is one of the most important areas in the field of image segmentation. However, the computational complexity of multilevel thresholding increases exponentially with the increasing number of thresholds. To overcome this drawback, a new approach of multilevel thresholding based on Grey Wolf Optimizer (GWO) is proposed in this paper. GWO is inspired from the social and hunting behaviour of the grey wolves. This metaheuristic algorithm is applied to multilevel thresholding problem using Kapur's entropy and Otsu's between class variance functions. The proposed method is tested on a set of standard test images. The performances of the proposed method are then compared with improved versions of PSO (Particle Swarm Optimization) and BFO (Bacterial Foraging Optimization) based multilevel thresholding methods. The quality of the segmented images is computed using Mean Structural SIMilarity (MSSIM) index. Experimental results suggest that the proposed method is more stable and yields solutions of higher quality than PSO and BFO based methods. Moreover, the proposed method is found to be faster than BFO but slower than the PSO based method.

Multilevel thresholding is a popular image segmentation technique. However, computational complexity of multilevel thresholding increases very rapidly with increasing number of thresholds. Metaheuristic algorithms are applied to reduce computational complexity of multilevel thresholding. A new method of multilevel thresholding based on Moth-Flame Optimization (MFO) algorithm is proposed in this paper. The goodness of the thresholds is evaluated using Kapur's entropy or Otsu's between class variance function. The proposed method is tested on a set of benchmark test images and the performance is compared with PSO (Particle Swarm Optimization) and BFO (Bacterial Foraging Optimization) based methods. The results are analyzed objectively using the fitness function and the Peak Signal to Noise Ratio (PSNR) values. It is found that MFO based multilevel thresholding method performs better than the PSO and BFO based methods.

A novel 9T-SRAM architecture is proposed in this paper. It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell. The proposed cell consists of nine transistors with separate read/write ports. It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design metrics. The main objective of the proposed architecture is to minimize the leakage current in an SRAM cell while improving the stability and reducing the read/write delays. The above design metrics of the circuit are compared with the conventional 6T, LP10T and WRE8T SRAM cells under process and temperature variations. It is observed that as compared to conventional SRAM, the proposed 9T SRAM architecture (8 × 16 arrays) reduces static power consumption by 98%, improves the read and write stability by 66.07 and 10.51% respectively. Again, the write delay is reduced to about 95% while read delay is minimized to about 64.1% under different body-bias voltages.

In literature, oriented filters are used for low-level vision tasks. In this paper, we propose use of steerable Gaussian filter in image quality assessment. Human visual system is more sensitive to multidirectional edges present in natural images. The most degradation in image quality is caused due to its edges. In this work, an edge based metric termed as steerable Gaussian filtering (SGF) quality index is proposed as objective measure for image quality assessment. The performance of the proposed technique is evaluated over multiple databases. The experimental result shows that proposed method is more reliable and outperform the conventional image quality assessment method.

This paper investigates on the structural stability and electronic properties of titanium dioxide (TiO2) nanowires of different novel shapes using first- principle based density functional approach. Out of linear, ladder, saw tooth, square, triangular, hexagonal, and octahedron shaped atomic configuration, the ladder shape atomic configuration is energetically most stable. After computation of lattice parameters as well as various mechanical properties of nanowire TiO2, it is seen that highest bulk moduli is obtained for triangular TiO2 nanowire which shows the highest mechanical strength for the structure whereas hexagonal configuration has lowest Bulk moduli which shows the lowest mechanical strength for the structure. Analysis of various electronic properties show that different configurations of TiO2 nanowires can have different utility as solid state materials.

In this work we have studied the impact of variation of k dielectric constant on Silicon Nano Tube FET for low power and high speed applications. The Silicon Nano tubular structure offers better immunity towards short channel effects (SCE‘s) because of the better control of channel region due to the double gate all around. By cause of gate engineered structure high K value structures possess high value of electron velocity as compare to low k dielectric structure, which helps in improving the efficiency of carrier transport. In this work we have considered a Silicon Di-oxide(SiO 2 ), Silicon Nitride(Si 3 N 4 ), Hafnium Oxide(HfO 2 ), Hafnium Silicate (HfSiO 4 ), Tin oxide (SnO 2 ) and Titanium Oxide (TO 2 ) as a gate dielectric. It has been found that when the high k is replaced with SiO 2 then the switching performance of the device is enhanced which makes it suitable for the SOC applications. From the analysis it has been found that HFO 2 in SINTFET will be a superior alternative for future tubular FET devices

In this brief, the reliability of SOI-TFET with dielectric pocket (DP SOI-TFET) has been investigated in the presence of fixed trap charges at the interface between dielectric pocket (DP) and drain region. During numerical simulation, both types of trap charges like donor (i.e. positive) and acceptor (i.e. negative) have been considered to analyse the impact on the performance of SOI-TFET having DP in drain region used for reduction of ambipolar conduction. We have compared the device performances such as ambipolar conduction, and OFF-state current of conventional SOI-TFET with both low and high- $\pmb{k}$ DP SOI-TFET in the presence of interface trap charges (ITCs). It has been found that SOI-TFET is more immune to interface trap charges when high- $\pmb{k}$ material is used as DP compared to low- $\pmb{k}$ . Since, high- $\pmb{k}$ provides even more reduction in ambipolar conduction as compared to low- $\pmb{k}$ , it can be preferred to be used a dielectric pocket in SOI-TFET.

This paper investigates on the structural stability and electronic properties of titanium dioxide (TiO 2 ) nanowires of different shapes using first-principle based density functional approach. Out of linear, ladder, and saw tooth shaped atomic configuration, the ladder shape atomic configuration is energetically most stable. After computation of lattice parameters as well as various mechanical properties of nanowire TiO 2 , it is seen that highest bulk moduli is obtained for linear TiO 2 nanowire which shows the highest mechanical strength for the structure whereas ladder configuration has lowest bulk moduli which shows the lowest mechanical strength for the structure. Analysis of various electronic properties show that different configurations of TiO 2 nanowires can have different utility as solid state materials.

In this brief, we have investigated a novel structure of double-gate TFET with extended back gate (EBG-DG-TFET) to improve the device performances. In the proposed device, the extended back gate is found to create an overlapped region with both source side as well as drain side which improves the overall performances of DG-TFET. Through two-dimensional numerical simulations, it is demonstrated that the overlapped gate-source region enhances the ON-state current due to reduction in the barrier width at input tunneling interface between source and channel regions, thus improving the current switching ratio of DG-TFET. In addition to improvement in ON-state current, the overlapped gate-source region also improves the subthreshold slope which is found to be lower than that of the conventional DG-TFET. Furthermore, the overlapped gate-drain region is found to remove the ambipolar conduction in DG-TFET when gate is biased with opposite polarity than drain terminal.

Metal oxide semiconductor field-effect transistor (MOSFET) is the main building block in low-power and high-performance very large-scale integration (VLSI) chips for the last few decades. Device scaling is the guiding force toward technological advancements, which allows more devices to be integrated on a single die thereby allowing greater functionality per chip. The ultimate goal of scaling is to build an individual transistor that is smaller, faster, cheaper, and consuming low power. We see an exponential growth in device complexity in today's nanoscaled chip. However, device scaling to deep nanometer regime leads to exponential increase in leakage current and excessive heat generation. Moreover, process variability has caused a serious limitation to further scaling. It is believed that with a mix of chemistry, physics, and engineering, nanoelectronics may provide a solution to increasing fabrication costs and may allow integrated circuits to be scaled beyond the limits of the modern transistor. Carbon nanotube (CNT) and nanowire (NW)-based FETs (CNTFET and NWFET) have been analyzed and characterized in the laboratory and also been demonstrated as prototypes. This work first presents, a detailed explanation on chemical bonding and crystalline structures of these new devices and then an extensive simulation and analysis of CNTFET and NWFET devices and compared the results with conventional MOSFET and double gate MOSFET. From this study, it reveals that these new devices have got some excellent properties and favorable characteristics, which will definitely lead the future semiconductor devices in the post-silicon era.

A multiplier circuit is one of the most important functional blocks of many nano-electronic, control and automation applications. In this work, an energy-efficient multiplier is reported based on a 3:2 compressor. The multiplier has been designed in three different parts. In the first part, a partial product (PP) generator is used. In the second part, the partial products are reduced which is termed as PPP (partial product processing). Whereas in the third step final addition is performed. PPs are produced by using AND gates. The PPP is designed in two-phase. In the first phase, the Wallace tree logarithm has been used to reduce the PPs. Whereas, in the second phase the PPs are reduced by using energy-efficient half adder and 3:2 compressor. At last, in the third step, by using a carry-save adder final addition has been computed. The performance analysis of the designed multiplier is evaluated and compared with other multiplier circuits. The multiplier shows performance improvements by 20.55%-46% for the power supply variation from 1.2 V to 0.6 V. All the simulations and analyses have been carried out by using the Synopsys EDA tool.

Leakage power dissipation is a serious concern in deep nanometer devices. Low power design methodology is often adopted in VLSI circuits and systems to minimize power; however, this is achieved at the cost of performance penalty. In this paper, we first review the existing circuit techniques for leakage minimization. A new circuit technique is then proposed which is designed intelligently by mixing a pair of dynamic threshold sleep transistors and a pair of helper transistors. The performance of the proposed technique is investigated in terms of area, power, delay and power---delay product. Extensive SPICE simulation with 32 nm process technology shows a significant reduction in power, delay and power---delay product.

A dynamic threshold voltage control strategy is presented in this paper to minimize leakage power while enhancing the speed and stability. The threshold voltage of driver and access transistor are tuned dynamically through a novel body-bias controller circuit. The word line signal level controls the action of the proposed body-bias controller. In order to reduce subthreshold leakage current, the threshold voltage of NMOS access and driver transistors are adjusted to a high value by applying a reverse body-bias. On the other hand, forward body-bias lowers the threshold voltage of NMOS access transistor thereby enabling faster read and writes operation. Simulation results shows that the proposed design is much better than conventional and other SRAM cells such as, NC SRAM, PP SRAM, WRE8T. The amount of leakage power reduction is as high as 41.071 % over conventional 6T SRAM cell when tested on (8 × 16) SRAM array. Whereas, the improvement in read and write delay is 30 and 15.81 % respectively.

This study describes the classification of four varieties of bulk rice grain images using back-propagation neural network (BPNN). Eighteen colour features, 27 texture features using grey-level co-occurrence matrix, 24 wavelet features and 45 combined features (combination of colour and texture) were extracted from the colour images of bulk rice grains. Classification was carried out on three different data set of images under different environmental conditions. It is seen that BPNN is able to classify faithfully the four varieties of rice grain even with a poor image quality. It is also found that classification based on reduced wavelet features outperform the classification using all other features (such as colour, texture features taken separately) for two data set of images with minimum resolution. The authors have further compared the proposed BPNN technique with other classifiers such as support vector machine, k-nearest neighbour and naive Bayes classifier on all the three data sets. It is found that the average classification accuracy of more than 96% was able to achieve using BPNN consistently on all different features for each data set.

Leakage power dissipation is the dominant contributor of total power dissipation in nanoscale complementary metal oxide semiconductor (CMOS) integrated circuits. CMOS technology scaling demands for a reduced power supply, low threshold voltage, high transistor density and reduced oxide thickness, which has led to significant increase in leakage power especially during standby mode. Here in this paper, at first we review some of the existing techniques for leakage minimization and pointed out their merits and shortcomings. We then propose a novel transistor level approach called leakage control NMOS transistor (LCNT) for leakage minimization. The proposed technique inserts two leakage control transistors (all N-type) within a standard CMOS logic circuit. The gate terminal of the leakage control transistors are connected with the drain of the pull-up transistors. Performance of the proposed technique is investigated in terms of area, power, delay, and power-delay product applying on some basic gates and benchmark circuits. The performance metrics of the proposed LCNT are then compared with other existing techniques. Extensive SPICE simulations were carried out using 32 nm predictive technology model. Simulation results indicate that the proposed technique is quite efficient in minimizing the leakage power which is found out to be 48.4 %.

Ever increasing demand for portable and battery-operated systems has led to aggressive scaling. While technology scaling facilitates faster and high-performance devices, at the same time it causes excessive power dissipation especially the leakage. Leakage power dissipation is now a dominating component of total power consumption in today's high-performance chip. So there is a tremendous need to limit the power dissipation in high-density chips, which has initiated many innovative techniques to develop in the design of low power circuits and systems. Nano-scaled very large-scale integration (VLSI) chips have ultra-thin gate oxide, very low threshold voltage, and have short channels. Therefore, leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. In this paper, we present a general review of the state-of-the-art circuit level leakage minimization techniques since 1995. It also conceptually classifies the different techniques for leakage minimization. Furt...