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Multilevel topologies with SiC devices for medium voltage (MV) motor drive have advantages to reduce the harmonics and device voltage stress as well as to increase the efficiency. However, with the application of SiC devices, the reflected wave phenomenon still happens in multilevel motor drive due to its high dv/dt, resulting in overvoltage at motor terminals. This paper proposed a T-type circuit based active reflected wave canceller (ARWC) to suppress the overvoltage of a M-level motor drives with reduced voltage rating of Vdc/(M-1). A coupled inductor is applied to isolate the ARWC output and the main inverter. In addition, the coupled inductor is designed with a small resistor to allow low current flowing into ARWC. The proposed ARWC configuration can be applied for general multilevel topologies. A 3-level ANPC converter with 3.3 kV SiC device is built in the laboratory. A 1.2 kV SiC module is applied in the proposed ARWC. The experimental results at 1.6 kV Vdc and 16 A (RMS) load current with and without proposed ARWC are provided and compared to verify the validity of proposed method.

Junction temperature fluctuation is the main cause of failure of power devices including silicon carbide (SiC) MOSFETs, and active junction temperature control is an effective way to improve their reliability. Most existing methods of active junction temperature control rarely consider the system efficiency and the complexity of hardware implementation, which limits their applications. This paper proposes an active junction temperature control method for SiC MOSFETs based on a resistor-less gate driver, which consists of two auxiliary MOSFETs with adjustable gate-source voltages. Hence, the switching loss of the SiC MOSFET can be continuously and accurately adjusted to mitigate the efficiency suffer with the junction temperature control. The power loss model of SiC MOSFETs with the proposed gate driver was established. The design principle of the junction temperature controller is introduced. The experimental results show that the junction temperature fluctuation is reduced by 24.1%, and that the lifetime of the SiC MOSFET is prolonged by 3.92 times via using the proposed junction temperature control method. The energy loss of the prototypical inverter is decreased by 4.15% over the whole testing period. The experiment was conducted with SiC MOSFETs, and the proposed method is also suitable for other Sibased semiconductor devices.

Multiplexing circuits in pixelated PET detectors are being studied with the goal of minimizing the degradation of detector performance. The purpose of this study was to develop a diode-based symmetric charge division (SCD) circuit with reducing the crosstalk caused by the leakage currents of adjacent channels connected in rows and columns. Four different SCD circuits (diode-based SCD with grounding path, diode-based SCD, resistor-based SCD with grounding path and resistor-based SCD) were constructed and their performance was evaluated and compared after being combined with a PET detector consisting of LYSO crystals optically coupled with SiPM. The diode-based SCD circuit with grounding path achieved a crosstalk ratio, energy resolution, coincidence timing resolution (CTR) and mean peak to valley ratio of 0.02, 14.3%, 0.5 ns and 27.9: 1, respectively; the diode-based SCD circuit achieved 0.03, 15.9%, 0.7 ns and 19.4: 1, respectively; the resistor-based SCD circuit with grounding path achieved 0.04, 14.5%, 0.9 ns and 19.4: 1, respectively; the resistorbased SCD circuit achieved 0.05, 17.8%, 1.8 ns and 17.7: 1, respectively. These results indicate that the proposed SCD has the potential to improve not only the crosstalk but also the energy linearity, energy resolution, and coincidence timing resolution characteristics in PET detectors.

In single-phase voltage source inverters (VSI) under a weak grid, the frequency coupling, caused by the asymmetrical system structure, poses a challenge to system modeling and controller design. In this article, a frequency coupling suppression control strategy is presented, where all the frequency coupling components in the current reference are eliminated. As a result, the single-phase grid-tied inverter is directly modeled as a simple single-input single-output (SISO) admittance rather than a complicated multiple-input multiple-output (MIMO) admittance matrix. The SISO admittance model is simple, compact, and accurate, which facilitates design-oriented analysis. The admittance characteristic analysis shows that the Sym-PLL has a critical impact on the system stability under weak grid conditions. To improve the system stability, a prefilter-based impedance-shaping control strategy is proposed by mitigating the negative resistor behavior of the Sym-PLL. Finally, simulations and experimental results validate the effectiveness of the frequency-coupling suppression control strategy.

In this paper, a robust wireless power transfer (WPT) system considering a wide variation in load resistance and coupling coefficient is proposed for electric vehicles (EVs) charging. Here, a new implementation of the parity-time(PT)-symmetric circuit using a phase synchronization method is presented, in which a power-adjustable negative resistor is constructed only by a single-stage inverter. Moreover, based on the PT-symmetric circuit, a control strategy that does not require dual-side communication and extra dc-dc converters is developed for battery charging. Theoretical analysis shows that constant current (CC) and constant voltage (CV) outputs independent of load and position can be achieved, and the charging mode can be switched automatically. A scaled-down prototype with an 8 A charging current and a 120 V charging voltage is built to verify the feasibility of the proposed method. Experimental results demonstrate that within the transfer distance of 10-25 cm, the CC/CV outputs can be maintained during the charging process.

Different from typical circuit breakers, breakers used to switch AC filters in convertor stations have to operate frequently according to the real-time operation mode and daily load changes. Therefore, the performance of filter breakers decreases very quickly, which leads to frequent accidents. Both preinsertion resistors and controlled switching devices can suppress switching transients. In this paper, a comparative analysis of whether a controlled switching device and preinsertion resistor should be adopted is carried out using PSCAD. The transient is calculated as the combined result of the switching angle and preinsertion resistor value, and the optimal configurations are proposed. After determining the resistor value and whether a controlled switching device should be included, the reference voltage of the arrester should be reevaluated.

The existence of inrush current poses a significant problem during the start-up process within three-phase voltage-source rectifiers. To address this problem, this study proposes a strategy to suppress the inrush current effectively based on the virtual-resistor- control method, while preventing the increase in cost of the system and complexity of the algorithm. First, a mathematical model is established based on the dq coordinate frame, and the primary cause of the inrush current is analyzed. Then, the design process of the virtual-resistor-control method is detailed. Finally, the accuracy and effectiveness of the proposed method are verified by simulations and experiments. The results show that the inrush current can be more than two times the rated current before the addition of the virtual resistor. The start-up process can be realized without the inrush current after the addition of the virtual resistor, it does not need to increase hardware costs, there is no secondary inrush current, and the sensitivity of the parameters and the complexity of control are low.

The stability problem induced by constant power loads (CPLs) is becoming more prominent in more electric aircraft. In this paper, the stabilization issue of DC distribution bus with dual-active-bridge (DAB) converters was investigated. On the basis of voltage regulation, an active damping solution based on model predictive control (MPC) was proposed by explicitly incorporating a stabilization term into a cost function. In this solution, to ensure the output voltage performance with a smaller steady-state error and a dynamic voltage overshoot, an adaptive weighting factor was adopted with a stray resistor taken into account. A theoretical design of the weighting factors was performed using the artificial neural network (ANN) method. The proposed approach could supply stiff load voltage and provide good DC-link voltage stabilization, as well as load voltage overshoot clamping. These findings were verified through the computer simulations and practical experiments of an 800 W converter prototype with a switching frequency of 20 kHz, an input voltage of 270 V, and an output voltage of 270 V.

Highly stable on-chip frequency references offer the possibility of replacing crystal oscillators in many cost- and form-factor-constrained applications. However, achieving good frequency stability in a power-efficient manner across process, voltage, and temperature variations possess many design challenges. This article describes these challenges and presents a method for improving the integrated RC oscillator's frequency accuracy by overcoming them. We show that the impact of resistor temperature coefficient (TC) on the accuracy of output frequency can be mitigated by using a parallel combination of two switched resistors that are digitally controlled by pulse-density modulated sequences. By trimming at only two temperatures, a prototype frequency-locked loop (FLL)-based 32-MHz oscillator fabricated in a 65-nm CMOS process achieves an inaccuracy of 530 ppm (8.4 ppm/°C), 80-ppm/V voltage sensitivity, 2.5-ppm Allan deviation, and 1-μW/MHz power efficiency.

Power system state-space models are often constructed by interconnection of their subsystems (converters, distribution lines, and grid). The interconnection between L-/LCL-filtered converters with the distribution lines subsystems is often realized through a virtual resistor, because they both have the voltage as input, introducing inaccuracy. Moreover, the parameters variations influence not only the eigenvalues, but also the equilibrium point. In this case, the small-signal model has to be reevaluated around the new equilibrium point. For the computation of the equilibrium point, an additional method, e.g., power flow, is conventionally used. However, the variables computed with power flow (e.g., {rm P},Q,{rm V},text{ and }theta) do not always coincide with the state-space model variables, required for the linearization. Furthermore, the traditional power flow does not consider the influence of the voltage-source-converter control system on the grid equilibrium point. This article proposes a nonlinear grid model that does not need the virtual resistor to be interconnected. The proposed model can be used both for equilibrium point computation through the Newton-Raphson method, and it can be linearized around the computed equilibrium point for small-signal analyses. Simulations and experiments are provided.

Virtual synchronous machine (VSM) based high voltage dc systems enhance the inertia of the power system. However, the dynamic interactions between the VSM-based rectifier station, the inverter station, and the grid could induce the system oscillation, which has been investigated in this article. At first, the hybrid ac-dc impedance models of the VSMs considering the coupling between the ac and dc dynamics are established. Then, the relationships between the dc impedance, dq-frame impedance, and the hybrid ac-dc impedance are presented. It is found that the dc impedance of the VSM-based inverter station and the d-d channel impedance of the dq-frame impedance of the rectifier station behave as negative resistors in the low-frequency range. Moreover, a five-dimensional impedance stability criterion based on the hybrid ac-dc impedance and generalized inverse Nyquist criterion is proposed to assess the system stability. The analysis results show that the low-frequency oscillation occurs when the grid short-circuit ratio of the rectifier station is small. Finally, the simulation and experimental results verify the impedance models and the stability criterion.

In order to suppress the crosstalk in gallium nitride (GaN)-based bridge configuration, a novel negative voltage self-recovery gate drive (NVSRGD) is proposed in this paper. The resistor-capacitor-diode voltage divider is applied to establish the negative gate-source voltage and suppress the impact of positive crosstalk. The antiparallel diode is added to constitute low-impedance Miller current path from the driver integrated circuit (IC) to the GaN device. It works together with the self-recovery gate-source voltage to suppress the negative crosstalk, which not only prevents the GaN device from the negative overstress but also reduces the reverse conduction loss during the dead time. The NVSRGD is composed of a few passive components, which are suitable for integrating into the driver IC. The capacitors and resistors of the NVSRGD are designed to determine the negative voltage level and the restore time. Additive separate negative voltage power supplies or active devices are not needed. The double pulse test based on GS66508B verifies the effectiveness of the proposed method for suppressing the positive and negative crosstalk of GaN devices.

An ageing condition monitoring method for the aluminum electrolytic capacitor (AEC) is presented. The target AEC is used in an ac-dc-ac variable speed drive (VSD) which usually contains an LCR network composed of a dc choke, an AEC and a braking branch. The condition of the AEC is monitored through the capacitance value and the equivalent series resistor (ESR) value. The capacitance value and the ESR value are identified by the LCR network response i.e. magnitude gain and phase shift of the network. The existing components of the VSD are fully utilized instead of adding additional current sensors and active devices. Some potential disturbances in field application such as three-phase voltage unbalances are also considered. Experiments are carried out in a 10-kW general-purpose VSD with different AECs. The maximum errors of capacitance value and ESR values identifications are 1.1% and 5.48%, respectively.

High-resolution continuous-time delta-sigma modulators use resistive feedback DACs for low-noise operation. Such DACs have conventionally been switched at the reference end. It turns out that reference-path resistance degrades the performance of these DACs. This problem can be addressed by the virtual-ground-switched resistor DAC. However, moving the switches to the virtual-ground-side degrades alias-rejection of the modulator. This brief analyzes the mechanism of degradation and develops a model to estimate alias rejection. Our theory is supported by simulations and measurements from a prototype modulator designed in a 180 nm CMOS process. We then describe a way to address this problem, and demonstrate its efficacy using layout-extracted simulations.

Source-side virtual synchronous machines (VSG) and load-side virtual synchronous machines (LVSM) are gradually utilized together in the microgrid to provide virtual inertia and damping. However, instability occurs in the islanded microgrid system due to the interaction dynamics between the VSG and the LVSM, which has been investigated in this paper. At first, the dq-frame impedance models of the VSG and the LVSM are established and compared. It is revealed that the d-d channel impedance of LVSM behaves the negative resistor with a V-type magnitude in the low-frequency range, which easily interacts with the d-d channel impedance of the VSG and leads to instability of the system. Thus, the inductor current feedforward control and the additional voltage feedback control are proposed for the VSG to reshape its impedance. It diminishes the impedance magnitude and generates the active impedance of the VSG. In this way, the low-frequency interaction between the VSG and the LVSM can be mitigated. Besides, the proposed control preserves the dynamic performance of the system. Finally, simulations and experiments verify the effectiveness of stability analyses and the proposed suppression method.

This paper presents a temperature sensor suitable for heavily duty-cycled wireless sensor node. To achieve both a fine resolution and a fast conversion time, the proposed temperature sensor embeds a RC network in a 16-bit residue-integrated successive approximation register (SAR) analog-to-digital conversion (ADC). A poly resistor is connected in series with the capacitor digital-to-analog converter (DAC) to develop a temperature-dependent ADC input. The proposed temperature sensor, implemented in 180nm CMOS, achieves a resolution of 20mK in a range of -30-to-100∘C. It shows a resolution figure-of-merit of 3pJ∙K2 while supporting a burst operation in a conversion time of 12μs after wake-up.

In integrated neural signal monitoring systems, pseudo resistor (PR) is widely used to form very large time constant filters, due to its large impedance within an acceptable die area. However, its linearity (the dependency of the resistance to applied voltage) and impedance are limited by the nonlinear MOS transistors in weak inversion, and suffers from process, voltage and temperature (PVT) variations. In this brief, a PR bootstrapped by reusing the operational transconductance amplifier-capacitor (OTA-C) filter is presented, it substantially increases the impedance and linearity to dynamically support lower frequency neural signal applications. It has no need for extra bias scheme on the gate or bulk, which decreases the circuit complexity, die area and power consumption. The proposed circuit implemented in a 0.18-μm CMOS process occupies an area of 0.026 mm2, the impedance of the bootstrapped PR is approximately 94 GΩ, and the high-pass cut-off frequency is reduced to 0.5 mHz.

Uniplanar wideband high-selectivity filtering full-band-isolation baluns are presented in this article utilizing two different types of out-of-phase matching phase shifters. To obtain high-selectivity performance, half-wavelength open-circuit stubs are introduced. In addition, a single resistor is used for favorable output matching and high full band isolation. By using parallel-coupled n-line technology, the bandwidth of the proposed balun can be controlled. Furthermore, the cascaded coupled-line sections and matching phase shifters are introduced to extend the impedance transforming. For demonstration, two prototypes with center frequency of 3.5 GHz were designed, fabricated, and measured. As expected, measurements show that the proposed baluns have the advantages of bandwidth control, high full-band isolation, impedance transforming, DC-blocking function, stable phase/amplitude imbalances, wideband out-of-band harmonic suppression and high selectivity.

This paper reports a high-performance, low-power temperature sensor suitable for wireless IoT devices/RFID tags. The system utilizes a mostly digital approach to achieve energy-efficient, sub-μW operation with a resistor-based temperature sensor. A sampled, incomplete-settling, switched-capacitor-based Wheatstone bridge is read out using a digital frequency-locked loop (DFLL) while harnessing the quasi-periodic limit cycles to reduce in-band noise. Implemented in a 65 nm CMOS process, it consumes 310 nW and achieves 9.8 mK resolution in a 10 ms conversion time. This results in a 297 fJ∙K2 figure-of-merit (FoM) and low energy (3.1 nJ/meas.).

We report a large submillimeter high-speed arrayed photodetector (PD) with a single-output design for high optical-alignment robustness free-space optical (FSO) communications. To realize a large photodetective area with a single-output design of over 10 Gbps, 8 × 8 multi-pixel PDs were designed and fabricated in a series–and-parallel network. To avoid sacrificing the frequency response, we successfully developed a large photodetective area PD, as large as 0.4 mm × 0.4 mm, with the same frequency response (8.5 GHz) as that in a small single PD (40-μm diameter worth). With the photodetector design and its characteristics, a high data-rate FSO demonstration of up to 25 Gbps for 10-m FSO communications was presented.

In this paper, we classify the instantaneous response of resistors with memory into three types: linear (L), separable nonlinear (SN), and non-separable nonlinear (NSN). A particular model of an NSN-type memristive device is introduced and used to demonstrate the possibility of rich dynamics in the memristor-capacitor circuit subjected to a sinusoidal voltage. In particular, our numerical simulations reveal the regimes of double period oscillations, multiple period oscillations, and chaotic oscillations. The comparison with L-type and SN-type memristive devices described by the same differential state equation indicates the importance of the NSN-type response to achieve such complex dynamics in the memristor-capacitor circuit with a first-order memristive device. Moreover, we demonstrate that a compound NSN-type memristive device can be assembled using one L-type memristive device, two resistors, and two diodes. The complex behavior of such compound devices is verified using SPICE modeling.

In this letter, an ultra-wideband (UWB) antipodal tapered slot antenna with reflectionless notched band is proposed and investigated. The proposed antenna uses an integrated absorptive bandstop filter (ABSF), consisting of two quarter-wavelength open-circuit stubs and a 50 resistor, to form a reflectionless notched band. Consequently, the input energy at the notched frequency is absorbed by the resistor rather than reflected. An antenna prototype is designed and fabricated to validate the design. Both simulated and measured results present that the realized gain drops over 40 dB at 5.5 GHz, and the reflection coefficient is below -10 dB from 3.1 to 10.6 GHz. Besides, a low ringing level of -23.4 dB of the measured reception pulse shows a good time-domain performance. Therefore, the proposed antenna could be applied in UWB short-pulse system to inhibit the 5-GHz WLAN interference.

The modified LCL (MLCL) is commonly applied in PV string inverters to suppress the leakage current and enhance the EMI performance of the grid current. However, the potential risk of resonance appears in the common mode (CM) loop caused by the MLCL filter. In this paper, the CM model of the inverter is firstly built considering the inductance saturation. It is found that the variable inductor brings phase margin decreasing problem and additional resonance points in the CM loop. To suppress the CM resonance (CMR), novel passive and active damping strategies are explored in this paper. The improved passive damping (IPD) strategy is realized by introducing a paralleled RC unit which greatly reduces the damping resistor losses without affecting the damping performance. Besides, a novel active damping strategy (NAD) is proposed to compensate the time delay and to raise the phase margin. Moreover, considering the gradient mutation issue brought by the discontinuous pulse width modulation (DPWM) scheme, an anti-saturation PWM (ASPWM) scheme is applied to eliminate the oscillation. Finally, experiments are conducted on an 80 kW PV string inverter. After applying the proposed CMR damping strategy with the ASPWM scheme, CMR is fully eliminated in the whole power range despite the grid condition.

In this paper, temporal gas temperature in plasma was measured by Rayleigh scattering in a passive way since synchronization was difficult due to the randomness of current pulses. The plasma was generated between a 10 mm pin-to-plane gap connected to a H.V DC voltage through a 130 MΩ resistor and a skin sample was placed on a grounded plate. Even the plasma can be touched by a human hand without any feeling of warmth, the peak temperature could be 337 K then decrease to 295 K over 60 μs at 1 mm. Moreover, the applied voltage dramatically affects peak current and the peak temperature. Therefore, the transient “high” temperature cannot be touched and the so-called “cold” plasma might not be “cold”.

In this article, a novel circuit is proposed to synthesize absorption common-mode filters (A-CMFs) in only one stage, which can be implemented with different kinds of transmission lines. This proposed one-stage absorption circuit has been derived with analytical equations, and design formulas are found to determine circuit parameters. To validate the proposed circuit and derived formulas, an intuitional structure composed of a meander slotline (MSL), a straight differential pair, and one resistor is proposed. Moreover, a technique named meander asymmetrical coplanar strip (MACPS) has also been developed to reduce the size of MSL-type A-CMF by up to 26%. Finally, the proposed test sample of MACPS-type A-CMF is fabricated in a two-layer printed circuit board (PCB) and measured. The common-mode (CM) noise absorption efficiency of above 80% can be obtained from 2.33 to 2.67 GHz to eliminate CM noises in the Wi-Fi 2.4 GHz band. Besides, the MACPS-type A-CMF provides an excellent differential-mode (DM) signal integrity. The −3 dB bandwidth of DM insertion loss can reach 7.5 GHz, and the measured eye diagram of the proposed work is identical to that of the reference board even the transmitted data rate is up to 16 Gb/s. To our best knowledge, the smallest A-CMF implemented in a two-layer PCB is achieved in this article with the electrical dimension being only 0.0358 λg2.

In this brief, a novel pseudo-differential low-transconductance amplifier is proposed based on the bootstrapping technique. The transconductor is implemented using two voltage follower topologies as amplifiers with their outputs connected to both terminals of a resistor, thus bootstrapping the voltages at these terminals to increase the equivalent resistance value, and achieve a very low transconductance without the need for large passive components. In this way, a highly-linear compact structure is designed whose transconductance can be tuned by external current sources. The circuit was fabricated in a standard 0.18μm CMOS process. The experimental results show a tunable transconductance in the range of tens of nA/V, with a total harmonic distortion lower than -40dB at 350mVpp@1kHz. The power consumption of the amplifier is 4μW under a 1.8V supply voltage. This work was supported by CONACYT through the Doctoral Grant 467255 and the Research Project CONACYT CB-2015-257985

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 GΩ and 700 GΩ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz.

A novel quasi-reflectionless bandpass filter (BPF) using double-sided parallel-strip line (DSPSL) is proposed in this letter. It is composed of a BPF and two symmetric absorptive bandstop filters (ABSFs) terminated by a pair of resistors that can dissipate the input untransmitted signal energy. Through detailed analysis, the high characteristic impedance is required for the open-circuited stubs of the ABSFs to enhance the selectivity. This cannot be realized in traditional microstrip designs, but it can be obtained easily by offsetting the DSPSL. Meanwhile, the BPF with T-shaped structure consists of a half-wavelength (λ/2) DSPSL with a centrally-loaded λ/2 stub, which answers for generating two transmission zeros (TZs) to achieve better out-of-band suppression. For demonstration, a prototype is designed, fabricated and measured, and the simulated and measured results with good agreement are presented.

In this letter, a compact bandpass filtering power divider with tunable bandwidth based on spoof surface plasmon polaritons (SSPPs) and substrate integrated waveguide (SIW) is proposed. The hybrid-SIW-SSPP structure shows good potential to expand the scope of bandwidth control of the device. The bandwidth can be designed in a wide range by simply optimizing its dimensions or loading interdigital structures (ISs). Defected ground structure (DGS) is also introduced on the bottom layer to further improve the out-of-band suppression. And good isolation can be obtained via additional resistors welded across the SSPP slot. A prototype loaded with dumbbell-shape DGS and two resistors is fabricated with an overall size of 45 mm x 18 mm x 0.5 mm. Both $S_{21}$ and $S_{31}$ are around -3.8 dB within the whole X-band. The simulated and measured results agree with each other well.

In this article, a novel wideband bandpass power divider (PD) with out-of-band multi-transmission zeros (TZs) is presented. It consists of 2M shunted short-circuited stubs (SCSs), (M + N) cascaded coupled line sections, and ( $M + N - K_{N)$ isolation resistors. There are two types of topologies, and the number of TZs is solely determined by N. Through even- and odd-mode analyses, general simultaneous equations for characteristic impedances, coupling strengths, and isolation resistors are derived with the proposed algorithm. By suitably selecting all the design parameters, all the S-parameters (S₁₁, S₂₁ = S₃₁, S₂₂ = S₃₃, and S₃₂) of the proposed topology could provide an equal-ripple response with controllable ripple level in the passband. For a given fractional bandwidth (FBW), TZs and out-of-band rejection level can be designed independently. For further optimization, several isolation resistors can be omitted with the unchanged performances. For verification, two experimental circuits are fabricated and measured. Good agreement between the measured and simulated results is attained so as to successfully validate the correctness of the proposed design approach.

In this brief, we analyzed the output ripple in a capacitively-coupled chopper-based instrumentation amplifier (CCIA). Our analysis found that the shape and amplitude of the output ripple of the CCIA are determined by five design parameters, namely amplifier offset, transconductance, chopping frequency, Miller compensation capacitance, and the nulling resistor. With different design specifications, the CCIA ripple appears in four different shapes, including triangular ripple, RC-settling ripple, square ripple, and step-change ripple. These findings are verified by the silicon results. As the cause of each ripple shape varies, this analysis serves as a guideline for designing practical chopper-based amplifiers and their corresponding ripple reduction techniques.

The indium phosphide (InP) 130 nm double-heterojunction bipolar transistor (DHBT) offers milliwatts of output power and high signal amplification in the lower end of the terahertz frequency band when the transistor is used in a common-base configuration. Instrumentation can directly benefit from this technology by enabling the development of novel broadband sources or synthesizers that rely on our ability to amplify the signal over enormous bandwidths. However, the design of high gain and stable amplifiers presents many obstacles and limitations as we increase the bandwidth and the carrier frequency. Here we show that adding a series resistor at the collector terminal of the common-base transistor prevents instabilities in the terahertz monolithic integrated circuit (TMIC) amplifier and increases its fractional bandwidth. Adopting this technique, we report a state-of-the-art broadband common-base amplifier that exhibits a minimum small-signal gain of 18.9 dB from 325 GHz to 477 GHz. This amplifier presents the highest fractional bandwidth and gain above 300 GHz. Our work demonstrates the feasibility of high-performance amplifiers that address the need of future terahertz electronic systems.

A technique to reduce the area of a low-noise sub-sampling PLL (SSPLL) is proposed. The resistor in the loop filter is eliminated. The transconductor driven by the phase detector is switched such that its output consists of a positive and negative pulse with the former wider than the latter. A low frequency zero can thus be realized with a substantially smaller capacitor. Transconductor noise is suppressed to acceptable levels by the high phase-detector gain. In applications that require low out-of-band phase noise, the capacitance can be reduced by 25x or more with typical PLL parameters. A prototype SSPLL from 24.4 GHz-29.2 GHz with a 50 MHz reference clock and bandwidth of 1MHz in 65nm LP CMOS process uses a loop filter capacitance of only 5pF. The conventional topology would require 38pF for the same integrated jitter. The in-band phase noise at 1MHz offset ranges from -90 to -95dBc/Hz, and the out-of-band phase noise at 10 MHz offset ranges from -117 to -121dBc/Hz. The jitter integrated from 10kHz to 50MHz is 330-390fs. It consumes 18.2mW, exhibiting a minimum FoM of 235dB over the frequency range. The SSPLL occupies an area of only 0.14mm².

A differential four-way power divider for 24 to 30 GHz and a frequency reconfigurable differential four-way power divider for 24 to 30 GHz and 37 to 43.5 GHz are presented. The differential structure provides sound virtual grounds in a multiple-channel chip. Both circuits have a four-way Wilkinson power divider (WPD) configuration based on lumped elements that provide small chip sizes. The first one has a small core chip area of 0.09 mm², a small insertion loss of 0.93 to 1.94 dB, and the port-to-port isolation of 19.1 to 25.6 dB from 24 to 30 GHz. It has a small amplitude and phase differences at four outputs. The second one allows frequency-reconfigurable operation by switching inductances and capacitances to cover widely separated frequency bands (5G NR n257-n261 bands). In addition, switched capacitors (SCs) are inserted to resonate out the parasitic series inductances in isolation resistors at both bands of 24-30 GHz and 37-43.5 GHz. It has a core chip area of 0.168 mm², insertion losses of 1.65-1.89 dB at 24 to 30 GHz and 2.04-2.70 dB at 37 to 43.5 GHz, respectively. The port-to-port isolations are 23.4-37.6 dB at 24 to 30 GHz and 22.6-28.4 dB at 37 to 43.5 GHz.

The multilevel connected dc–dc converters system is considered a practical technology to increase the capacity and reduce voltage and current stresses on the power devices. In practice, mismatched parameters are inevitable, which increase the challenge of output voltage regulation and current sharing control. In order to conquer these difficulties, this article investigates the current sharing based on incremental passivity control for multilevel connected dc–dc converters. Combined with passivity-based control, a finite-time estimator is given to improve the robustness against the load variations. The proposed method results in a linear control law despite the bilinear nature of this system. Moreover, analysis exhibits that stability and current sharing are independent of inductor parameters. Furthermore, stability of the closed-loop system has been proved that the proposed approach is valid both for a linear and nonlinear load. After introducing the proposed control scheme, simulation and experiments are offered to validate its fast transit response and antidisturbance performance.

The study presents the pyroelectric performance improvement by employing exhaust emissions from automobiles. Electric outputs through the material BaSn0.05Ti0.95O3 are recorded after subjecting the surface of the sample for heating under infrared (IR) lamp and flowing water. The thickness of the automobile exhaust ink was nearly 35 µm on the sample surface. Observations show significant improvements with open circuit voltage increase to five times, electric current enhances upto six times across the resistor of 10 Ω and nearly 17 times increment in energy harvested. Peak values of open circuit voltage obtained were 0.3 and 1.2 V for uncoated as well as coated samples respectively. The electric current for the heating & cooling cycle represents peak value of 1.47 µA when compared with uncoated sample with a value of 0.24 µA. Moreover, energy stored across capacitor of10 µF founds an increment from 1.4 µJ for uncoated sample to 23.10 µJ for coated sample. The study proposes effective utilization of harmful automobile exhaust and harvesting of energy for low power electronics. Therefore this study systematically investigates the pyroelectric energy potential of BaSn0.05Ti0.95O3 ceramics by using automobile emission and compares it with similar class of materials.

This paper presents a new approach to design filtering power dividers (FPD) with regular triangle patch resonator (RTPR). According to the electric-field (E-field) distributions of the resonator modes, the TM₁₀ and TM₁₁ modes have been selected to realize two- and three-way power dividers respectively, showcasing the flexible characteristic of the RTPR. Afterwards, an in-phase multiway excitation scheme for the RTPR is developed to well excite the designated modes and suppress multiple spurious modes, simultaneously. Subsequently, to further reject the harmonics so as to extend the upper stopband greatly, shorting posts are deployed at the locations with null electric field distribution for the specified operation mode. Ultimately, to validate the design concept, a two-way and a three-way second-order FPD employed at TM₁₀ (f₁₀= 1.27GHz) with fractional bandwidth (FBW) of 7% and at TM₁₁ (f₁₁= 2.2GHz) with FBW of 4.5% are designed and measured. The measured results of the two fabricated circuits well agree with the simulated ones. Results indicate that both of the two FPDs exhibit properties of good port-to-port isolation, high selectivity with transmission zeros near both sides of the passband, as well as wide stopband extended to 3.35 and 2.9 times of fundamental operation frequencies, respectively.

The avalanche transistor-based Marx circuit has great advantages in generating high-voltage nanosecond pulses. The introduction of auxiliary triggering topology (ATT) can reduce the damage probability of transistors in M × N -stage Marx bank circuits (MBCs). However, as the number of modified stages increases, the output voltage drops significantly, which makes it not achievable to adopt ATT at each stage. The transistors in nonmodified stages still have a certain failure rate when operating at a high repetition rate. Moreover, the previous ATT is only applicable in the negative polarity MBC. In this article, an improved ATT is proposed to solve the above problems. First, its operating principle is analyzed, and the feasibility of its application in both negative and positive MBCs is verified by simulations. Then, the effects of the improved ATT on M × N -stage MBCs are experimentally studied, and the results show that the improved ATT can be used in all stages of MBC without reducing the output voltage. It can also reduce the minimum operating voltage of transistors and widen the regulating range of output voltage. In addition, it can improve the synchronous conduction of parallel-connected transistors. Finally, two nanosecond pulse generators with positive and negative polarity, respectively, are developed and used to drive the atmospheric pressure plasma jet. The amplitude of output voltage can be adjusted in the range of 5–10 kV, measuring at the open end of a coaxial cable with 75 Ω impedance, and the maximum repetition rate is up to 7 kHz.

In this brief, novel single-layer dual-band bandpass filters (BPFs) with input-/two-port all-frequency absorptive performance are presented. The design consists of a simple coupled-line (CL) based dual-band BPF section and auxiliary dual-band bandstop filter (BSF) sections with resistively terminated absorptive stubs. The dual-band BPF can transmit spectral energy in two operational passbands with good in-band filtering response, while the out-of-band RF-signal energy can be well absorbed by auxiliary BSF sections shunted at input/output ports, which indicates all-frequency absorption from DC. Besides, the impedance of the absorptive stub and the value of the grounded resistor can be independently adjusted to enhance the absorption performance. Furthermore, the operational foundations and explicit design equations are discussed and derived. Good agreements between the simulated and measured results verify the design theory.

Silicon carbide (SiC) MOSFET exhibits low channel resistance, low junction capacitances, and wider temperature range compared with silicon counterpart. However, the high dv=dt in a bridge-leg connected SiC MOSFETs induce the detrimental coupling noise, increasing device stress and EMI and restricting the converter operation at a high switching frequency. This paper presents two single-supply based variable gate voltage driving (SSVGVD) circuits for SiC MOSFETs to exploit the switching-speed capacity by mitigating the coupling noise during switching transients. Both driver circuits employ a simple auxiliary circuits comprising a transistor, zener diode, and resistor to control the gate voltage of power devices in a bridge-leg configuration. The proposed driver circuit can be easily realized with a driver IC using only positive driver supply, offering a compact, low-cost, and reliable solution. Experimental tests with SiC MOSFETs demonstrate the effectiveness of the SSVGVD gate driver.

In this paper, an integrated low-profile low radar cross section (RCS) circularly polarized (CP) antenna array based on multi-functional modes generation method is proposed, which can realize good in-band radiation performance and wide out-of-band RCS reduction characteristics on the same layer without additional subassembly except resistors. By embedding a resistor in the center of a metallic strip, the half and one and a half wavelength resonant modes are changed into the absorption modes; while the one wavelength resonant mode is excited as the radiation mode when offset feeding at an appropriate location. Furthermore, the CP radiation performance is achieved with four bent and center-rotating-symmetric metallic strip and the sequentially rotated feeding network. The simulation results show that the designed integrated antenna array generates the same left-hand CP radiation performance as the array without embedding resistors, and the monostatic RCS of the array is significantly reduced in the lower and upper bands, with an average reduction value of 10 dB. Prototypes of the designed antenna array with 4×4 elements are fabricated and measured to validate the simulation results.

Conventional di/dt and dv / dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.

Though Current Mode Logic has excellent features like higher switching speed and reduced crosstalk due to small output swing, there exists numerous flaws such as static power dissipation, non-suitable for power-down modes and comparably higher design complexity of load resistors. To address the aforementioned worries, this article incorporates a dynamic current mode design approach having active load and controlled current source to configure an improved (2/3) dual modulus prescaler. Simulation results of the proposed circuit using Cadence Virtuoso platform for 90 nm CMOS at 1.2 V supply depict a power consumption of 2.517 mW when driven by a high frequency of 2 GHz. The phase noise and output noise are found to be − 147.001 dBc/Hz and − 181.7 dB at 1 MHz offset while it reads a self-oscillation frequency of 5 GHz. The variation tolerance of the design is proved via 5% skew-based simulation at all corners; whereas the correct functionality at 28 nm UMC justifies its scalability.

Fractional and reference spurs appear at the output of a fractional PLL along with the carrier. In the proposed architecture, two PLLs are conjunctly implemented for spur reduction—one fractional and other integer—with their control voltages summed together for dual control. A very low value (1/100) of the fractional frequency division ratio is considered. A fractional sampler is introduced that places bandstop notches at very low frequencies and hence, loop bandwidth of the fractional PLL has to be lower than the first spur frequency. To alleviate the issue of high area requirement by the second-order loop filter capacitors in the fractional PLL, the charge pump is divided into two parts with high and low values of pump currents. The charge pump with the low pump current drives the loop filter network segment with the resistor; thus, the area of the capacitor in this network can be reduced. By simulation in 180 nm CMOS technology, it is observed that the largest fractional spurs are reduced from $$+19.2$$ to $$-66.2$$ dBc, and the reference spurs from $$-28.5$$ to $$-67.8$$ dBc. Monte Carlo simulations show best and worst case spurs at $$-73$$ and $$-69$$ dBc, respectively. The architecture shows the phase noise characteristics of the integer PLL when identical oscillators are used in both the loops.

This paper presents a new mutually coupled circuit (MCC) based on voltage differencing current conveyor (VDCC). The proposed MCC has been designed using the Gorski-Popiel technique. The proposed circuit consists of two VDCCs as active elements, three resistors, and two grounded capacitors as passive elements. The primary and secondary self-inductances and the mutual inductance can be controlled independently and can be adjusted electronically by the bias current of the VDCCs. There is only one matching condition for satisfying symmetrical coupling. Time and frequency-domain analyses have been performed with the LTspice program to verify the theoretical analyses. A double-tuned band-pass filter application is given to show the functionality of the proposed MCC.

Fast recovery, high sensitivity, high selectivity, and room temperature (RT) sensing characteristics of NO gas sensors are essential for environmental monitoring, artificial intelligence, and inflammatory diagnosis of asthma patients. However, the conventional semiconductor-type gas sensors have poor sensing characteristics that need to be solved, such as slow recovery speeds (>360 s), low sensitivity (3.8), and high operating temperatures (>300 °C). We propose here a memristor-based NO gas sensor as a gasistor (gas sensor + memory resistor) with SnO2, Ta2O5, and HfO2 films, which successfully demonstrated the feasibility of fast reaction/recovery (

A differential quench and reset (QR) configuration for single-photon avalanche diodes (SPADs) is proposed and investigated in this work. Compared to the traditional single QR configuration in which only one QR circuit is connected to either the cathode or anode of the SPAD, the differential QR configuration consists of two QR circuits to quench and reset through both the cathode and anode terminals. Using a SPAD fabricated in a 65 nm CMOS process, the measurement results of the traditional single passive quench and reset (SPQR) circuit and the proposed differential passive quench and reset (DPQR) circuit shows that the SPAD with the DPQR circuit presented a reduced reset time, an improved timing performance, an increased count rate and a decreased afterpulsing. In addition, the differential output pair from the DPQR circuit has the potential to increase the signal-to-noise ratio of the detection system due to its ability to reject common-mode noise and interference.

The charge-generating sensors are widely used in many applications in consumer, automotive and medical electronics. They generate a charge proportional to the applied input quantity: pressure, temperature, acceleration, strain, light, etc. Usually, charge amplifiers are used to register such signals. The charge amplifier is an integrator that integrates the input current over time. In continuous-time signal processing, a parallel resistor is used to dissipate the energy stored on the integration capacitor, and such self-zeroed integrator circuits are known as lossy integrators. To achieve low-frequency operation, when a capacitor is in the picofarad range, a very high-ohmic resistor, in the range of gigaohms, must be used. Such a high-ohmic resistor increases the output offset voltage to an unacceptable level. To overcome the output offset problems, a composite charge amplifier has been recently introduced. This paper presents an innovative lossy integrator readout circuit which contains only one opamp in the feedback. The circuit can be easily adapted to the needed gain and cut-off frequency. Its operation is validated by experimental results. The sufficiently low high-pass cut-off frequency allows the circuit to be used for biosignal amplification. Heart and respiration rates can be easily recorded with piezoelectric sensors attached to the wrist or lung wall. The presented circuit can benefit many applications where charge-to-voltage conversion is needed.

In this brief, a novel compact single circular patch dual-band (DB) filtering power divider (FPD) is proposed for the first time. In this design, the modified TM01 resonance mode (i.e., TM01’ mode) is developed by introducing a metallic via in the center of the patch, while four additional same metallic vias are placed in the patch to control the generated TM01’ mode and the TM21 mode. In addition, vertical slot perturbations are investigated to control the TM11 mode and the TM31 mode, while the transversal slot perturbation loaded with three resistors is exploited to achieve good isolation. In this context, with elaborate exploitation of these resonant modes, two passbands can be attained, correspondingly. The lower passband is formed by TM01’ and TM11 modes, while the upper passband is constituted by TM21 and TM31 modes, respectively. For validation, a prototype is implemented. Results exhibit relative compact size, wider bandwidths, nice return losses, as well as decent isolation.