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In a previous study [1], the authors have investigated stacked silicon microcoolers and quantified their thermal performance envelope in a separable format where the microcooler is attached to an electronic package lid with an intervening TIM2. In this study, we expand the previous study by integrating the stacked microcoolers into an electronic package, i.e., by removing the lid and the TIM2.A summary of thermal resistance and pressure drop experimental data spanning a wide range of fluid flow rates is presented. Additionally, numerical modeling using FEA/CFD models is conducted and the results compared to the experimental data.Results reveal that the thermal performance of the integrated microcoolers is ~ 30% superior that of the separated microcoolers. The numerical model results accurately predict the experimental data to within 20%. Directions for future thermal performance improvements using multiple inlet/outlet ports and varying the number of cooler stacks are identified using the numerical models.

We introduce a new packaging technology termed as Direct Bonded Heterogeneous Integration (DBHi) where a Si-bridge is directly bonded to and in between processor chips using Cu pillars, allowing high-bandwidth low-latency low-power communication between the chips. The DBHi package structure, test vehicle design, and bond and assembly details are first described. The test vehicle package consists of chips with standard interconnect pitch where they join to a laminate chip-carrier and fine-pitch pads in the region where the chips joins to a bridge. The bridge has Cu pillars correspondingly mating to the pads on the chips. The bond and assembly sequence starts with first joining the silicon chips and bridge using a thermocompression bonding process followed by a mass reflow join of the chips to the laminate. The assembly is then underfilled and capped using specialized techniques. Mechanical modeling was extensively used to simulate the DBHi structure and assembly process to allow material selection and reliability prediction. The mechanical models were calibrated using warpage measurements. The stress/strain reliability metrics of the DBHi package are compared to a non-bridge package of the same dimensions. Results show that the main focus should be directed towards ensuring a robust assembly process as the standard reliability stress/strain metrics of the DBHi package are very similar to a non-bridge package. Thermal measurements using chip heaters and temperature sensors were conducted to calibrate a numerical thermal model of the DBHi package. The thermal model was exercised to show the relation between the allowable chip and bridge power densities for the particular package size and cooling conditions. DBHi test packages were created using the best-known assembly process and then measured for continuity performance. A variety of inter- and intra-bridge daisy chain nets were incorporated into the test vehicle for continuity measurements. Post-assembly continuity measurements demonstrated a robust assembly process for multiple rounds of assembly. Reliability performance was demonstrated using standard JEDEC tests of thermal cycling, aging, and temperature/humidity.

With aggressive scaling of single-expose EUV lithography to the sub-7 nm node, stochastic variations play a prominent role in defining the lithographic process window. Fluctuations in photon shot noise, absorption and subsequent chemical reactions can lead to stochastic failure, directly impacting electrical yield. Fundamental characterization of the mode and magnitude of these variations is required to define the threshold for failure. In this work, a complementary series of techniques is enlisted to probe the nature and modulation of stochastic variation in single exposure EUV patterning. Unbiased line edge roughness (LER), local critical dimension uniformity (LCDU) and defect inspection techniques are employed to monitor the frequency of stochastic variations leading to failures in line/space and via patterning. Using this methodology, we explore the modulation of stochastic variations by different photoresists and illuminations, with emphasis on material and process down-selection for improved yield at the sub-7 nm node.

The ability to rapidly detect both printable EUV mask adder defects as well as mask absorber defects across the entire mask image field is a key enabler for EUV lithography. Current optical wafer-based inspection techniques are only capable of detecting repeater defects on a die-to-die basis for chiplets within the image field. Larger server-type chips that encompass the entire mask image field cannot rely on such a scheme, since the presence of the defect in every die prevents their detection. In this paper, a prototype optical wafer defect inspection methodology designed to detect repeater defects over the entire image field, termed die-to-baseline reference die (D2BRD), is investigated. The sensitivity of this inspection technique is demonstrated and compared to eBeam inspection over a range of defect sizes for both opaque and clear type mask absorber programmed defects. Moreover, the D2BRD methodology is used to monitor printing defect adders present in a lithographic defect test mask, as well as 7-nm BEOL layers. Using defect repeater analysis, SEM review and patch image classification of full chip wafer inspections over several mask cycles, the D2BRD scheme is shown to allow the unambiguous identification of mask adder defects, while suppressing random process defects. This methodology has the potential to define the risk assessment of mask adder defects in the absence of an EUV pellicle, and can play an integral part of the wafer print protection strategy.

The demand for integrated silicon packages is driving packaging advancements for increasingly fine circuit pattern designs. Due to the thinner copper and finer features required for advanced packaging, copper line defects can significantly impact yield and reliability. Industry Automated Optical Inspection (AOI) capabilities for packaging features are reaching detection limits.Phase One of the iNEMI metrology project surveyed industry capability and completed a gap analysis. This work established the basis for the current activities in Phase Two. A fine featured test vehicle was designed and fabricated using thin film processing technologies on both glass and silicon substrates to evaluate and assess the limits of today’s AOI metrology equipment. The test vehicle also provided a platform to develop future metrology capability required to close the technical gaps with respect to product requirements and process and material capabilities.The test vehicle samples were provided to various industrial AOI equipment suppliers to evaluate their capabilities in evaluating fine lines and spaces. The integrity of the fine wiring lines and spaces was compared between a control pattern and known defects utilizing wiring patterns from 10 μm lines and spaces to 1 μm lines and spaces. Various types of features including different orientations were evaluated: a) Line width violations; b) Spacing violations; c) Excess copper or missing copper; d) Shorts; e) Opens. This paper will review the details of the Phase Two test vehicle and the results from the AOI evaluations, and present a roadmap for the next phase of the study with test vehicles on organic substrates.

Defects are ubiquitous in the semiconductor industry and detection, classification at various levels is a challenge and requires rigorous sampling. Every technology offers a new challenge in this area and requires numerous hours of setup, debug time for semiconductor integrated chip manufacturers. Intentional defects on patterns at various sizes in comparison to the critical dimension of a particular technology are used to preview their modulation and assess inspection tool performances. Figure 1 shows a few types of intentional defects as designed and their respective manifestation on a photomask. The chart also shows detection and printability limit and it varies by each defect type.1, 2 In recent years deep learning has made tremendous progress and has substantially improved the state-of-art in many applications that include object detection, speech recognition, and image classification3 The application and design of these deep learning tools in semiconductor defect recognition can be very useful, as it has the potential to reduce the setup time, cost and improving the overall (defect) detection and classification accuracy. In this work we demonstrate the application of convolution neural networks on e-beam images of intentional defects on various types of patterns. We assess various filters and their outputs at each layer of a custom convolutional neural network (Figure 2) to ultimately improve the architecture and its accuracy. We also demonstrate the relative effectiveness of transfer learning in this application with limited availability of labelled data. Using the architecture illustrated in Figure 2 we are able to achieve a classification accuracy of 95%.

Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern the metal layer at aggressive pitch using a single exposure. We report here a mask process compatible with a 30nm pitch patterning module for the demanding sub 7nm node, single expose interconnect application. We found a large increase in mask to wafer image transfer sensitivity during the 32nm to 30nm pitch shrink development that led to increases in stochastic and systematic wafer defect generation mechanisms. In this work, we describe our steps to characterize, model and improve the mask related factors that reduce this sensitivity as part of a successful 30nm pitch patterning module demonstration. High resolution wide area electron beam mask inspection alongside a suite of advanced mask characterization and optimization(AMCO)tools were key elements in understanding mask process gaps and improvement opportunities. Critical mask parameters optimized in closed loop with wafer response included two and three dimensional pattern fidelity, line roughness and spatial variability. Mask critical dimension targeting was found to be a critical factor for delivering the yielding 30nm pitch wafer process and this targeting was tuned dynamically through mask and wafer co-optimization. Finally, the role of wafer anchored process simulation proved an invaluable guide for linking various mask error source mechanisms to the wafer response.

Background: With aggressive scaling of single-expose (SE) extreme ultraviolet (EUV) lithography to the sub-7-nm node, stochastic variations play a prominent role in defining the lithographic process window (PW). Fluctuations in photon shot noise, absorption, and subsequent chemical reactions can lead to stochastic failure, directly impacting electrical yield. Aim: Fundamental characterization of the mode and magnitude of these variations is required to define the threshold for failure. Approach: A complementary series of techniques is enlisted to probe the nature and modulation of stochastic variation in SE EUV patterning. Unbiased line edge roughness (LER), local critical dimension uniformity (LCDU), and defect inspection techniques are employed to monitor the frequency of stochastic variations leading to failures in line/space (L/S) and via patterning. Results: When characterizing different resists and illumination conditions, there is no change in unbiased LER or via LCDU with increasing critical dimension (CD). Stochastic defect density is correlated with CD for both L/S and via arrays, and there is a strong correlation with L/S electrical yield data. Conclusions: Traditional 3σ LER and via LCDU measurements are not sensitive enough to define and improve PW. For PW centering and yield improvement, stochastic defect inspection is a necessity.

Defects in semiconductor processes can limit yield, increase overall production cost, and also lead to time-dependent critical component failures. Current state-of-the-art optical and electron beam (EB) inspection systems rely on rule-based techniques for defect detection and classification, which are usually rigid in their comparative processes. This rigidity limits overall capability and increases relative engineering time to classify nuisance defects. This is further challenged due to shrinkage of pattern dimensions for advanced nodes. We propose a deep learning-based workflow that circumvents these challenges and enables accurate defect detection, classification, and localization in a unified framework. In particular, we train convolutional neural network-based models using high-resolution EB images of wafers patterned with various types of intentional defects and achieve robust defect detection and classification performance. Furthermore, we generate class activation maps to demonstrate defect localization capability of the model “without” explicitly training it with defect location information. To understand the underlying decision-making process of these deep models, we analyze the learned filters in pixel space and Fourier space and interpret the various operations at different layers. We achieve high sensitivity (97%) and specificity (100%) along with rapid and accurate defect localization. We also test performance of the proposed workflow on images from two distinct patterns and find that in order to retain high accuracy a modest level of retraining is necessary.

Metrology of nanoscale patterns poses multiple challenges that range from measurement noise, metrology errors, probe size etc. Optical Metrology has gained a lot of significance in the semiconductor industry due to its fast turn around and reliable accuracy, particularly to monitor in-line process variations. Apart from monitoring critical dimension, thickness of films, there are multiple parameters that can be extracted from Optical Metrology models3. Sidewall angles, material compositions etc., can also be modeled to acceptable accuracy. Line edge and Line Width roughness are much sought of metrology following critical dimension and its uniformity, although there has not been much development in them with optical metrology. Scanning Electron Microscopy is still used as a standard metrology technique for assessment of Line Edge and Line Width roughness. In this work we present an assessment of Optical Metrology and its ability to model roughness from a set of structures with intentional jogs to simulate both Line edge and Line width roughness at multiple amplitudes and frequencies. We also present multiple models to represent roughness and extract relevant parameters from Optical metrology. Another critical aspect of optical metrology setup is correlation of measurement to a complementary technique to calibrate models. In this work, we also present comparison of roughness parameters extracted and measured with variation of image processing conditions on a commercially available CD-SEM tool.

Pattern transfer fidelity is always a major challenge for any lithography process and needs continuous improvement. Lithographic processes in semiconductor industry are primarily driven by optical imaging on photosensitive polymeric material (resists). Quality of pattern transfer can be assessed by quantifying multiple parameters such as, feature size uniformity (CD), placement, roughness, sidewall angles etc. Roughness in features primarily corresponds to variation of line edge or line width and has gained considerable significance, particularly due to shrinking feature sizes and variations of features in the same order. This has caused downstream processes (Etch (RIE), Chemical Mechanical Polish (CMP) etc.) to reconsider respective tolerance levels. A very important aspect of this work is relevance of roughness metrology from pattern formation at resist to subsequent processes, particularly electrical validity. A major drawback of current LER/LWR metric (sigma) is its lack of relevance across multiple downstream processes which effects material selection at various unit processes. In this work we present a comprehensive assessment of Line Edge and Line Width Roughness at multiple lithographic transfer processes. To simulate effect of roughness a pattern was designed with periodic jogs on the edges of lines with varying amplitudes and frequencies. There are numerous methodologies proposed to analyze roughness and in this work we apply them to programmed roughness structures to assess each technique’s sensitivity. This work also aims to identify a relevant methodology to quantify roughness with relevance across downstream processes.

We report on the printability, mitigation and actinic mask level review of programmed substrate blank pit and bump defects in a EUV lithography test mask. We show the wafer printing behavior of these defects exposed with an NXE:3300 EUV lithography scanner and the corresponding mask level actinic review using the AIMSTM tool. We will show which categories of these blank substrate defects print on wafer and how they can be mitigated by hiding these defects under absorber lines. Furthermore we show that actinic AIMSTM mask review images of these defects, in combination with a simple thresholded resist transfer model, can accurately predict their wafer printing profiles. We also compare mask level actinic AIMSTM to top down mask SEM review in their ability to detect these defects.

The ability to rapidly detect both printable EUV mask adder defects as well as mask absorber defects across the entire mask image field is a key enabler for EUV lithography. Current optical wafer-based inspection techniques are only capable of detecting repeater defects on a Die-to-Die basis for chiplets within the image field. Larger server-type chips that encompass the entire mask image field cannot rely on such a scheme, since the presence of the defect in every die prevents their detection. In this study, a prototype optical wafer defect inspection methodology designed to detect repeater defects over the entire image field, termed Die-to-Baseline Reference Die (D2BRD), is investigated. The sensitivity of this inspection technique is demonstrated and compared to eBeam inspection over a range of defect sizes for both opaque and clear type mask absorber programmed defects. Moreover, the D2BRD methodology is used to monitor printing defect adders present in a lithographic defect test mask, as well as 7 nm metal mask layer. Using defect repeater analysis, SEM review and patch image classification of full chip wafer inspections over several mask cycles, the D2BRD scheme is shown to allow the unambiguous identification of both mask adder and absorber "native" mask defects, while suppressing random process defects. Thus, this methodology has the potential to help define the risk assessment of mask adder defects in the absence of an EUV pellicle, and can play an integral part of the wafer print protection strategy.

Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM).1, 2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable.3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing. In this work, we assess multiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.

As Extreme Ultraviolet (EUV) lithography has matured, numerous imposing technical challenges have been the focus of intense scrutiny, including the EUV radiation source, reflective optics, and fundamental mask fabrication. There has been a lurking question on the state of mask defectivity that has been almost unanswerable until the recent relative maturation of the rest of the infrastructure. Without readily available actinic blank or patterned inspection systems, EUV blank and mask manufacturers must continue to rely on relatively low resolution optical systems for blank characterization. Despite best efforts, detectable defects still exist; these can be classified into three types: small defects that can be avoided through pattern-shift, medium defects that can be repaired, and large defects which must be suppressed during manufacture. To successfully intercept high-volume-manufacturing (HVM) for the 7nm node, aggressive, continued industry focus is required to ensure that these three defect types are addressed. Without actinic mask inspection, an unknown element with EUV lithography continues to be the presence of nondetected printable defects – defects that print on wafer despite being undetected during mask or blank fabrication. Another risk is that until recently, focus has been on developing techniques to identify catastrophic defects, while past manufacturing experience tells us that much more subtle defects (

Combining vapour sensors into arrays is an accepted compromise to mitigate poor selectivity of conventional sensors. Here we show individual nanofabricated sensors that not only selectively detect separate vapours in pristine conditions but also quantify these vapours in mixtures, and when blended with a variable moisture background. Our sensor design is inspired by the iridescent nanostructure and gradient surface chemistry of Morpho butterflies and involves physical and chemical design criteria. The physical design involves optical interference and diffraction on the fabricated periodic nanostructures and uses optical loss in the nanostructure to enhance the spectral diversity of reflectance. The chemical design uses spatially controlled nanostructure functionalization. Thus, while quantitation of analytes in the presence of variable backgrounds is challenging for most sensor arrays, we achieve this goal using individual multivariable sensors. These colorimetric sensors can be tuned for numerous vapour sensing scenarios in confined areas or as individual nodes for distributed monitoring., Individual vapour sensors often suffer from poor selectivity, which hinders their broad applicability. Here, Potyrailo et al. fabricate individual sensors inspired by the Morpho butterfly capable of selectively detecting vapours in mixtures and with a variable moisture background.

NAP-PD (Native Acting Phase – Programmed Defects), otherwise known as buried program defects, with attributes very similar to native defects, are successfully fabricated using a high accuracy overlay technique. The defect detectability and visibility are analyzed with conventional phase contrast blank inspection @193 nm wavelength, pattern inspection @193 nm wavelength and SEM. The mask is also printed on wafer and printability is discussed. Finally, the inspection sensitivity and wafer printability are compared, leading to the observation that the current blank and pattern inspection sensitivity is not enough to detect all of the printable defects.

The backside of photomasks have been largely ignored during the last several decades of development, with the exception of avoiding gross damage or defects, as almost all problems are far enough out of the focal plane to have minimal effect on imaging. Since EUV masks are reflective, and the column is held in a vacuum, scanners have been designed to utilize electrostatic chucking. With the chucking system for EUV, the requirements for the backside of the mask must be redefined to integrate concerns in substrate design, mask manufacturing, and usage. The two key concerns with respect to an electrostatic chuck are defects and durability. Backside defects can affect imaging, while potentially damaging or contaminating the tool, the mask, or even subsequently used masks. Compromised durability, from either usage or cleaning, can affect the ability of the chuck to hold the mask in place. In this study, these concerns are evaluated in three stages: minimizing defects created during mask fabrication, actions taken upon discovery of defects, and durability of the backside film with continued cleans and chucking. Data incorporated in this study includes: sheet resistance, film thickness, and optical inspection images. Incorporating the data from the three stages of fabrication, disposition, and lifetime will help us define how to structure backside EUV mask handling during mask manufacture and indicate what further solutions are needed as EUV technology transitions into manufacturing.

The detection of EUV mask adder defects has been investigated with an optical wafer defect inspection system employing a methodology termed Die-to-“golden” Virtual Reference Die (D2VRD). Both opaque and clear type mask absorber programmed defects were inspected and characterized over a range of defect sizes, down to (4x mask) 40 nm. The D2VRD inspection system was capable of identifying the corresponding wafer print defects down to the limit of the defect printability threshold at approximately 30 nm (1x wafer). The efficacy of the D2VRD scheme on full chip wafer inspection to suppress random process defects and identify real mask defects is demonstrated. Using defect repeater analysis and patch image classification of both the reference die and the scanned die enables the unambiguous identification of mask adder defects.

The black border is a frame created by removing all the multilayers on the EUV mask in the region around the chip. It is created to prevent exposure of adjacent fields when printing an EUV mask on a wafer. Papers have documented its effectiveness. As the technology transitions into manufacturing, the black border must be optimized from the initial mask making process through its life. In this work, the black border is evaluated in three stages: the black border during fabrication, the final sidewall profile, and extended lifetime studies. This work evaluates the black border through simulations and physical experiments. The simulations address concerns for defects and sidewall profiles. The physical experiments test the current black border process. Three masks are used: one mask to test how black border affects the image placement of features on mask and two masks to test how the multilayers change through extended cleans. Data incorporated in this study includes: registration, reflectivity, multilayer structure images and simulated wafer effects. By evaluating the black border from both a mask making perspective and a lifetime perspective, we are able to characterize how the structure evolves. The mask data and simulations together predict the performance of the black border and its ability to maintain critical dimensions on wafer. In this paper we explore what mask changes occur and how they will affect mask use.

EUV Lithography is aimed to be inserted into mainstream production for sub-20nm pattern fabrication. Unlike conventional optical lithography, frequent defectivity monitors (adders, repeaters etc.) are required in EUV lithography. Due to sub-20nm pattern and defect dimensions e-beam inspection of critical pattern areas is essential for yield monitor. In previous work we showed sub-10nm defect detection sensitivity 1 on patterned resist wafers. In this work we report 8-10× improvement in scan rates of etched patterns compared to resist patterns without loss in defect detection sensitivity. We observed good etch transfer of sub-10nm resist features. A combination of smart scan strategies with improved etched pattern scan rates can further improve throughput of e-beam inspection. An EUV programmed defect mask with Line/Space, Contact patterns was used to evaluate printability of defects and defect detection (Die-Die and Die-Database) capability of the e-beam inspection tool. Defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability and were compared to previously obtained results on resist patterns.

Understanding the effect of defect sizes and their impact on EUV lithography is an ongoing challenge due to continued scaling of devices [1], [2]. The objective of this study is to assess printability of defects on post develop photoresist wafers and their detection capability with an electron beam inspection tool on EUV resist for various patterns (Line/Space, Contacts). Total capture of defects is an important factor for assessing printability on photoresist patterned wafers and monitoring process window. In this work, we present a comparison of Die to Die (reference to programmed defect to sites on wafer) and Die to Database (program defect sites on wafer to design). A programmed defect test mask is used to understand the impact of printing mask defects at multiple lithography levels (ex. gate, metal etc.) at 20 and 14nm technology ground rules. It is designed with both additive and subtractive features at defect sizes ranging from 30nm to 1nm. The defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability.

Successful implementation of multilayer lithography to fabricate three-dimensional structures involves depositing multiple layers of radiation sensitive materials with necessary dose and tone contrast. Resists are radiation sensitive materials (usually polymers dissolved in solvents) used in micro- and nanolithography. Currently, they are deposited on wafers using the spin coating process. Solvent incompatibilities between different resist systems can cause unwanted dissolution and intermixing of adjacent layers. Here, the authors show the use of Hansen solubility parameters to identify compatible solvents and developers. Multiple solubility models have been proposed, and Hansen solubility parameters are the most widely accepted. The Hansen solubility parameters are used to form a three dimensional space in which polymers and their solubility in different solvents can be represented as spheres. This representation makes it convenient to select compatible solvents and developers. It can also provide necess...

Three dimensional nanostructures are of great interest in photonics and optical sensor communities. Although there are many theoretical models developed, lithographic reduction to practice is an ongoing challenge. Numerous lithographic techniques have been proposed for fabricating three dimensional structures with applications in photonics. We demonstrate a novel three-dimensional electron beam fabrication method that is precise, fast, intrinsically self-aligned and has the ability to produce large area patterns.

Native acting phase-programmed defects, otherwise known as buried program defects, with attributes very similar to native defects, were successfully fabricated using a high-accuracy overlay technique. The defect detectability and visibility were analyzed with conventional amplitude and phase-contrast blank inspection at 193-nm wavelength, pattern inspection at 193-nm wavelength, and scanning electron microscopy. The mask was also printed on wafer, and printability is discussed. Finally, the inspection sensitivity and wafer printability are compared, leading to the observation that the current blank- and pattern-inspection sensitivity is not enough to detect all of the printable defects.

At the end of 2008, the College of Nanoscale Science and Engineering (CNSE) formally accepted a Vistec VB300 Gaussian electron beam lithography system. The system is a key component of the overall lithography strategy of the College and complements existing state of the art tooling for 193nm immersion, Extreme Ultra Violet and nanoimprint. The demonstrated resolving power of the system easily exceeds that of the facility's optical scanners. Together with 300mm wafer compatibility, and a class 1 mini environment, the system is well poised to execute its primary mission of supporting a variety of programs in post CMOS device integration. For a 300mm tool to be able to exchange wafers with other tooling in a full flow line it is necessary to pass stringent backside metal contamination testing. TXRF (total reflection x-ray fluorescence) testing performed with 300mm wafers on the VB300 satisfied the permitted metal contamination levels and cleared the way for introduction of ebeam patterned wafers into the process flow. Most of the tooling in the 300mm line handles wafers in front opening universal pods (FOUPS). With the relatively low throughput of the system (hours per wafer, not wafers per hour), this type of interface is not required. In order to maintain a low level of defects, 300mm wafers are removed from the FOUPS in the class 1 mini environment and loaded into the system. In addition to the 300mm capability, the system supports a wide range of wafer sizes, photomasks and piece parts. This enables the platform to support the 200mm activities at the College as well as the small samples frequently encountered with novel materials that have no support tooling available for 200mm and 300mm wafer sizes. The VB300 platform readily met the Vistec standard acceptance test specifications. The paper presents details of the acceptance test together with examples of additional work in progress that includes implementation of rigorous tool monitor standards, imprint template fabrication and mix and match overlay between the VB300 and optical patterning tools.

A novel asynchronous nanowire crossbar architecture has been recently proposed by authors' research group. The proposed clock-free architecture provides numerous significant benefits over its clocked counterparts which include better manufacturability, scalability, modularity and robustness. We also proposed various gate mapping and reconfiguration algorithms for defect-tolerant programming of PGMB (programmable gate macro blocks) - which is the primary building block of the proposed architecture. These algorithms were tested by simulations and a variety of parameter values were applied to show their performance characteristics. The most important performance metric of the proposed techniques is the programmability (i.e., the ratio of successfully programmed gates to the total number of gates). However, algorithms with higher programmability should come with higher time/space requirements. In this work, we will evaluate the tradeoff between programmability and time/space requirements and suggest a way to find the most suitable algorithm with acceptable combination of programmability and time/space requirements.

Recently, we proposed a new clock-free nanowire crossbar architecture based on a delay- insensitive paradigm called Null Convention Logic (NCL). The proposed architecture has simple periodic structure that is suitable for non-deterministic nanoscale assembly and does not require a clock distribution network - so it is intrinsically free from timing-related failure modes. Even though the proposed architecture offers improved manufacturability, it is still not free from defects. This paper elaborates on the different programming techniques to map a given threshold gate macro on a random PGMB (Programmable Gate Macro Block) with predefined dimension. Defect-Aware and Defect Unaware approaches have been considered to map a given threshold gate onto a PGMB without affecting its functionality. Defect aware approach uses a defect map, gate table which help in efficient programming and also conservative use of resources. Defect unaware approach on the other hand is faster than defect aware approach, does not use defect maps and is not as efficient as defect aware approach. Parametric simulation results using MATLAB are used to show the programmability of these approaches under various circumstances.

In this paper a method is being proposed to find the optimal dimension of Programmable Gate Macro Block (PGMB) in clock-free nanowire crossbar architecture. A PGMB is a nanowire crossbar matrix with discrete number of rows and columns on which the NCL (Null Convention Logic) gates can be programmed. This method uses inherent redundancy to route through defective crosspoints. A 6 X 10 defect-free crossbar can be used to program any of the 27 threshold gates. Due to imperfections and variations in nanoscale manufacturing process, high defect densities are anticipated. Thus, such defects should be located when tested and the logic has to be rerouted around them to maintain proper functionality. This paper discusses this problem and tried to find an optimal solution through simulations. In the final submission, more effective logic mapping techniques will be proposed and validated.

There have been numerous nanowire crossbar architectures proposed till date, although all of them are envisioned to be synchronous (i.e., clocked). The clock is an important part in a circuit and it needs to be connected to all the components to synchronize their operation. Considering non-deterministic nature of nanoscale integration, realizing them on a nano wire crossbar system would be quite cumbersome. Unlike the conventional clocked counterparts, a new clock-free crossbar architecture is proposed to resolve the issues with clocked counterparts in this paper, where the use of clock is eliminated from the architecture. This has been done by implementing delay-insensitive logic encoding technique called Null Convention Logic (NCL). A delay-insensitive full adder has been implemented on the proposed architecture to demonstrate the feasibility in this paper.

Scatterometry is one of the most useful metrology methods for the characterization and control of critical dimensions and the detailed feature shape of periodic structures found in the microelectronics fabrication processes. Spectroscopic ellipsometry (SE) and normal incidence reflectometry (NI)-based scatterometry are widely used optical methodologies for metrology of these structures. Evolution of improved optical hardware and faster computing capabilities led to the development of Mueller matrix (MM)-based scatterometry (MMS). Unlike SE and NI, MM data provides complete information about the optical reflection and transmission of polarized light interacting with a sample. This gives MMS an advantage over traditional SE scatterometry due to the ability to characterize samples that have anisotropic optical properties and depolarize light. In this paper, we present the study of full MM (16-element) scatterometry over a wide spectral range from 245 to 1700 nm on a series of one-dimensional, two-dimensional symmetric, and asymmetric grating structures. A series of laterally complex nanoscale structures were designed and fabricated using a state-of-the-art e-beam patterning. Spectroscopic MM and SE data were collected using a dual rotating compensator ellipsometer. Commercial modeling software based on the rigorous coupled-wave approximation was used to precisely calculate the critical dimensions. Results from MMS were compared with scanning electron microscopy.

As scaling continues, the need for reliable sub-10-nm electron beam lithography is apparent. Throughput is a major drawback and complex test structure fabrication would be constrained by practical limits on writing time. A major challenge for sub-10-nm patterning with electron beam lithography is tool and process efficiency especially for high sensitivity resists. This article presents current work done at the College of Nanoscale Science and Engineering where the authors investigated three different commercially available resist systems, namely, SU-8, NEB-31, and HSQ, which have a range of sensitivity from close to the shot noise limit to slow material with high resolution. The authors present the results obtained from these resists with their respective critical dimension, line edge roughness (LER), and line width roughness (LWR) values that correlate with sensitivity and are consistent with the well known resolution, line edge roughness, sensitivity trade-off. Due to the inability of tools to deliver l...