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In this paper, a 2-bit digital reflection-type phase shifter working at 120 GHz is presented. It uses a compact coupled-lines coupler with low insertion loss and high isolation over a wide bandwidth. The loads are made by a microstrip-line loaded by three PIN diodes whose states are tuned ON/OFF to obtain 90°, 180° and 270° phase shift relative to the reference (0°). Measurement results show RMS phase and amplitude error equal to 10.3° and 1.2 dB, respectively. The maximum insertion loss is equal to 8.6 dB, leading to a figure of merit of 31°/dB. As shown by simulation, by flipping PIN diodes and use negative voltage for biasing, the maximum insertion loss could be reduced to 3.6 dB (figure of merit of 75°/dB) along with a great improvement in RMS phase and amplitude errors, thus showing the potential of the proposed architecture.

This letter presents an ultra-wideband crossover based on metallic-nanowire-filled membrane (MnM) from dc to 110 GHz. Two designs are proposed with reduced insertion loss and high isolation. Design Type 1 presents a 1.2 dB insertion loss and 19 dB isolation up to 80 GHz, with a phase imbalance of 14° at 80 GHz. This important phase imbalance is due to CPW that passes under the top microstrip (MS) line. To improve the device, a CPW was used in both paths. The improved design Type 2 shows a 1.5 dB insertion loss, 0.2 dB insertion loss imbalance, and 3.3° phase imbalance at 110 GHz. The latter presents a measured isolation of 38 dB up to 70 GHz and a simulated isolation better than 30 dB up to 110 GHz.

A switched‐line substrate integrated waveguide 1‐bit phase shifter is designed and measured at 28 GHz. Reconfigurability is achieved through a set of floating metallized vias whose connection to the waveguide top and bottom layers can be controlled using PIN diodes. The reconfigurable vias are used to dynamically create alternative paths having different phase delays. A three‐metal layer printed circuit board stack‐up is employed to fully integrate the diode biasing network and to ease the routing of the bias signal. The high integration of the proposed configuration makes it well suited for the implementation of reconfigurable Butler matrices. The phase shift offset between the two states of this digital 1‐bit phase shifter equals 262° at 28 GHz, leading to a measured figure of merit of 161°/dB, and input 1‐dB compression point over 20 dBm. The total area is 13.72 × 10.9 mm without feeding lines and bias.

In this paper, the design of a 77.3 GHz Standing-Wave oscillator (SWO) is presented. The proposed SWO relies on the distribution of varactors along an asymmetrical slow-wave coplanar stripline, which enables the improvement of the quality factor of the tunable resonator, resulting in superior performance in terms of phase noise and DC-to-RF efficiency. The design methodology, based on the use of analytical models and abaci, is presented in detail and applied to a design in a 55-nm CMOS technology. With a core consumption of 15.1 mW, the proposed SWO operates from 76.09 GHz to 78.60 GHz and presents a phase noise of −115.1 dBc/Hz at 10 MHz offset, leading to a Figure of Merit (FOM) of −181 dBc/Hz. The DC-to-RF efficiency obtained is 3.1%.

This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50- $\Omega $ load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50- $\Omega $ load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50- $\Omega $ load connection.

The design of a compact substrate integrated waveguide (SIW) cavity-backed circular-polarized antenna using a slow wave structure is proposed in PCB technology. Based on a multilayer substrate, this topology includes internal metallized blind via holes connected to the bottom conductive plane, inducing the physical separation of electric and magnetic fields in the SIW cavity. Hence, a slow wave effect is obtained, allowing a 47% reduction of the antenna cavity in comparison with its classic SIW antenna counterpart. Moreover, by asymmetrically inserting an inductive via into the patch region, a degenerated mode allows both a circular polarization and an enlargement of impedance bandwidth. Measurements and simulations are in good agreement in terms of radiation pattern and circular polarization with a return loss of 15 dB and a gain of 4.8 dBic.

This article introduces a description of the slow wave effect based on the analysis of spatial field separation. Considering an ideal parallel-plate framework, approximate analytical expressions are derived for the slow wave factor (SWF), as well as dielectric attenuation. In particular, it is shown that the SWF can be related to the spatial distribution of both electric and magnetic fields. It is also demonstrated that the dielectric attenuation increases by the same factor as the velocity reduces. The derived principles are applied to a study case consisting of a parallel-plate waveguide partially filled with vertically grown metallic nanowires.

MEMS-based phase shifters show the best performance in terms of figure of merit, but their footprints are usually large and it is difficult to achieve several bits. This paper demonstrates a miniaturized phase shifter based on slow-wave CPW and MEMS that occupy 0.47 mm2. A total phase shift of 152° was obtained with a maximum insertion loss of 3 dB, resulting in a figure of merit of 50°/dB at 60 GHz. The 3-bit device showed an insertion loss variation of 1.3 dB and return loss better than 13 dB. The pull-in and pull-out voltages were measured to be 17 V and 10 V, respectively. The presented device is well suited for mm-wave phased array applications. Thanks to the proposed concept, more bits could be easily achieved and much higher frequencies could be addressed.

In this paper, the patch concept is applied to the design of millimeter-wave band-pass filters in BiCMOS 55 nm technology. The operation frequencies are 120 GHz and 200 GHz, respectively. A via- and slot-based approach makes filters very compact, albeit patch-based, through a multi-mode approach. At 200 GHz, the side of the patch is only 194 μm long, or about a quarter wavelength, compared to half a wavelength for a conventional patch. The dependence of performance on the thickness of the Back-End-Of-Line is studied, and the design method is detailed. The performance is very good, with for example a filter operating at 200 GHz with a relative bandwidth of 23% and insertion loss of 3 dB. Finally, the prospect of using a thicker Back-End-Of-Line, offered as an option in 55-nm BiCMOS technology, makes it possible to show that even better performance can be achieved, with insertion loss below 3 dB.

The study presented in this article concerns germanium telluride (GeTe) phase-change material-based switches, actuated via direct heating and arranged through two configurations: series or shunt. It is concluded that direct heating provides a performing solution for GeTe amorphization, preventing heater aging. The two configurations are compared in terms of RF performance, power handling, and linearity. Some design rules are derived from empirical data, consolidated with thermal simulations. In either configuration, a large, thick, and short GeTe switch geometry is preferable. Higher isolation can be obtained in shunt configuration, while lower insertion loss can be reached in a series configuration. The Figure-of-Merit, as cutoff frequency, is 11 and 21 THz for shunt and series configurations, respectively. In terms of power handling, for amorphous GeTe, results confirm the existence of a threshold voltage leading to better handling for longer switches in both configurations. For crystalline GeTe, design rules that link the maximum current through the switch before failure to the material geometry are derived for the very first time. It is shown that current is proportional to the GeTe switch width, to the square root of its thickness, and inversely proportional to its length. The shunt configuration presented here holds 31 dBm at ON-state and more than 35 dBm at OFF-state while the series configuration holds 27 dBm at ON-state and 32 dBm at OFF-state. For power handling, a balance exists between series and shunt configurations with a ratio of 4 in the crystalline phase and of 0.25 in the amorphous phase.

In this paper, an original architecture of a mm-wave passive phase shifter is presented. It is based on an original hybrid approach mixing digital and analog stages to form a 0-360° continuous phase shifting. The overall architecture is presented and a detailed analysis of the insertion loss of each stage is performed, leading to a figure of merit of 34°/dB. Then the design of the 45° digital stage is carried out up to the layout, with a careful description of the optimization steps.

The impact of interface charges under the gate spacer on FDSOI devices integrated in low temperature process are explored. A great number of traps (~1013/cm2) are identified on the interface between the spacer oxide and the silicon film using Terman's method for interface states characterization. Thanks to electrical characterization and TCAD simulations, it is shown that the trapped charges induce the formation of a depleted region in the vicinities of the spacer. Moreover, a strong degradation of performances on underlap channels is observed. The spacer charges influence on reliability measurements is finally explored.

In this paper, a compact and high-performance Reflection-Type Phase Shifter operating around 2 GHz is proposed. It is realized in standard PCB technology by using a very compact transdirectional coupler and simple tunable reflection loads. The circuit size is equal to 0.29 • 0.1$\lambda _g^2$. This small size is achieved without sacrificing performance; the figure of merit, given by the ratio of the maximum phase shift divided by the maximum insertion loss reaches 169°/dB at 2.15 GHz, which is comparable to the average performance published in the literature. The demonstrated small size paves the way for the realization of very compact RF feeding networks for phased arrays.

This paper presents Wilkinson power divider (WPD) designs using slow-wave microstrip lines realized in multilayer printed-circuit-board technology. The main objective of this work is to reduce the size of the WPD using simple technique while maintaining similar electrical performance as a conventional WPD realized using conventional microstrip lines. Two Wilkinson power dividers (1:2 and 1:4) are designed and measured. The proposed dividers operate at 2.45 GHz. As compared to WPD realized using conventional microstrip lines, the proposed 1:2 WPD exhibits a size reduction of 44%.

International audience; This paper gives an overall picture from BiCMOS technologies up to THz systems integration, which were developed in the European Research project TARANTO. The European high performance BiCMOS technology platforms are presented, which have special advantages for addressing applications in the submillimeter-wave and THz range. The status of the technology process is reviewed and the integration challenges are examined. A detailed discussion on millimeter-wave characterization and modeling is given with emphasis on harmonic distortion analysis, power and noise figure measurements up to 190 GHz and 325 GHz respectively and S-parameter measurements up to 500 GHz. The results of electrical compact models of active (HBTs) and passive components are presented together with benchmark circuit blocks for model verification. BiCMOS-enabled systems and applications with focus on future wireless communication systems and high-speed optical transmission systems up to resulting net data rates of 1.55 Tbit/s are presented.

In this paper, the slow-wave effect and air-filled technology are combined to achieve a compact and efficient substrate integrated waveguide in the W-band. The MnM interposer technology, based on a nanoporous alumina membrane and copper nanowires, allowing a simple through substrate via fabrication, was used. A first partially-air-filled slow-wave substrate integrated waveguide was fabricated and measured, resulting in a reduction of the attenuation constant by 75% at 1.2 times the cut-off frequency as compared to the classic SIW, with Slimilar dimensions.

This paper presents the design of a voltage controlled Standing-Wave Oscillator for applications in the E-band. A high quality factor tuneable Slow-wave Coplanar Stripline is used for the resonator. Varactors are distributed along the transmission line to mitigate the effect of their low Q-factor on the losses of the resonator. The Slow-wave Coplanar Stripline is asymmetrically sized to maximise the tuning range. The VCO achieves a measured phase noise of −114.9dBc at 80 GHz with 15mW power consumption and 3.3% continuous frequency tuning range.

In this letter, an X-band reflection-type phase shifter is presented. It is based on a single-layer stub-loaded coupled-line coupler loaded by two-varactor tuning circuits. This choice of coupler significantly improves on the phase shifter bandwidth achievable with a branch-line coupler, as it features a lower phase imbalance across the band of interest. The proof-of-concept prototype achieves better than 10-dB return loss across a 20% fractional bandwidth. The phase shifter further exhibits insertion loss of 2.1 ± 1.3 dB and maximum phase shift of 392° at 10 GHz, leading to a state-of-the-art figure of merit at X-band of 115°/dB. The occupied area is $0.25\lambda _{g}^{2}$ .

In this paper we present a balun on the MnM interposer technology platform based on a microstrip to CPS transition that was designed to feed a quasi-Yagi antenna at 60 GHz. Two microstrip lines with lengths differing in half a wavelength create a phase shift of 180° from a single-ended input. The balun structure occupies an area of 0.2 mm2 and operates in the frequency range between 67 GHz and 76 GHz. The output amplitude and phase imbalance of the balun are lower than 1 dB and 10 degrees, respectively.

This paper presents the design of a planar miniaturized 4x4 Butler matrix, with implementation of 4 tunable 135° delay line phase shifters for a 160 GHz application. The Butler matrix and phase shifters are both realized with a metallic nanowire filled alumina membrane (NaM) technology, using slow-wave microstrip line to miniaturize the size. Tunability is achieved by filling in a microwave liquid crystal. Comparing with commonly used corporate feed network, the simulation results show such a Butler matrix with 135°-phase shifters has less insertion loss and reduced size.

International audience; This work presents a comparative study of conventional and slow wave (SW) transmission lines implemented in an advanced 22-nm CMOS process. Both microstrip (MS) and coplanar waveguides (CPW) were analysed through simulations and measurements. A classical SW approach was used for the implementation of the SW CPWs while the SW effect was generated in the MS lines using bed of nails integrated in the CMOS process. As a proof of concept, the proposed SW MS approach was employed to design a new artificial quarter-wave TL section. The proposed configuration was created loading a meandered MS line with open ended S-MS stubs acting as discrete capacitive loads. Results show that the proposed methodology offers an attractive form factor and good performance.

This paper presents and validate the concept of a suspended, slow-wave microstrip transmission line that uses air as a substrate. The lines are fabricated on a low-cost interposer technology, the metallic nanowire membrane (MnM), that allows selective growth of copper nanowires, enabling transmission lines with a wide range of Z c . Lines with widths of $35 \mu \mathrm{m}, 25\mu \mathrm{m}$ and $15\mu \mathrm{m}$ were designed and fabricated with 1, 2 or 4 suspended segments of $250\mu \mathrm{m}$ or $500\mu \mathrm{m}$ of length. Parametric extraction from the measured S-parameters showed $\varepsilon_{eff}$ ranging from 5 to 7.5, $\alpha$ smaller than 0.8 dB/mm at 70 GHz and Q as high as 55. Z c varied between $65 \Omega$ and $90 \Omega$.

We propose and demonstrate experimentally a band-modulation device with extremely sharp switching capability. The Z 3 -FET (Zero gate, Zero swing and Zero impact ionization) has no top gate, is processed with FDSOI CMOS technology, and makes use of two adjacent buried ground planes acting as back gates. The buried gates emulate respectively N + and P + regions in the undoped body, forming a virtual thyristor-like NPNP structure with feedback operation. Vertical output I A – V A and transfer I A – V G characteristics over more than 8 decades of current are measured with relatively low gate and drain bias (

This paper presents a compact substrate integrated waveguide (SIW) sensor combining slow-wave and air-filled technologies for humidity environment detection. Designed in a multilayer printed-circuit-board process, the proposed sensor operates at 5.8 GHz, in the industrial, scientific and medical (ISM) frequency band. Since the permittivity of the air depends on its relative humidity, the detection is obtained by measuring the resonant frequency shift of a SIW resonator. Whereas air-filled technology allows improving sensitivity detection, slow-wave effect allows both concentrating the electric field in the air and reducing the size of the sensor. Hence, a surface area reduction of the resonator cavity of 41% and 75% is obtained as compared to the partially air-filled SIW and the fully air-filled SIW, respectively. A good agreement between the numerical EM simulation and the experimental result without humidity variation is obtained. Moreover, thanks to the concentration of the electric field in the air region of the cavity, simulation results show that a sensor sensitivity of 973 kHz/RH can be expected. It allows validating the interest of combining slow-wave SIW and air-filled technology for humidity sensing application.

In this paper, a predictive electrical model of the slow-wave coplanar waveguide structure (S-CPW) is presented. The model was developed under the assumption of Quasi-TEM propagation mode. This assumption allows treating separately the electric field from the magnetic field. Therefore, inductive and capacitive effects are processed apart. Within this context, analytical formulas, parameterized by S-CPW geometric dimensions, are given for each electric parameter in the model, including resistances that account for losses. The model was validated with electromagnetic simulations $({\rm HFSS}^{{{{\rm TM}}}})$ and measurement results on several integrated technologies. An excellent agreement was achieved over a wide frequency band from DC up to 110 GHz, with a maximum error of 10%. Consequently, the model provides a fast and powerful tool for designing circuits based on S-CPW. The developed model enables a better insight of how geometries influence the overall S-CPW performance. The model was applied to the design of a quarter-wave length transmission lines and tunable phase shifter. The transmission lines were optimized in terms of performance, minimum length or surface. The tunable phase shifter was designed by embedding varactors in the S-CPW floating shield. These designs highlight the efficiency of the model for complex optimization or complex circuits design, respectively.

A three-stage 60-GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High-quality-factor slow-wave coplanar waveguides (S-CPW) were used for input, output and inter-stage matching networks to improve the performance. Being biased for Class-A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3-dB bandwidth of 8.5 GHz. The measured 1-dB output compression point (OCP1dB) and the maximum saturated output power Psat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm2 (875 × 600 μm2) including all the pads, whereas the effective area is only 0.24 mm2. In addition, the performance improvement of the PA in terms of G, OCP1dB, Psat, PAE and the figure of merit using S-CPW instead of thin film microstrip have been demonstrated. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2015.

A new flexible and miniaturized power divider (PD), based on the Wilkinson PD topology, is carried out in this paper. Flexibility and size reduction are achieved simultaneously thanks to both an open-stub loading the input port and additional transmission lines (TLines) connecting the output ports to the isolation resistance. Design equations and rules are given. As a proof-of-concept, two PDs working at 2.45 GHz were fabricated and measured. Then, on the basis of the previous developments, a 1:4 power-dividing feeding network was realized. It highlights the high performance and flexibility of the proposed PD. Agreement between simulation and measurement results is very good, for PDs as well as for the feeding network, thus validating the proposed approach. This concept is straightforward to be applied at higher frequencies, in particular in the millimeter-wave range on CMOS technologies, where flexibility in the choice of the TLines characteristic impedances and size reduction are mandatory.

This paper presents the design of a mm-wave VCO with high quality factor slow-wave coplanar stripline synthesized inductor. The objective is to show the advantage of using slow-wave coplanar stripline to improve the figure of merit. For that purpose, the proposed VCO is compared to its classical LC-tank VCO counterpart in the same technology. Both VCOs use same varactors and are designed for center frequency of 80 GHz in BiCMOS 55 nm technology. Due to high quality factor (≈38) of slow-wave coplanar stripline, the phase noise is 6 dB better and power consumption is 30% lower than classical LC-tank VCO. The slow-wave coplanar stripline based VCO also achieved 17% higher frequency tuning range. The measured phase noise is −112 dBc/Hz at 10 MHz offset for the proposed VCO with power consumption of 6.3 mW and output power of −3 dBm.

International audience; This paper presents a novel 3D inductor (solenoid) fabricated on a 50-pm thick AAO membrane using nanowire-vias. Several inductors were fabricated in this simple and low-cost technology with nanowires. They were measured up to 110 GHz and compared to the state-of-the-art results presented in the literature in different technologies: CMOS, glass, LCP and MEMS. The simulations are in good agreement with measurement, predicting the great potential of these inductors. The first 3D inductors using nanowire-vias presented inductances from 0.5 nH to 1.7 nH with small areas that range from 0.03 mm2 to 0.08 mm2.

This paper gives a complete theoretical study in a narrow band for the parallel-coupled filters based on short-circuited stub-loaded resonators. It describes a synthesis method for this filter topology, and a complete resonant mode analysis to fully control the spurious frequencies positions. To enlarge the out-of-band rejection, an original technique, based on simple design steps, is used to address tuning of extra transmission zeros. Harmonic was suppressed to better than 35 dB with a wide stopband of more than six time the fundamental frequency. Design equations and design rules are given. Finally, several three-pole bandpass filters are designed and characterized in stripline and miscrostrip technologies to demonstrate the efficiency of the proposed concepts.

Based on a CMOS slow-wave coplanar-waveguide transmission-line topology, a novel compact millimeter-wave phase shifter is presented. The tunability is accomplished by using a liquid crystal (LC) material as a tunable dielectric between the coplanar signal strip and the shielding plane of the slow-wave transmission line. The device tunability is considerably enhanced by moving the free-standing signal strip with the application of a bias voltage. Combining the miniaturizing benefits of the slow-wave effect with the continuous tuning of LC material, the proposed device occupies only 0.38 mm2 and exhibits high performance. The phase shifter was characterized up to 45 GHz for a maximum bias voltage of 20 V without significant power consumption. The reproducible measurements show a figure-of-merit (ratio between the maximum phase shift and the maximum insertion loss) of 51°/dB at 45 GHz.

This paper presents a mm-wave compact, ultra-wideband reflection-type phase shifter (RTPS). This phase shifter is dedicated to phased array transmitter based on LO-path phase shifting for beamforming and beam-steering applications in the sub-mm-wave band. The proposed RTPS is designed using a slow-wave coplanar waveguide coupler and reflective loads. The circuit was fabricated in BiCMOS 55 nm technology. As predicted by simulations, measurement results show a relative phase shift of 61°±1° that is very stable over a wide frequency range from 30 GHz to 50 GHz, with insertion loss of 4 dB ± 1 dB at 50 GHz, leading to a figure-of-merit (FoM) of 12°/dB. The measured return loss is always better than 10 dB across the whole band. The chip area is only 0.18 mm2.

This article presents a novel method for the design of tunable and miniaturized power dividers.It is based on three impedance transformers and requires a single bias voltage command, instead of three commands needed for more classical designs. This single voltage simplifies the power divider in terms of design and use. For a proof-of-concept, a power divider with a 950 MHz working frequency has been designed, with two output varactors tuning the power repartition through the two output ports. Thanks to the developed approach, the miniaturization ratio between our power divider and the Wilkinson one is equal to 75.5% at 950 MHz. Measurements show a wide tunable power ratio between the two output ports (1:3.4), a very good matching in the pass band (return loss better than 16 dB), low insertion loss (0.6 dB), and a tunable bandwidth of ±15%. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:357–363, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27297

This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.

A new methodology for the synthesis of tunable patch filters is presented. The methodology helps the designer to perform a theoretical analysis of the filter through a coupling matrix that includes the effect of the tuning elements used to tune the filter. This general methodology accounts for any tuning parameter desired and was applied to the design of a tunable dual-mode patch filter with independent control of center frequency and bandwidth (BW). The bandpass filter uses a single triangular resonator with two etched slots that split the fundamental degenerate modes and form the filter passband. Varactor diodes assembled across the slots are used to vary the frequency of each degenerate fundamental mode independently, which is feasible due to the nature of the coupling scheme of the filter. The varactor diode model used in simulations, their assembling, the dc bias configuration, and measured results are presented. The theory results are compared to the simulations and to measurements showing a very good agreement and validating the proposed methodology. The fabricated filter presents an elliptic response with 20% of center frequency tuning range around 3.2 GHz and a fractional BW variation from 4% to 12% with low insertion loss and high power handling with a 1-dB compression point higher than .

Graphical abstractThe concept of a slow-wave MEMS phase shifter using a maskless post-CMOS etch to release the ribbons of the shielding layer is presented. The ribbons can be actuated electrostatically, which results in a change of the equivalent capacitance, thus a change in phase.Display Omitted Highlights? New concept of phase shifter for millimeter wave frequencies. ? State-of-the-art performance is expected. ? Simple post-CMOS maskless etch is used to realize electrostatically actuated MEMS. ? Virtually no power consumption, small foot print, and low loss for 360? phase shift. We propose a slow-wave MEMS phase shifter that can be fabricated using the CMOS back-end and an additional maskless post-process etch. The tunable phase shifter concept is formed by a conventional slow-wave transmission line. The metallic ribbons that form the patterned floating shield of this type of structure are released to allow motion when a control voltage is applied, which changes the characteristic impedance and the phase velocity. For this device a quality factor greater than 40 can be maintained, resulting in a figure of merit on the order of 0.7dB/360? and a total area smaller than 0.14mm2 for a 60-GHz working frequency.

Slow-wave coplanar striplines (S-CPS) have been implemented in the standard AMS 0.35 μm CMOS technology. Compared to conventional coplanar striplines (CPS), at 20 GHz, the proposed S-CPS line has more than 675% increase in quality factor, 54% improvement in the attenuation constant and 72% reduction in the electrical length. The RLCG model has also been extracted and the sources of losses have been identified. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:650–654, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26645

This paper presents an analysis of a reconfigurable patch filter based on a triple-mode circular patch resonator with four radial slots. The analysis has been carried out thanks to the development of a new theoretical approach of the tunable patch filter based on the coupling matrix. The coefficients of the coupling matrix related to the tunable behavior have been identified and some rules for their evolution have been derived. For a proof-of-concept, a bandpass filter has been designed with a continuous tunability obtained with varactors connected across the slots. State-of-the-art results have been obtained, with a frequency tuning range of 27% from 1.95 to 2.43 GHz and a change in fractional bandwidth from 8.5% to 31.5% for the respective frequencies. In the entire tuning range, the return loss is better than 10 dB and the maximum insertion loss is 2 dB. Due to the newly developed coupling matrix, measurements, simulations, and theory showed great agreement.

Shielded coplanar waveguides are promising candidates for the development of high quality factor transmission lines in millimeter-wave frequency bands. In this article, state-of-the-art experimental results carried out on a CMOS 0.35 μm low-cost technology are presented. This letter especially deals with the benchmark of slow-wave transmission lines in focusing on the impact of technology dispersion on the measurement results. Eight dies have been measured, each from a different wafer, showing a robust design versus the technology. These results open new possibilities for the development of miniaturized low-loss compact passive devices. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2786–2789, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25598

This article describes the design and performance of a compact tunable impedance transformer. The structure is based on a transmission line loaded by varactor diodes. Using only two pairs of diodes, the circuit is very small with a total length of only λ/10. Both the frequency range and the load impedance can be tuned by varying the varactor bias voltages. Our design provides a tunable operating frequency range of ±40% and an impedance match ranging from 20 to 90 Ω at 0.8 GHz and from 30 to 170 Ω at 1.5 GHz. In addition, a new approach that considers losses for the simulation and measurement of this impedance transformer was investigated. The measured performance of a 1 GHz prototype design confirmed the validity of this new approach.

We produced three symmetric power divider ports, compact, fixed, and tunable based, with hybrid technology by using capacitors CMS or commercial diode varactors, at low costs. These dividers consist of an impedance transformer in the shape of T in entry and by two transmission lines with an impedance of 50 Ω on the two output ports. The impedance transformer contains a transmission line with electrical length θ1, a fixed capacitor C or variable (diode), and another transmission line with electrical length θ2. We designed these power dividers at working central frequencies 900 and 1800 MHz for GSM applications by using two substrates: Epoxy and RO4003. The band pass should be higher than 20% around central frequency for a good adaptation (S11 < −20 dB) and also for losses lower than 0.3 dB. The size of our dividers is more than two times shorter than a classical Wilkinson power divider. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 229–232, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24005

Slow wave coplanar transmission lines (S-CPW), based on conventional coplanar CPW transmission lines with a floating patterned ground plane, consisting in floatting strips below the line, are good candidates for the integration of distributed RF circuits for front-end modules. They offer high quality factors when compared to conventional coplanar transmission lines. In this paper, guidelines are carried out for the design of such transmission lines. Simulations are first compared to already published measurements thus validating the simulation method used throughout the paper. Next, considering a standard 0.35 µm CMOS process, a design guideline is drawn in order to determine the characteristic impedance, the phase velocity and the dielectric effective constant of the S-CPW transmission lines, along with the attenuation loss and the quality factor. The effects of the floating strips duty cycle, the floating strip width and the ground plane width are studied.

A three-stage 60-GHz power amplifier was implemented in a 65 nm CMOS technology. High-quality-factor slow-wave coplanar waveguides were used for input, output and inter-stage matching networks in order to improve the performance. In Class-A operation, the power amplifier exhibits a measured maximum linear power gain G of 18.3 dB at 55 GHz, with a 3-dB bandwidth of 8.5 GHz. The measured 1-dB output compression point OCP 1dB and the maximum saturated output power P sat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16 %. The die area is 0.52 mm2 (875 ×m × 600 μm) including all the pads, whereas the effective area is only 0.24 mm2.