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Altres ajuts: Institució Catalana de Recerca i Estudis Avançats This article presents a low-cost and portable phase-variation planar microwave sensor operating in reflective mode, where the output variable, the phase of the reflection coefficient of the one-port sensing element, is retrieved by means of a distributed circuit based on a pair of rat-race hybrid couplers and the associated electronics. This includes a microcontroller, a voltage controlled oscillator (VCO), a digital-to-analog converter (DAC), and an RF/microwave gain/phase detector. By this means, vector network analyzers (VNAs), i.e., high-cost instruments typically used for obtaining the reflection coefficient in one-port structures or circulators (microwave components able to separate the injected signal from the reflected signal in any one-port network) are avoided. Indeed, the presented architecture (including the microwave rat-race hybrid configuration and the associated electronics) can be adapted to other one-port reflective-mode phase-variation microwave sensors. A prototype example, where the sensing element is a one-port step-impedance open-ended transmission line, is reported. The device provides the phase of the reflection coefficient of the sensing element as a function of the dielectric constant of the material under test (MUT) with a maximum sensitivity of −65.7° and a relative error of less than 8% in all the measurements.

This work presents an ultra-low jitter, direct W-band phase-locked loop (PLL). Using the proposed power-gating injection-locked frequency multiplier (PG-ILFM)-based phase detector (PD) that can maintain a high phase-error-detection gain even at high frequencies above 100 GHz, this W-band PLL can achieve a very low in-band phase noise. Due to this intrinsically low in-band phase noise, the bandwidth of the PLL can be extended so that it can suppress the poor phase noise of the W-band voltage-controlled oscillator (VCO). The frequency-offset canceller (FOC) is also presented to remove the possible frequency offset between the main VCO of the PLL and the replica VCO of the PG-ILFM-based PD. Operating in the background, the FOC can ensure high phase-error-detection gain and wide loop bandwidth and, thus, the low-jitter performance of the PLL. The proposed PLL was fabricated in a 65-nm CMOS process, and it used a power of 22.5 mW and an area of 0.16 mm². The rms jitter, integrated from 1 kHz to 300 MHz, was 82 fs at 102 GHz. It also achieved the $FoM{_{{JIT}}}$ of -248.2 dB, which is the best among the state-of-the-art W-band frequency synthesizers.

Accurate faulty phase detection under single-line-to-ground (SLG) fault is the basis of the emerging voltage-based fault arc suppression technology. Most conventional faulty phase recognition criteria assume the distributed line-to-ground parameters are symmetrical, therefore suffering invalidity in actual distribution networks especially under high-resistance ground-fault conditions. This paper firstly analyzes the magnitude and phase angle variation models of the phase-to-ground voltages before and after the SLG fault. Considering the asymmetrical distributed parameters and the line impedance, the specific phase-to-ground voltage variation rules corresponding to SLG fault on each phase are then discussed. Based on the voltage variation rules, a robust and practical method for faulty phase identification is proposedwhich does not need the distributed parameters. Finally, the correctness of the variation rules and the availability of the proposed method is verified by simulation. Comparative study shows the proposed method has better accuracy and applicability with the conventional methods when the asymmetry and ground-fault resistance are high.

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This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm² and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/μs] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art.

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50μW RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm 2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

This article presents design techniques for a continuous-rate reference-free clock and data recovery (CDR) circuit employing a stochastic frequency-phase detector (SFPD). By taking a histogram-based design methodology, optimal weights for both frequency and phase detection are obtained by utilizing the same information as the Alexander phase detector. The design methodology is inductive and stochastic, distinguished from the conventional, deductive, and procedural methods. To verify a robust operation, the effects of varied data patterns, noise, and channel loss are examined, together with the avoidance of harmonic locking. In addition, a consideration of a sample window is analyzed by fast Fourier transform (FFT) simulation. Fabricated in 40-nm low-power (LP) CMOS technology, the proposed CDR circuit achieves a capture range from 6.4 to 32 Gb/s and a lock time of less than 11 μs. The measured frequency acquisition behavior shows that harmonic locking is avoided with a seamless transition to the fundamental mode. The CDR circuit tested over a 10-dB loss channel achieves a bit error rate (BER) less than 10⁻¹² and energy efficiency of 0.96 pJ/b.

A technique to reduce the area of a low-noise sub-sampling PLL (SSPLL) is proposed. The resistor in the loop filter is eliminated. The transconductor driven by the phase detector is switched such that its output consists of a positive and negative pulse with the former wider than the latter. A low frequency zero can thus be realized with a substantially smaller capacitor. Transconductor noise is suppressed to acceptable levels by the high phase-detector gain. In applications that require low out-of-band phase noise, the capacitance can be reduced by 25x or more with typical PLL parameters. A prototype SSPLL from 24.4 GHz-29.2 GHz with a 50 MHz reference clock and bandwidth of 1MHz in 65nm LP CMOS process uses a loop filter capacitance of only 5pF. The conventional topology would require 38pF for the same integrated jitter. The in-band phase noise at 1MHz offset ranges from -90 to -95dBc/Hz, and the out-of-band phase noise at 10 MHz offset ranges from -117 to -121dBc/Hz. The jitter integrated from 10kHz to 50MHz is 330-390fs. It consumes 18.2mW, exhibiting a minimum FoM of 235dB over the frequency range. The SSPLL occupies an area of only 0.14mm².

Active load impedance variations in a phased array transmitter cause significant power amplifier (PA) performance degradation, in terms of output power, linearity, and power-added efficiency, which are key parameters to enable high-speed data throughputs using spectrally efficient modulation schemes. The system performance can be restored by using PAs having active or passive reconfigurability with the help of antenna impedance sensors. This article presents a low-power reflection-coefficient sensor for 5G millimeter-wave phased-array applications. The complex load impedance of the PA is determined based on the complex voltage over a sensing element, which can be integrated and co-designed with the PA output matching network, with minimal loss (

A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ( $\Delta V_{\text {in}}$ ) is presented. Such adaptive operation significantly reduces the power of high-precision comparators in successive-approximation-register (SAR) ADCs. $\Delta V_{\text {in}}$ is integrated as a time difference via the VCO, where the integration continues as long as the time difference is below a certain threshold, defined by the phase detector deadzone. Thus, when $\Delta V_{\text {in}}$ is large, the comparator operates as a low-power delay line-based comparator, and with small $\Delta V_{\text {in}}$ , the VCO oscillates to integrate the input signal and suppresses the comparator noise. The required oscillations to complete the comparison are inversely proportional to $\Delta V_{\text {in}}$ , realizing fully adaptive noise and power scaling. This article provides a detailed analysis and specific design guidelines of the VCO comparator. Moreover, the PVT drift tolerance and detailed circuit implementations are deeply discussed as well. For proof-of-concept, a 13-bit SAR ADC with the proposed VCO-based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves peak SNDR 66 dB at 1 MS/s with a peak FoM of 29 fJ/conv.-step.

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-N phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional-N mode, a phase detector range reduction technique is used to halve the required DTC delay range (DR), resulting in lower thermal noise and better DTC linearity. Moreover, a reconfigurable dual-core voltage-controlled oscillator (VCO) provides extra freedom in power and jitter tradeoff. It achieves 83.4-fs rms jitter in fractional-N mode, integrated from 10 kHz to 100 MHz, with a 76.8-MHz crystal oscillator (XO) reference. In the low-power mode, the rms jitter degrades to 96.3 fs and the PLL FoM improves from -250.1 to -251.2 dB, as the PLL power consumption reduces from 14.2 to 8.2 mW. The measured fractional spurs are less than -70 dBc for near-integer channels. The PLL rms jitter remains within 100 fs across the 5-7-GHz output frequency band, thanks to the digital background calibrations. It is implemented in a 14-nm FINFET process and occupies 0.31 mm².

An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, the supply voltage, and the phase noise. Based on the review, the reduction in CMOS scaling decreases the transistor size in ADPLL design which leads to a smaller area and a low power dissipation. The combination of the time-to-digital (TDC) and the digital-to-time converter (DTC) that is used as the phase-frequency detector (PFD) in ADPLL is proposed to reduce the power and phase noise performance due to their high linearity design. The delay cell oscillator is found to consume more power at higher operating frequency, but it has an advantage of having less complexity and consuming less power and area in the circuit compared to the LC tank oscillator. For future work, it is recommended that an ADPLL-based LO of RFID transceiver with lowest voltage supply implementation is chosen and the use of the TDC-less as the PFD is selected due to its small area. While for the DCO, the delay cell will be designed due to its simpler implementation and occupy small area.

This study investigated various types of Micro-Electro- mechanical Systems (MEMS)-based detectors, which enabled the derivation of a general formula via microwave network analysis. Multiple microwave parameters were measured and converted into a problem involving N-port network structural design with the derived formula. Furthermore, a compact integrated detector was proposed by removing a redundant power divider. Additionally, one processing circuit was designed to compensate for the output voltages from the detector and calculate the microwave parameters. The detector fabrication process is compatible with GaAs monolithic microwave integrated circuit (MMIC) process. Experimental results indicate that the revised detector is at least 35% smaller than that obtained using existing methods. This approach can detect multiple parameters, including frequency, power, and phase detection on a monolithic chip.

Most conventional vital-sign radars cannot easily detect human vital sign signals under nonperiodic body movement. This article presents a novel frequency-locked loop (FLL) radar that can track the phase changes that are caused by nonperiodic body movement. A gain/phase detector and a cross correlation function (CCF) in the FLL radar greatly reduce the second harmonic, the intermodulation terms between vital sign signals and nonperiodic body movement noise, enhancing both the signal-to-noise ratio and the accuracy of detection of the vital signs. Measurements indicated that the implemented 2.4-GHz FLL radar with a gain/phase detector and CCF can effectively detect the human respiration rate (RR) and heart rate (HR) under nonperiodic body movement. Using a chest belt as the measurement reference, the standard deviation (SD) of RR and HR measurements were 1.27 and 5.69 beats/min, respectively, when the seated subject under test (SUT) swung nonperiodically his upper body. When the SUT walked away from the radar naturally at 2.6 km/h, the implemented FLL radar measured RR and HR with SDs of 2.67 and 8.28 beats/min, respectively.

This article presents a low-power fractional- ${N}$ all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efficiency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then amplified by a low-noise gated amplifier and digitized by a low-power successive approximation register analog-to-digital converter (SAR-ADC). Leveraging the benefits of digital architecture, gain mismatches from the waveform estimator are calibrated by means of an LMS algorithm, consequently lowering fractional spurs. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 2.0–2.3-GHz carrier with an rms jitter of 414 fs while consuming only 1.15 mW. This corresponds to a state-of-the-art ADPLL FoMjitter of −247 dB in a fractional- ${N}$ mode. Due to the wide (largely linear) monotonic range and $4\times $ oversampling rate from a 48-MHz reference, without any additional circuitry, the proposed ADPLL can settle within $3~\mu \text{s}$ in face of a 70-MHz frequency step.

A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. This wide-range FD is composed of a coarse FD and a fine FD (FFD) which share the same front-end comparators with the PD and the DFE. Thus, no extra comparators are required. In addition, by monitoring the drift direction of five samples on the five-bit data patterns, the FFD performs an error-free operation within a frequency error of 7.7%. Therefore, the CDR has a robust FD-to-PD transition. By using the proposed FD, this CDR circuit not only achieves a wide frequency capture range of 43%, but also has a short frequency settling time of $680~\mu \text{s}$ . This CDR circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.1004 mm2. The total power of the receiver is 39.9mW at 16 Gb/s, and the calculated energy efficiency is 2.49pJ/b.

In this work, we report the portable NMR system which provides solutions to the existing problems in miniature CMOS NMR systems. First, a higher IF of 50 kHz is achieved by exploiting separate frequencies for sample excitation and LO, thereby having higher immunity to 1/f noise. The proposed phase detector circuit aligns the experiment trigger with the constant phase difference between two frequencies. It maintains the constant RX output phase in every experiment, allowing the direct signal averaging without extra phase correction. In addition, 40X faster RX recovery with RX BW switching enables the signal acquisition with the dead time of 10 $\mu \text{s}$ . Fast settling improves the acquisition sensitivity. Lastly, a frequency calibration method based on signal peak detection is proposed. Combining the techniques with the fully integrated NMR transceivers, the system demonstrates the NMR experiments to measure the decaying time constant of less than 100 $\mu \text{s}$ . Furthermore, NMR diffusion experiments are performed with the echo spacing of $0.2\sim 8$ ms.

This paper introduces an accurate frequency regulation method based on a constant on-time (COT) buck regulator designed for point-of-load (POL) regulation with a fast load transient requirement and wide load range. Traditional COT regulators suffer from frequency shift due to load variations. The proposed frequency adjustment circuit helps the COT control engine to reach its target frequency of operation by adjusting the on-time pulse under varying conditions. This circuit includes a phase detector and a voltage-to-current converter block. The phase error between the target clock signal and the PWM is directly used to adjust the width of the on-time pulse. This will fine-tune the bandwidth of the frequency regulation loop, which can help to improve the transient performance of the COT as well. The fabricated chip has been tested under 20A/ $\mu \text{s}$ load transient speed with a 10A load step condition. The measured silicon performance shows that the error of the switching frequency is less than 0.16% in the 400kHz to 1MHz range during steady-state operation.

This paper describes a bias-current-free fractional-N hybrid phase-locked loop (HPLL) architecture that does not use a charge pump (CP) or a linear time-to-digital converter (TDC). A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection under a low supply voltage. The CP-less analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. Unlike the TDC, the flip-flop PD has negligible contribution to the in-band phase noise over different supply voltages. To mitigate $\Delta \Sigma $ quantization noise and PD nonlinearity effects, an FIR-filtered $\Delta \Sigma $ modulation is employed for fractional division. The proposed fractional-N HPLL implemented in 65-nm CMOS operates with a 0.65-V supply except a 0.9-V digital/voltage-controlled oscillator (D/VCO), consuming 1.85 mW at 1.2 GHz. The phase noise of–97 dBc/Hz at 1-MHz offset frequency and the reference spur of–76 dBc with the programmable notch filter are achieved. The measured in-band fractional spur levels vary from–37 dBc to–58 dBc. The experimental results show that the proposed architecture is promising for low-voltage clock generation and modulation systems.

This brief presents a hybrid PLL by leveraging the advantages of analog and digital techniques in the frequency-control loop to achieve ultra-compact area and ultra-low power consumption simultaneously. Specifically, the hybrid loop consists of two paths: an integral path features a charge-sharing integrator realized by switched capacitors with high precision in digital discrete integration to improve the frequency resolution without deteriorating the output phase noise, and a proportional path directly switches the bias voltage of the VCO varactors to compensate the phase margin without costing extra power and area. Both paths are digitally controlled by a tiny power-efficient 1-bit bang-bang phase detector (BBPD). Prototyped in 28-nm CMOS, the 1.3-to-2.3-GHz PLL occupies a core area of 600 $\mu \text{m}~^{2}$ and dissipates 380 $\mu \text{W}$ at a 0.8-V supply, of which only 30 $\mu \text{W}$ is due to the hybrid loop. At a 2.0-GHz output, the PLL exhibits a reference spur of −60.5 dBc and a jitter of 1.71 ps $_{rms}$ , resulting in state-of-the-art FoMR of −239.5 dB, and FoMNRA of −271.7 dB.

Purpose The purpose of this study is to develop an algorithm to accurately detect faults in series capacitor compensated (SCC) power transmission lines. The line fault must be distinguished from stable power swing, compensating unit malfunction and defects on other lines sharing the same bus (external faults). Design/methodology/approach In this regard, an effective fault feature extractor based on the cumulative sum (CUSUM) of the amplified second harmonic of the phase currents is suggested. The features are then applied to an artificial neural network for classification. No-fault cases include stable power swing and several disturbances. Due to the independent analysis of each phase, faulty phase detection is also a by-product. Findings Various fault scenarios are defined, and the algorithm success rate is compared with some newly published methods. Extensive simulations performed over a single-machine infinite bus, a 3-machine, 9-bus and the large-scale New England IEEE 39-Bus networks all indicate that the proposed algorithm can trip the faulty line more quickly and accurately than the contestant algorithms. Originality/value Suggestion of a new algorithm based on the CUSUM of the amplified second harmonic of the phase current for the fault feature extraction that is able to isolate the transmission line internal faults from stable poser swing, line compensating unit malfunction and faults on the adjacent lines connected to the same bus.

Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless injection timing is carefully controlled. This work investigates a behavioral model of the ILO with digital control of a bang-bang phase detector (BBPD) on a discrete-time domain, a quantitative analysis on the dynamics of the digital injection-locked clock multiplier (ILCM) is provided. Adjusting frequency error between the free-running oscillator and the injection signal is crucial to obtain better spur performance. However, the timing offset caused by the device mismatches hinders it from being correctly compensated. Therefore, we investigate the effect of timing offset (or mismatch) between the replica cells and BBPD and then propose the time-division dual calibration (TDDC) to reduce the discrepancies. In addition, three-stage replica cells are chosen to achieve a robust operation in the phase generating aspect. By removing the residual phase offset using multiple delay cells, the optimum locking point is guaranteed.

Made available in DSpace on 2022-05-01T07:58:42Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-01-01 The Phase-Locked Loops, conceived in the 1930’s by Henri de Bellescize, and used in a large scale on TV sets and integrated services digital telecommunication networks are nowadays increasing their relevance, being present in the time-basis generation and detection either in integrated circuits or in smart-grids power distribution systems. Among the Phase-Locked Loop architecture components is the Phase Detector. The phase detection function is a measure of phase/frequency errors in the Phase-Locked Loop, with analog, hybrid and digital implementations. In most of the classical literature the phase detection function is implemented by a signal multiplier device that can be approximated by a sine function from the phase error. Additional simplifications made on the phase detection function approximates the Phase-Locked Loop to a Düffing system. The phase detection function usually generates oscillations, such as the double-frequency jitter, which is a sinusoidal signal with the double of the synchronization frequency. Nowadays, software implementation allows a considerable flexibility to the phase detection function. Therefore, the phase detection requires accurate modeling to guarantee precision to the obtained clock signals. This work presents a performance comparison between the multiplier, the sine and the Düffing detectors. Polytechnic School University of São Paulo-USP Institute of Science and Technology São Paulo State University-UNESP Institute of Science and Technology São Paulo State University-UNESP

Made available in DSpace on 2022-05-01T06:31:27Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-01-01 The delay in signal transmission for oscillator networks influences in the synchronization, getting oscillatory behavior. The synchronization occurs by the phase-locked loops (PLL), synchronizing the local oscillator with a reference phase and frequency. The oscillators are implemented in data and telecommunications communication systems, as elements (nodes) for distribution of time signals (clock). In the work is implementated the time signal distribution network, with three nodes, in order to establish a common time base, with adjustment of disturbance in clock. The phase detection process generates a periodic oscillation called double-frequency jitter (DFJ). The DFJ is inevitable, appearing even with the PLL operating in the blocking range. Therefore, this work aims to study the effect of the double frequency oscillation on a network with signal transmission delay, its influence on the synchronous states of network, and the performance of oscillators to recover the common time base of clock, when disturbed. Institute of Sciente and Technology São Paulo State University-UNESP, Av. Três de Março 511 Fedeal University of ABC-UFABC, R. Arcturus 3 School of Engineering São Paulo State University-UNESP, Av. Eng. Luís Edmundo Carrijo Coube, 14-01 Institute of Sciente and Technology São Paulo State University-UNESP, Av. Três de Março 511 School of Engineering São Paulo State University-UNESP, Av. Eng. Luís Edmundo Carrijo Coube, 14-01

Gait phase detection is essential for the wearable powered exoskeletons. This paper proposes an online gait phase detection method based on dynamic time warping mean (DTW-MEAN) templates using ground contact forces (GCFs). There are two important methods of gait phase detection, which are the template matching and statistical method. Template matching methods such as DTW are robust and have been widely used in the field of gait phase detection. However, the template matching is a kind of method based on distance measure, and the gait phase detection will ignore the coupling connections between the gait sequences; on the contrary, the statistical method can fuse these connections well. In this paper, a statistical mean method based on DTW is proposed to solve the problem of recognizing phases between gait sequences that are not correctly detected by single template methods. We tested our approach in complex environment (such as different terrains, different payloads, and different speeds) and gained over 95% accuracy and time difference below 25ms. Our proposed approach obtained better detection results with the advantage of no need to retrain templates.

Fiber deformation measurement is crucial in the structure health monitor, which reflects the stress, strain or deformation of the structure where the fiber is laid. The principle of the fiber deformation measurement by the optical phase tracking in OFDR scheme is described and the data processing algorithm is demonstrated in details to receive accurate results. The differential phase is acquired by making a difference between the phase spectrum of the reference and measurement states. A robust phase unwrapping method based on the density distribution is proposed to get the whole unwrapped low-noise phase of the fiber. Additionally, the phase decoherence caused by the scatter unit misalignment induced by the fiber deformation is analyzed and the phase correction method is proposed to improve the phase coherence. The fiber deformation can be tracked along the fiber with a resolution of tens of microns, depending on the set parameters of the OFDR system. Moreover, the strain distribution is also derived from the differential phase. In the experiments, the measurements of the standard single-mode fiber with uniform and non-uniform deformation have been accomplished in a spatial resolution of 40 μm. The noise is about 0.1 μm in a stretching range of about 40 μm. Simultaneously, hundreds of microstrain are obtained and show a high accuracy with a resolution of the level of millimeter.

Three-phase inverters for grid-connected applications typically require some form of grid voltage phase detection in order to properly synchronize to the grid and control real and reactive power. This phase detection is usually based upon some type of grid voltage sensing. However, in this work, a method is proposed, whereby the phase angle of the grid can be accurately identified solely via the grid current feedback. In the proposed current-control scheme, the only measurement is the output inverter current, and no phase-locked loop (PLL) exists within the scheme. This phase observer is incorporated into a current controller, which can manage the injected power to the grid. The design of this combined observer/controller system is motivated and validated via a Lyapunov stability analysis. The performance of the proposed control scheme has been compared with the conventional PI PLL-based control scheme that needs both a grid voltage and a current sensors. Experimental results utilizing a Controller+ Hardware-in-the-Loop test bed have been presented in order to validate the proposed observer/controller scheme under normal operation, weak grid, distorted grid, and faulty grid conditions. To summarize, this scheme archives current control for a grid-connected inverter using only current feedback. In comparison, traditional methods require voltage and current feedback along with a PLL to synchronize with the grid creating a cascaded closed-loop control system.

This article presents the analytical modeling of synchronous class E rectifiers with the load-independent operation, which achieves zero-phase-angle input impedance, soft-switching over the entire load range with a constant voltage gain. The optimal design of the synchronous class E rectifier is proposed to realize both zero-voltage-switching turn- on and zero-current-switching turn- off at the expected output power. An $ LCC$ - $S$ compensated MHz-WPT topology, which comprises the push–pull class E inverter and rectifier with the load-independent operation, is proposed to achieve the fully soft-switching and a nearly constant voltage gain over the entire load range. The efficiency improvement of the compensation network is also investigated to provide a design methodology for the proposed topology. A $ 6.78$ -MHz WPT prototype, along with an alternative phase detector using an auxiliary coil to realize phase detection, is built to validate the analytical model and the proposed methodology. The system efficiency reaches $ \text{86.7}\%$ at $ 214$ -W output. The synchronous push–pull class E rectifier maintains soft-switching over the load range, and the rectification efficiency reaches $ 94.6\%$ .

The AC fault ride-through and support capability of line commutated converter based high voltage direct current (LCC-HVDC) have significant influence on the safe operation of power system. The ability of phase locked loop (PLL) to synchronize with the voltage phase under AC faults would affect the recovery performance of LCC-HVDC systems. This paper analyzes the influence of the conventional PLL on the subsequent commutation failure (SCF) of LCC-HVDC systems and points out that the conventional PLL has some problems such as slow dynamic response, significant frequency fluctuation, and coupling of phase and frequency detection under fault conditions. A novel PLL is proposed to address the problems. Cascade delayed signal cancellation operators are combined with a mathematical filter, forming a hybrid pre-filter to extract fundamental positive sequence voltage for the PLL. To reduce the fluctuation of PLL's frequency during AC faults, the estimated frequency is fixed when the fault is detected by a fault detector. As a consequence, the decoupling between phase detection and frequency detection is realized, and the proposed PLL's dynamic response performance is enhanced. Simulation results show that the proposed PLL can provide accurate phase reference for the DC control system and reduce the probability of SCFs of LCC-HVDC system.

Purpose The purpose of this paper is to present gait analysis for five different terrains: level ground, ramp ascent, ramp descent, stair ascent and stair descent. Design/methodology/approach Gait analysis has been carried out using a combination of the following sensors: force-sensitive resistor (FSR) sensors fabricated in foot insole to sense foot pressure, a gyroscopic sensor to detect the angular velocity of the shank and MyoWare electromyographic muscle sensors to detect muscle’s activities. All these sensors were integrated around the Arduino nano controller board for signal acquisition and conditioning purposes. In the present scheme, the muscle activities were obtained from the tibialis anterior and medial gastrocnemius muscles using electromyography (EMG) electrodes, and the acquired EMG signals were correlated with the simultaneously attained signals from the FSR and gyroscope sensors. The nRF24L01+ transceivers were used to transfer the acquired data wirelessly to the computer for further analysis. For the acquisition of sensor data, a Python-based graphical user interface has been designed to analyze and display the processed data. In the present paper, the authors got motivated to design and develop a reliable real-time gait phase detection technique that can be used later in designing a control scheme for the powered ankle-foot prosthesis. Findings The effectiveness of the gait phase detection was obtained in an open environment. Both off-line and real-time gait events and gait phase detections were accomplished for the FSR and gyroscopic sensors. Both sensors showed their usefulness for detecting the gait events in real-time, i.e. within 10 ms. The heuristic rules and a zero-crossing based-algorithm for the shank angular rate correctly identified all the gait events for the locomotion in all five terrains. Practical implications This study leads to an understanding of human gait analysis for different types of terrains. A real-time standalone system has been designed and realized, which may find application in the design and development of ankle-foot prosthesis having real-time control feature for the above five terrains. Originality/value The noise-free data from three sensors were collected in the same time frame from both legs using a wireless sensor network between two transmitters and a single receiver. Unlike the data collection using a treadmill in a laboratory environment, this setup is useful for gait analysis in an open environment for different terrains.

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of operation up to 30 GHz, and the dead zone equal to 1 ps. Compared to the conventional PFD based on CMOS technology, its dead zone and power consumption are lower. In addition, the effects of blocks’ parameters including the phase detector, which affect the operation of the phase locked loop, or delay locked loop, are systematically analyzed.

This brief presents an auxiliary feed-forward noise cancellation (AFFNC) technique that can be applied to a generic Type-II ring oscillator (RO) PLL. The AFFNC technique uses a stand alone sub-sampling phase detector (SSPD) embedded into an alignment loop to extract and cancel noise from the RO output. Along with AFFNC, which uses one reference edge for noise extraction, a Double Sampled AFFNC (DS-AFFNC) which utilizes both the rising and falling edge of the reference for noise extraction is also presented. By using both the reference edges, higher cancellation bandwidth is achieved in DS-AFFNC. The phase-domain model developed for AFFNC and DS-AFFNC show a 2.9x and 3.9x integrated jitter reduction respectively.

The satellite laser ranging method is based on measuring the transit time of a laser pulse from the transmitter to the satellite and back to the receiver. A special feature of the TPL telescope is that the laser signal is transmitted and received by the same telescope. This requires auxiliary equipment to separate these signals. In addition, this telescope is also used for visual tracking of the object, which adds complexity to the optical design. In most cases, the signals are separated mechanically using rotating mirrors. In one position, the mirrors transmit the signal to a specific channel, and they reflect the optical signal into another channel in the other position. The rotational speed of the mirrors corresponds to the frequency of the laser transmitter. Both mirrors rotate at the same frequency but with a different phase. A logic circuit built on two D-triggers and one 2-input NAND element is used as a phase detector. The paper discusses the scheme and principle of operation of the device for mirror synchronization by signals of the control computer and mirror position sensors. This device has been successfully used at the Riga-1884 laser location station of the University of Latvia.

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of -247dB, and normalized TR and area (FOMTA) of -262dB.

A new topology that generates a DC voltage whose value is depending on the phase difference of two input RF signals is presented. It is implemented by the mixer concept. With the use of microwave photonics, the mixer-based phase detector can be operated over a very wide frequency range. It also has the advantages of high phase detection resolution, small phase detection error, and small DC offset and phase offset. The phase detector can be constructed using off-the-shelf components including a single integrated optical modulator and a low-speed balanced detector. Measured results on the phase detector demonstrate a 0° to 180° RF signal phase difference detection range for 3.5 GHz to 18 GHz input RF signal frequencies, less than ±3° phase detection error and 2° phase detection resolution.

Frequency-modulated continuous-wave (FMCW) interference, as a new technology of laser interferometry, has the advantages of length traceability, large range, high accuracy, simple structure, and optical fiber transmission. Based on the formula of FMCW laser interference displacement, a zero-crossing phase detection algorithm is proposed, which can accurately calculate the initial phase of a cosine signal in a modulation period, and it is successfully applied to the contact laser interference displacement sensor. The experimental results show that the FMCW technology based on the zero-crossing phase detection algorithm can achieve the technical specifications of the contact displacement sensor with a measurement range greater than 15 mm and the standard deviation is less than 0.01 μm. The conversion of noncontact measurement to contact measurement can realize the direct measurement of workpieces with complex surface conditions on the production line, breaking through the limitation of optical measurement and expanding the application of optical fiber interferometry.

This paper analyses the noise performances of coupled phase-locked loops, providing closed-form expressions for the transfer functions of the various noise sources, and presents a novel coupling topology, whose goal is the reduction of both in-band and out-of-band phase-noise. The proposed circuit consists of two, or more, standard loops coupled via an additional phase detector. It will be demonstrated that in this architecture the impact of the main PLL noise sources, the oscillator and the reference buffer, is efficiently traded with the power dissipation without resorting to lossy and area-consuming passive coupling networks. The work then shows how to derive the set of design parameters that grant the desired performance for a given case study. The entire procedure is verified by simulations.

A sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be reduced. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm2. The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75 MHz and the output frequency range of the SSPLL is 2.4~3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from −71.4% to −18.5% at 3.0GHz.

In this article, a fractional- $N$ reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor-based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be effectively suppressed with the high-gain setting for the RSPD when the loop is in lock. The linear range of RSPD can be programmed to cover the quantization error in a frac- $N$ mode without degrading the PLL in-band phase noise. To mitigate the nonlinearity of RSPD, the CDAC is implemented with a high-order cancellation scheme using only one capacitor array but multiple reference voltages. The prototype chip was fabricated in a 45-nm partially depleted silicon-on-insulator (PDSOI) CMOS process. The measurement showed an output frequency range covering 7.7–9.1 GHz with an integrated jitter (10 kHz–50 MHz) of 135 fs and an in-band fractional spur level of −55 dBc at an offset frequency of 50 kHz. The entire PLL consumes 4.5 mW and achieves an figure of merit (FoM) of −250.8 dB.

A 180-GHz minimum shift keying (MSK) receiver (RX) using a phase-locked loop (PLL), which self-synchronizes the carrier frequency, is demonstrated. The mixer-first RX is fabricated in a 65-nm CMOS process. A double-balanced anti-parallel-diode-pair sub-harmonic mixer performs the phase detection, reducing the frequency of local oscillator (LO) by half. Tunable zeros realized by series inductors are used to improve the stability and to increase the data rate handling capability. Without external LO synchronization, the RX demodulates MSK signals at 10 Gb/s with a bit error rate (BER) $\times $ 10−5. The BER at 10 Gb/s is the lowest and the data rate of 12.5 Gb/s is the highest for PLL RXs.

In this article, we develop the theory of a special type of optoelectronic phase-locked loop (PLL). The output signal of this type of PLL is in the electrical domain and its reference oscillator, typically a mode-locked laser, operates in the optical domain. The PLL uses a balanced optical microwave phase detector (BOMPD). In order to model the optoelectronic PLL, the nonlinear characteristic function and the gain of the BOMPD are derived analytically. Using the results of the phase detector analysis, the theory of an optoelectronic PLL using such a phase detector is developed. Based on the theoretical analysis, a broadband optoelectronic frequency synthesizer with a programmable frequency range from 2 to 20 GHz is designed and implemented. Phase noise measurements show that the optoelectronic PLL frequency synthesizer achieves an integrated rms-jitter (1 kHz–100 MHz) of less than 4 fs in the frequency range from 5 to 20 GHz with a typical value of 4 fs and a minimum of 3 fs. This is the first reported wideband PLL frequency synthesizer achieving sub-10-fs integrated rms-jitter (1 kHz–100 MHz) in the frequency range from 3 to 20 GHz. A comparison with best-in-class laboratory-grade frequency synthesizers in this frequency range shows that this synthesizer achieves lower phase noise than any electronic frequency synthesizer for offset frequencies larger than 2 kHz.

Purpose A high-precision gyroscope is an important tool for accurate positioning, and the amplitude stability and frequency tracking ability of the drive control system are important and necessary conditions to ensure the precision of micro-electro-mechanical systems (MEMS) gyroscopes. To improve the precision of MEMS gyroscopes, this paper proposes a method to improve the amplitude stability and frequency tracking ability of a drive control system. Design/methodology/approach A frequency tracking loop and an amplitude control loop are proposed to improve the frequency tracking ability and amplitude stability of the drive control system for a MEMS gyroscopes. The frequency tracking loop mainly includes a phase detector, a frequency detector and a loop filter. And, the amplitude control loop mainly includes an amplitude detector, a low-pass filter and an amplitude control module. The simulation studies on the frequency tracking loop, amplitude control loop and drive control system composed of these two loops are implemented. The corresponding digital drive control algorithm is realized by the Verilog hardware description language, which is downloaded to the application-specific integrated circuits (ASIC) platform to verify the performances of the proposed method. Findings The simulation experiments in Matlab/Simulink and tests on the ASIC platform verify that the designed drive control system can keep the amplitude stable and track the driving frequency in real time with high precision. Originality/value This study shows a way to design and realize a drive control system for MEMS gyroscopes to improve their tracking ability. It is helpful for improving the precision of MEMS gyroscopes.

Phase rotator-based digital clock and data recovery (CDR) using multi-level bang-bang phase detector (ML-BBPD) and time to digital converter (TDC) is analyzed at system and circuit level. A model is proposed for calculating the quantization noise and bit error rate (BER), in order to evaluate the important parameters in CDR design. The jitter analysis is done based on the probability density function achieved from the quantization noise error of the BBPD and TDC. The analysis of ML-BBPD is shown that by increasing the number of sampling clocks, the quantization noise and consequently the jitter and BER are significantly reduced. Also, it is shown that by improving the resolution of the TDC and increasing number of delay cells for the purpose of keeping fixed the dynamic range, the output jitter of TDC is decreased. In the proposed model and also simulation, it is approved that by increasing the ratio of RMS input Gaussian jitter to the quantization step, the output jitter reaches to its saturated value. To prove the jitter model, the goodness of fit test based on Kolmogorov–Smirnov test is used and in addition, the simulation is provided for circuit level CDR. The circuit level simulation is done in TSMC 65 nm CMOS technology. The CDR is worked under 1 V supply voltage at 480Mbit/s bit rate useful for USB2 applications. The CDR dissipates 913 µW power and generates 0.258 ps RMS jitter, while it occupies 166 µm × 104 µm chip area.

Step detection is very important for the foot-mounted Pedestrian Dead Reckoning (PDR) system. To deal with the false detection caused by variant stepping modes and occasional disturbance, a novel robust step detection algorithm is proposed. The proposed algorithm detects the number of steps and zero-velocity phase using data from inertial sensors mounted on the user’s foot. It includes two parts: a novel anti-fault detection algorithm and a novel zero-velocity detection method, which are used to reduce the over-detection and miss-detection of steps, respectively. Field tests show that the proposed approach is robust under varying motion speeds in different step modes for different persons and the average accuracy of the proposed algorithm is 99.94% in all motion modes, which significantly exceeds conventional estimation approaches in terms of step detection accuracy.

Objectives: To design and develop a simple, robust, and novel SOGI based frequency lock loop approach with DC-offset elimination capability for extracting precise phase angle of the grid voltage. As the additional objective of the work is to utilize the unused capacity of the PV system for providing reactive power support to the grid. Method: The second-order generalized integrator (SOGI)-Frequency Look loop (FLL) is implemented to achieve precise phaseangle for the control system, filtering capability for the adaptive frequency tuning as well as an orthogonal signal generation. The DC blocker is designed to eliminate the dc-offset generated during analog to digital conversion without compromising the dynamics of the system. To achieve the second objective, the virtual two-axis current control is simulated and experimented on in a single-phase grid-assisted system. Synchronous-frame current controllers are designed to inject active power to the grid and also ensure the unity power factor by providing reactive power support to the grid. The developed system is simulated using MATLAB /Simulink and implemented on the experimental stepup. Findings: The precise phase-angle is extracted from the grid voltage during the abnormal grid conditions like frequency shift, distorted by harmonics, and dc-offset. The DC-offset can be eliminated without adopting high-order FLLs by choosing the appropriate control parameter and DC cancellation block (DBC). Novelty: This study presents simple, efficient, novel SOGI based control that provides assurance of power quality as well as injection of active power injection into the grid using the virtual two-axis reference frame power control. The experimental and simulation results confirm that the presented control approach provides fast and accurate phase angle extraction in the grid synchronization with DC-offset cancellation. Keywords: Grid synchronization; STM32F407VG microcontroller; WAIJUNG Blockset; phase detection; Phase Locked Loop (PLL); virtual two axis reference frame power control

Gait phase analysis is widely used in disease diagnosis, rehabilitation training, and other fields by studying the characteristics of human gait. It systematically evaluates human body’s skeletal muscles and nerves with combined disciplines. Microelectromechanical system (MEMS) inertial sensors are extensively used in attitude detection because of its high-precision, portability, and good real-time performance in time-domain analysis. In this article, we presented a multi-degree-of-freedom MEMS gait detection method, which resolved the problems of single sensor and limited gait phase. We designed a sensor-based gait signal acquisition system, in which gait data acquisition program and feature analysis algorithm were compiled to verify the feasibility of the proposed method. We performed coordinate transformation and corrected position information to eliminate the gait phase detection error caused by random noise interference. Acceleration and angular velocity information were collected from 20 experimenters. We applied an adaptive threshold gait phase detection algorithm to classify the gait information collected by single sensor. To improve the results of gait phase classification, we used multisensor redundant measurement to analyze characteristics of five gait phases. The acceleration and angular velocity information collected by the three sensors placed at instep, ankle, and thigh were input into support vector machine (SVM). The classification results of the five gait phases are approximately 90%. Lastly, we built a human body structure model to simulate human motion in real time, realizing the real-time gait phase detection, which proves effectiveness of the proposed algorithm.

In this paper, a novel closed-loop synchronization algorithm is proposed based on the linear phase angle detection. The linear phase detection is performed by the inverse tangent (atan2) trigonometric function, while the frequency tracking is performed by a proportional-integral (PI) loop filter and phase integrator. By using the linear phase detection, the linear phase-locked loop (PLL) is employed, which is simpler to implement and to tune, and which also performs better for large frequency and phase variations when compared to conventional PLL algorithms. Also, the novel technique operates consistently for a whole range of designated PLL crossover frequencies when compared to existing PLL techniques, which makes it a better candidate when higher filtering is required of higher harmonics and measurement noise. When compared with existing algorithms that use atan function for phase angle estimation, the novel algorithm enables the frequency estimation that does not include differentiation, which improves the resulting algorithm immunity to measurement noise and higher harmonics. The novel PLL is tested by simulation and experimental runs.