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We introduce an architecture for a programmable IEEE 802.11ah Wi-Fi modem based on a new Cadence Xtensa-based low-energy DSP. The design is based on a methodology for partitioning the system into hardware and software components that takes into account power consumption, silicon area and the need for programmability. Physical layer software functions avail the DSP's extensible architecture options for baseband processing, such as complex signal filtering and FFT acceleration instructions. We provide sensitivity data from software simulations and laboratory tests that demonstrate the modem is capable of reliable detection and decoding of 2MHz packets with −107dBm of received signal power. Additionally, we analyze latency requirements for a System-on-Chip (SoC) design.