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Background: Low grade of sterile inflammation plays detrimental roles in the progression of diabetic kidney disease (DKD). Sappanone A (SA), a kind of homoisoflavanone isolated from the heartwood of Caesalpinia sappan, exerts anti-inflammatory effects in acute kidney injury. However, whether SA has beneficial effects on diabetic kidney disease remains further exploration.Methods and Results: In the present study, uninephrectomized male mice were treated with Streptozotocin (STZ, 50 mg/kg) for five consecutive days to induce diabetes. Next, the diabetic mice were administered orally with SA (10, 20, or 30 mg/kg) or vehicle once per day. Our results showed that STZ treatment significantly enhanced damage in the kidney, as indicated by an increased ratio of kidney weight/body weight, elevated serum creatinine and blood urea nitrogen (BUN), as well as increased 24-h urinary protein excretion, whereas SA-treated mice exhibited a markedly amelioration in these kidney damages. Furthermore, SA attenuated the pathological changes, alleviated fibrotic molecules transforming growth factor-β1 (TGF-β1) and Collagen-IV (Col-IV) production, decreased inflammatory cytokines interleukin-1β (IL-1β) and tumor necrosis factor-α (TNF-α) expression in STZ-treated mice. Similarly, in glomerular mesangial cells, SA pretreatment decreased high glucose (HG)-induced proliferation, inflammatory cytokines excretion, and fibrotic molecules expression. Mechanistically, SA decreased the expression of nuclear factor kappa B (NF-κB) and restored the expression of total NF-κB inhibitor alpha (IκBα) both in vivo and in vitro.Conclusion: Our data suggest that SA may prevent diabetes-induced kidney inflammation and fibrosis by inhibiting the NF-κB pathway. Hence, SA can be potential and specific therapeutic value in DKD.

A second-order dynamic phase transition in a non-equilibrium Eggers urn model for the separation of sand is studied. The order parameter, the susceptibility and the stationary probability distribution have been calculated. By applying the Lee-Yang zeros method of equilibrium phase transitions, we study the distributions of the effective partition function zeros and obtain the same result for the model. Thus, the Lee-Yang theory can be applied to a more general non-equilibrium system.

In this paper, a novel approach to automatic SAR image registration is proposed. First, the bi-temporal images are decomposed by wavelet transform. Then, the sensed image and its wavelet approximation component are divided to some saliency region based on spectrum residua approach. And the saliency regions are fitted into ellipses. Finally, the region matching is performed by searching the corresponding regions in the reference image at every layer by the comprehensive learning particle swarm optimization (CLPSO) twice. Thus, the registration in every layer is a coarse-to-fine process, which effectively improves the efficiency, accuracy and stability. The proposed technique is validated by testing on real SAR images and compared with existing state-of-the-art techniques.

Automatic decomposition is an optimization technique that distributes computation and data onto different processors. The consequence of decomposition directly affects the performance of parallel program. Since every computing node has its own memory in distributed memory parallel computers (DMPCs), false dependence does not hinder the parallelism. Affine decomposition is an effective method to represent and derive computation partition and data distribution, and its principle of adding dependence constraint is too strict to gain more parallelism. Some loop nests do not satisfy the affine condition, and are prohibited from parallelism by affine decomposition. However, if only the irregular access is caused by indirect array, loop and array reference can be partitioned at compile time. To tackle above problems of affine decomposition, an improved static decomposition algorithm of DMPCs proposed in this paper. The experimental results show that this algorithm can improve the performance of parallel programs.

In high speed three-dimensional integrated circuits (3D ICs), through silicon via (TSV) insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.

Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design of nano-scale integrated circuits.

Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, in which a non-uniform interconnection structure is adopted. This model takes into account the self-heating effect and is constrained by delay, bandwidth, area, minimum interconnect width and minimum interconnect space. The validity of the proposed model is verified by 90 nm and 65 nm complementary metal-oxide semiconductor technology. The results indicate that the proposed model can cause a power consumption reduction as high as 35%, and yet the delay, area, and bandwidth are not deteriorated, when compared with the conventional power model. The proposed optimal model can be used for designing large scale interconnect router and clock network in network-on-chip structure.