Search

Supplementary Material 1

Network-on-chip (NoC) provides a structured way of realizing interconnections on silicon for highly parallel SoC with many processing cores, which forces a communication-centric, as opposed to a computation-centric, design view. Thus, the choice, modeling and simulation of current rich types of communicators are essential for accurate evaluation and optimization of the overall performance of a NoC. In this paper, we present a SystemC-based NoC simulation and evaluation framework which can support most of current communicators. This framework is initially developed for our NoC architecture, called "CHNoC - cluster-based hierarchical NoC". Several adaptation and interfacing techniques are described, including the proposed convergent interface (CI) which decouples communication from computation and interfaces mixed abstraction levels. The designer can easily explore, evaluate and compare a wide range of NoC solutions in different abstraction levels, with a very limited effort to integrate various communicators with proposed framework