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We propose a compact single-flux-quantum (SFQ) lookup table (LUT) that uses CMOS decoder circuits for reconfiguration to improve scalability. Reconfiguration by external control currents. An n×n -bit LUT is composed of a two-dimensional array of memory cells and cryo-CMOS decoders. The memory cell at the target address is set to a logic “1” state when the corresponding x - and y -directional control currents are both applied from the CMOS decoders and is reset to logic “0” when a reset current is applied. Cryo-CMOS decoders are integrated with the SFQ LUT to reduce the number of control current lines (from 2 n +1 to 2log 2 n +2) from the room-temperature electronics for LUT reconfiguration. For demonstration, we designed and fabricated a 64-b SFQ LUT integrated with CMOS decoders using the AIST 2.5-kA/cm 2 Nb standard process and the Rohm 180-nm CMOS process. Experimental results confirm the correct functionality of the SFQ LUT reconfigured by the CMOS decoders. All operating SFQ memory cells in the experiment showed almost the same control current margins. The proposed reconfiguration method is scalable in terms of the number of interconnections and control current margins for SFQ memory cells.

This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology. The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN). Peer Reviewed Article signat per 43 autors/es: Guillem Cabo∗, Gerard Candón∗, Xavier Carril∗, Max Doblas∗, Marc Domínguez∗, Alberto González∗, Cesar Hernández†, Víctor Jiménez∗, Vatistas Kostalampros∗, Rubén Langarita∗, Neiel Leyva†, Guillem López-Paradís∗, Jonnatan Mendoza∗, Francesco Minervini∗, Julian Pavón∗, Cristobal Ramírez∗, Narcís Rodas∗, Enrico Reggiani∗, Mario Rodríguez∗, Carlos Rojas∗, Abraham Ruiz∗, Víctor Soria∗, Alejandro Suanes‡, Iván Vargas∗, Roger Figueras∗, Pau Fontova∗, Joan Marimon∗, Víctor Montabes∗, Adrián Cristal∗, Carles Hernández∗, Ricardo Martínez‡, Miquel Moretó∗§, Francesc Moll∗§, Oscar Palomar∗§, Marco A. Ramírez†, Antonio Rubio§, Jordi Sacristán‡, Francesc Serra-Graells‡, Nehir Sonmez∗, Lluís Terés‡, Osman Unsal∗, Mateo Valero∗§, Luís Villa† // ∗Barcelona Supercomputing Center (BSC), Barcelona, Spain. Email: name.surname@bsc.es; †Centro de Investigación en Computación, Instituto Politécnico Nacional (CIC-IPN), Mexico City, Mexico; ‡ Institut de Microelectronica de Barcelona, IMB-CNM (CSIC), Spain. Email: name.surname@imb-cnm.csic.es; §Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. Email: name.surname@upc.edu

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Postlayout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74- $\mu \text{W}$ power consumption for the high-speed design and a maximum frequency of 10 GHz with 53- $\mu \text{W}$ power consumption for the minimum PDP design.

The fast settlement of privacy and secure operations in the Internet of Things (IoT) is appealing in the selection of mechanisms to achieve a higher level of security at minimum cost and with reasonable performances. All these aspects have been widely considered by the scientific community, but more effort is needed to allow the crypto-designer the selection of the best style for a specific application. In recent years, dozens of proposals have been presented to design circuits resistant to power analysis attacks. In this paper, a deep review of the state of the art of gate-level countermeasures against power analysis attacks has been carried out, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison. Advantages and drawbacks of the proposals are analyzed, showing quantified data for cost, performance (delay and power), and security when available. One of the main conclusions is that the RSL proposal is the best in masking, while TSPL, HDRL, SDMLp, 3sDDL, TDPL, and SABL are those with the best security performance figures. Nevertheless, a wise combination of hiding and masking as masked_SABL presents promising results.

In this paper, the PAELib - an occupied area and power dissipation estimation library written in VHDL - and its use cases are presented. Estimates are based on the structural description of a CMOS digital circuit made with gates/components included in the library; they can be achieved with systematic accounting of leaf components in the structural description. The advantage of this library is that it obtains occupied area and power dissipation estimates using a logic simulator, rather than specialized circuit synthesis or power simulation/estimation software. To validate the library, two use cases are presented. In the first use case, the power dissipation of a 5-stage ring oscillator - implemented with logic gates from the CD4000 series - is estimated and a power estimation error of 16% was obtained. In the second use case, a designer must choose between two implementations of the same finite state machine: one implemented with 74HC series binary counter and the other with D flip flops from the same logic family. The answer is not an obvious one, but the PAElib can offer estimates in an early design stage, allowing the designer to take an informed design decision based on circuit power and area estimates.

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison. Published version

Alternatives to CMOS logic circuit implementations are under research for future scaled electronics. Memristor crossbar-based logic circuit is one of the promising candidates to at least partially replace CMOS technology, which is facing many challenges such as reduced scalability, reliability, and performance gain. Memristor crossbar offers many advantages including scalability, high integration density, nonvolatility, etc. The state-of-the-art for memristor crossbar logic circuit design can only implement simple and small circuits. This paper proposes a mapping methodology of large Boolean logic circuits on memristor crossbar. Appropriate place-and-route schemes, to efficiently map the circuits on the crossbar, as well as several optimization schemes are also proposed. To illustrate the potential of the methodology, a multibit adder and other nine more complex benchmarks are studied; the delay, area and power consumption induced by both crossbar and its CMOS control part are evaluated.

In a CNN (convolutional neural network) accelerator, to reduce memory traffic and power consumption, there is a need to exploit the sparsity of activation values. Therefore, some research efforts have been paid to skip ineffectual computations (i.e., multiplications by zero). Different from previous works, in this paper, we point out the similarity of activation values: (1) in the same layer of a CNN model, most feature maps are either highly dense or highly sparse, (2) in the same layer of a CNN model, feature maps in different channels are often similar. Based on the two observations, we propose a block-based compression approach, which utilizes both the sparsity and the similarity of activation values to further reduce the data volume. Moreover, we also design an encoder, a decoder and an indexing module to support the proposed approach. The encoder is used to translate output activations into the proposed block-based compression format, while both the decoder and the indexing module are used to align nonzero values for effectual computations. Compared with previous works, benchmark data consistently show that the proposed approach can greatly reduce both memory traffic and power consumption.

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

178 p. La forma en que funciona la red eléctrica no ha cambiado mucho desde su creación en la década de 1930, los métodos y medios de transmisión de los datos siguen siendo similares. Aunque la infraestructura general permanece inalterada, algunas tecnologías han cambiado desde entonces, y el ritmo de cambio ha aumentado significativamente en la última década. Por ejemplo, la introducción de las Tecnologías de la Información y las Comunicaciones (TICs) en la operación de las redes eléctricas ha dado como resultado una red compleja denominada Smart Grid. En términos generales, el sistema eléctrico actual consiste en una compleja red en la que están interconectadas las centrales eléctricas, la infraestructura de transporte de electricidad, la infraestructura de distribución, y la carga.Desde un punto de vista tecnológico, la Smart Grid puede ser vista como una superposición de una red de comunicación sobre la red eléctrica. La red de comunicaciones de la Smart Grid es un tipo de red capaz de proporcionar servicios avanzados, como el envío de datos de sensores en tiempo real, la redundancia y la ciber-seguridad. Se implementa utilizando una variedad de tecnologías de redes y medios de comunicación, incluyendo el mismo cableado eléctrico, redes inalámbricas y otras infraestructuras de comunicaciones existente, como las redes Ethernet basadas en cables de cobre o fibra óptica. Existen ventajas y desventajas asociadas a cada opción y es probable que los tres enfoques puedan utilizarse para las comunicaciones en la Smart Grid. Como resultado, las redes mencionadas se integran finalmente en el sistema, lo que obliga a que los equipos utilizados para gestionar las comunicaciones sean completamente heterogéneos. Por ello, desde una perspectiva global que favorezca la interoperabilidad, es imprescindible disponer de dispositivos de comunicaciones que combinen requisitos de procesamiento en tiempo real, sincronización avanzada, alta disponibilidad en las comunicaciones, reconfigurabilidad y ciber-seguridad. Estos dispositivos se conocen comúnmente como Cyber Physical System (CPS).A modo de resumen, un CPS típico se compone de varios dispositivos conectados a través de redes cableadas e inalámbricas. Estos dispositivos abarcan desde plataformas embebidas, sistemas en tiempo real, sensores y actuadores, hasta dispositivos en red. Por lo tanto, los CPS se benefician de los continuos desarrollos de nuevas plataformas de computación y sensórica de bajo coste, las comunicaciones inalámbricas, las redes de comunicación de gran ancho de banda y sistemas que permiten realizar una gestión más eficiente de la energía de los dispositivos.La propuesta de investigación presentada en esta tesis busca realizar contribuciones en el campo de los sistemas embebidos, planteando una arquitectura común de nodos que sirva como referencia de arquitectura CPS para la Smart Grid. Esta arquitectura deberá dar solución a la integración directa de los nodos en la red, permitiendo a su vez procesamiento en tiempo real, necesario en ciertas secciones y operaciones de la Smart Grid.En primer lugar, se presentará una visión general de la red eléctrica actual (Smart Grid). En particular, se describirá los elementos fundamentales de una subestación, y se presentará los estándares de comunicación utilizados para garantizar y satisfacer los requisitos de interoperatividad que deben cumplir las redes de transmisión y distribución modernas. A continuación, se describirán los requisitos y las características de funcionamiento que debe cumplir un dispositivo CPS Gateway para poder ser utilizado en la red eléctrica inteligente. Por otra parte, se definirá un CPS y se describirán sus partes, características y campos de aplicación. A continuación, se realizará un estudio detallado de varias arquitecturas existentes que representan ventajas significativas para su utilización en la Smart Grid. En segundo lugar, se propondrán arquitecturas CPS Gateway sobre plataformas reconfigurables System-on-Chip que garantice procesamiento en tiempo real, necesario en ciertas secciones y operaciones de la Smart Grid. También, deberá incorporar mecanismos avanzados de sincronización, comunicaciones de alta disponibilidad mediante comunicaciones redundantes, compatibilidad con la infraestructura de automatización de subestaciones actualmente en fase de despliegue (IEC 61850) y ciber-seguridad para las tramas SV y GOOSE.Para finalizar, el dispositivo Zynq de Xilinx será utilizado como plataforma de validación de las arquitecturas propuestas. La última parte de la tesis, describirá el hardware utilizado para realizar los experimentos. A continuación, se describirán los experimentos realizados para validar las arquitecturas. En este sentido, se implementarán tres arquitecturas para verificar el funcionamiento del CPS Gateway. La primera arquitectura, tendrá como finalidad validar los requisitos de sincronización, interoperabilidad y alta disponibilidad. En la segunda arquitectura se implementará un protocolo y un módulo de comunicaciones que permita la configuración remota del CPS Gateway. Finalmente en la tercera arquitectura se propondrá el uso de cifrado simétrico como mecanismo de ciber-seguridad para las tramas SV y GOOSE.

213 p. Las FPGAs (Field-Programmable Gate Array) y los SoC (System-on-chip) basados en FPGA son dispositivos electrónicos configurables en campo (in field), que ofrecen la posibilidad de desarrollar un circuito a medida con un tiempo de salida al mercado y unos costes de diseño reducidos en comparación con los ASICs. Debido a la reducción continua del tamaño de los transistores, las prestaciones de estos dispositivos se están incrementando de manera vertiginosa en las últimas décadas, lo que ha generado interés en sectores muy específicos como automoción, ferroviario, industrial, aviónico o aeroespacial. En estos sectores se exige que los diseños estén orientados a confiabilidad y que cumplan con diversas normativas de seguridad, lo que requiere de métodos para la estimación y justificación de la tasa de fallos del sistema. El problema radica en que las FPGAs son especialmente susceptibles al SEU (Single Event Upset) generado por radiación en la memoria de configuración, un tipo de error que provoca la modificación aleatoria de uno o más bits de dicha memoria, afectando al circuito implementado. Por lo tanto, los diseños orientados a confiabilidad que utilicen FPGAs comerciales han de considerar la inclusión de una serie de medidas y mecanismos para mitigar sus efectos. No solo eso, sino que también es necesaria la aplicación de mecanismos de evaluación para corroborar que las estrategias aplicadas permiten alcanzar los objetivos de confiabilidad. De entre los diferentes procedimientos de evaluación aplicables se destaca la emulación de SEUs, que consiste en programar el dispositivo con un archivo intencionadamente corrompido para que se almacene contenido erróneo en la memoria de configuración, lo que genera un efecto análogo al SEU. Se han estudiado diferentes metodologías de emulación en la literatura y se han observado una serie de deficiencias. Por un lado, los métodos de emulación internos (los errores se inyectan desde la propia FPGA) tienen el problema de ser autobloqueantes, ya que el error inyectado puede afectar al propio sistema de emulación. Por otro lado, los sistemas de emulación externos pueden requerir cambios importantes a nivel de hardware.El objetivo principal de este trabajo es el desarrollo de un mecanismo de emulación de SEUs que pueda implementarse de manera sencilla en sistemas ya construidos, cuyo único requisito es que dicho sistema tenga un SoC FPGA del tipo Zynq o similar. Además, se pretenden solventar las deficiencias observadas en la literatura aprovechando las diferentes capacidades que ofrecen los SoCs que combinan FPGA y sistema procesador (PS). Para ello se ha planteado la implementación del sistema de inyección de errores en el PS, ya que de esta manera se previenen las inyecciones de errores bloqueantes. De igual modo, aunque las inyecciones de realicen desde fuera de la FPGA, las inyecciones se llevan a cabo desde el interior del propio chip, evitando la necesidad de añadir modificaciones en el hardware. Se ha propuesto un esquema de verificación universal independiente de la aplicación, de modo que el esquema de test pueda ser adaptado a diferentes sistemas de forma sencilla, independientemente de su complejidad.Una vez planteada la metodología de emulación, se han realizado otras dos aportaciones. En primer lugar se ha comprobado cómo afectan las diferentes decisiones que puedan tomarse en las diferentes etapas de la fase de diseño. Aquí se ha comprobado que un mismo diseño puede tener fluctuaciones de hasta el 50\% si se modifican algunos parámetros. Por otro lado, habiendo observado que los emuladores de SEU existentes en la literatura se centran en el estudio del SBU (Single Bit Upset), se ha propuesto un procedimiento para la estimación de la tasa de fallo en presencia de MCUs (Multiple Cell Upsets).

2019 International Conference on High Performance Computing and Simulation (2019 : Dublin; Ireland), This paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) architecture of FPGAs. To achieve significant throughput for the search operation on BST, we present several novel mechanisms including tree duplication as well as horizontal, duplicated, and hybrid (horizontal-vertical) tree partitioning. Also, we present efficient techniques to decrease the stalling rates that can occur during the parallel tree search. By combining these techniques and implementations on Xilinx Virtex-7 VC709 platform, we achieve up to 8X throughput improvement gain in comparison to the baseline implementation, i.e., a fully-pipelined FPGA-based accelerator. © 2019 IEEE.

This paper presents the design and implementation of a high-level test bench for high-speed multi-FPGA pipelines, to model and simulate architectures that gather and process large amounts of data. The test bench was successfully employed in a nuclear particle detector system, forming part of a large physics experiment. The design under test consists of three main stages. The first stage simulates the acquisition of the analog input data, providing designers with a means to verify correct operation with unlimited input variation, be it actual or generated data. The second stage, which contains multiple hierarchies of FPGAs, comprises the actual detector firmware design. The last stage is divided into two modules: data acquisition and triggering, which are based on non-synthesizable VHDL features. The simulated system has been verified against the provided technical documentation. Each module was individually tested; subsequently, integration testing of the entire pipeline was carried out to ascertain its physical correctness across design corners. The upfront costs in terms of time and resources required to set up the environment are outweighed by the benefits of having such a system, which range from the scalability, predictability and manageability of modular systems to overcome the associated limitations of high-speed synthesis and instrumentation. Hence, factoring high-level test benches in the design pipeline becomes not just an asset but an invaluable tool for the optimization, testing and verification of complex high-speed designs., peer-reviewed

We propose a technique for the analysis of manufacturing yield of nano-crossbar architectures for different values of defect percentage and crossbar-size. We provide an estimate of the minimum-size crossbar to be fabricated wherein a defect-free crossbar of a given size can always be found with a guaranteed yield. Our technique is based on logical merging of two defective rows (or two columns) that emulate a defect-free row (or column). Experimental results show that the proposed method provides higher defect-tolerance compared to that of previous techniques.

We present a translation from programs expressed in a functional IR into dataflow networks as an intermediate step within a Haskell-to-Hardware compiler. Our networks exploit pipeline parallelism, particularly across multiple tail-recursive calls, via non-strict function evaluation. To handle the long-latency memory operations common to our target applications, we employ a latency-insensitive methodology that ensures arbitrary delays do not change the functionality of the circuit. We present empirical results comparing our networks against their strict counterparts, showing that nonstrictness can mitigate small increases in memory latency and improve overall performance by up to 2x.

Special Issue: 99; International audience; This paper addresses the important issue of fault tolerance in network-on-chip (NoC) and presents an on-the-field test and configuration infrastructure for a 2-D-mesh NoC, which can be used in many generic shared-memory many-core tiled architectures and MPSoCs. This paper also details all the hardware and software means needed to: 1) initialize the NoC in a clean state (self-deactivation of faulty NoC components using a controlled built-in self-test strategy) and 2) set up a distributed collaborative configuration infrastructure that can be used to make the chip autonomously determine, during its initialization, the operational degraded architecture, identify and bypass black holes. Experimental results prove that the approach is effective and lightweight in terms of additional software and hardware resources.

Superconducting Single-Flux-Quantum (SFQ) devices have been paid much attention as alternative devices for digital circuits, because of their high switching speed and low power consumption. For large-scale circuit design, the role of computer-aided design environment is significant. As the characteristics of the SFQ devices are different from conventional devices, a new design environment is required. In this paper, we propose a new timing-aware circuit description method which can be used for SFQ circuit design. Based on the description and the dedicated algorithms we have been developing for SFQ logic circuit design, we propose an integrated design flow for SFQ logic circuits. We have designed a circuit using our developed design tools along with the design flow and demonstrated the correct operation. key words: single-flux-quantum circuit, design methodology, circuit description, logic design, layout design, design verification

Commonly used in software design, assertions are statements placed into a design to ensure that its behavior matches that expected by a designer. Although assertions apply equally to hardware design, they are typically supported only for logic simulation, and discarded prior to physical implementation. We propose a new hardware design language-agnostic language for describing latency-insensitive assertions and novel methods to add such assertions transparently to an already placed-and-routed circuit without affecting the existing design. We also describe how this language and associated methods can be used to implement semi-transparent exception handling. The key to this paper is that by treating hardware assertions and exceptions as being oblivious or less sensitive to latency, assertion logic need only use spare FPGA resources. We use network-flow techniques to route necessary signals to assertions via spare flip-flops, eliminating any performance degradation, even on large designs (92% of slices in one test). Experimental evaluation shows zero impact on critical-path delay, even on large benchmarks operating above 200 MHz, at the cost of a small power penalty.

The paper presents a first effort at exploring a novel area in the domain of asynchronous controllers: specification mining. Rather than synthesizing circuits from specifications, we aim at doing reverse engineering, i.e., discovering safe specifications from the circuits that preserve a set of pre-defined behavioral properties (e.g., hazard freeness). The specifications are discovered without any previous knowledge of the behavior of the circuit environment. This area may open new opportunities for re-synthesis and verification of asynchronous controllers. The effectiveness of the proposed approach is demonstrated by mining concurrent specifications (Signal Transition Graphs) from multiple implementations of 4-phase handshake controllers and some controllers with choice.

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept., This work was supported by the Spanish MEC and MICINN, as well as by the European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009- 14475-C04. This work was supported in part by the Project NaNoC (Project Label 248972) which is funded by the European Commission within the Research Programme FP7. This paper was recommended by Associate Editor L. P. Carloni.

State encoding is one of the most difficult problems in the synthesis of asynchronous controllers. This paper presents a method that can solve the problem of large controllers specified with signal transition graphs. The method is based on the structural theory of Petri nets and uses integer-linear programming to insert state signals in locations that guarantee the consistency and absence of critical races. The structural nature of the proposed method makes it conservative, i.e., a solution cannot be guaranteed, even if it exists. Nevertheless, the experiments show that this limitation did not preclude finding a solution for all the examples presented in this paper. The method can be customized for area or delay optimization. The experimental results confirm the quality of the circuits, as compared with state-based methods. They also show the significant benefits that could be obtained if logic synthesis would be incorporated in synthesis frameworks that generate controllers by syntax-directed translation.

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2m). These properties are related to the parity of the binary representation of the elements of the Galois field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.

To enhance the efficiency of numerical control machines for cutting of sheet material, a method of searching for the cutter trajectory as a path with ordered enclosing in the flat graph G = (V, E) corresponding to the cutting design is proposed. It is shown that this path can be represented as a sequence of no more than n/2 + 1 chains with ordered enclosing, where n is the number of odd-order vertices in G. An algorithm for finding the sought sequence of chains, with a complexity of O(|E|) is developed. © Nauka/Interperiodica 2007.

Thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based Field Programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of highly reliable systems. In this context, Dynamic Partial Reconfiguration (DPR) is far from being widely adopted due to the additional complexity introduced during the hardware design phase, and the dependability issues related to the FPGA reconfiguration process itself. This paper presents a portable open-source controller for safely enabling self dynamic and partial reconfiguration of systems implemented on Xilinx FPGAs. The controller embeds configurable error detection and correction circuitry that enables a safe DPR by monitoring for partial bitstreams data errors. Experiments highlight the high performances achieved and the limited hardware resources needed to implement it on different devices. The HDL source code has been made available through the popular open-source Cobham Gaisler GRLIB IP-cores library.

Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitude.

The classical multivariable Smith delay compensator is extended to multivariable non-square systems with multiple time delays where there is more number of inputs than the outputs. For the delay compensated system, centralized multivariable PI controllers are designed by an extended version of Davison method with a pseudo inverse for the steady-state gain matrix. A method is proposed to select the two tuning parameters in Davison method. To show the improvement, PI controllers for the uncompensated system are also designed by the Davison method. The proposed method is applied to shell standard control problem (3 input and 2 output) and hot oil fractionator (4 input and 2 output). Simulation studies are carried out for both servo and regulatory problems. Robustness studies are carried out for uncertainty in all the process model parameters. The performance of the multivariable delay compensated system with the centralized PI controllers is improved by 25-35% when compared to that of the multivariable control system without any delay compensator. It is also shown that the performance and robustness of the delay compensator are significantly better for the non-square systems than that of the squared down systems. � 2006 Elsevier Ltd. All rights reserved.

The design and development of the neural network (NN)-based controller performance for the activated sludge process in sequencing batch reactor (SBR) is presented in this paper. Here we give a comparative study of various neural network (NN)-based controllers such as the direct inverse control, internal model control (IMC) and hybrid NN control strategies to maintain the dissolved oxygen (DO) level of an activated sludge system by manipulating the air flow rate. The NN inverse model-based controller with the model-based scheme represents the controller, which relies solely upon the simple NN inverse model. In the IMC, both the forward and inverse models are used directly as elements within the feedback loop. The hybrid NN control consists of a basic NN controller in parallel with a proportional integral (PI) controller. Various simulation tests involving multiple set-point changes, disturbances rejection and noise effects were performed to review the performances of these various controllers. From the results it can be seen that hybrid controller gives the best results in tracking set-point changes under disturbances and noise effects. � Springer-Verlag 2005.

A pipelined circuit to calculate linear regression is presented. The proposed circuit has the advantages that it can process a continuous flow of data, it does not need memory to store the input samples and supports variable length that can be reconfigured in run time. The circuit is efficient in area, as it consists of a small number of adders, multipliers and dividers. These features make it very suitable for real-time applications, as well as for calculating the linear regression of a large number of samples.

A central geometric structure in applications such as robotic path planning and hidden line elimination in computer graphics is the visibility graph. A new parallel algorithm to construct the reduced visibility graph in a convex polygonal environment is presented in this paper. The computational complexity is O(p2log(n/p)) where p is the number of objects and n is the total number of vertices. A key feature of the algorithm is that it supports easy mapping to hardware. The algorithm has been simulated (and verified) using C. Results of hardware implementation show that the design operates at high speed requiring only small space. In particular, the hardware implementation operates at approximately 53 MHz and accommodates the reduced visibility graph of an environment with 80 vertices in one XCV3200E device. ? 2004 Elsevier B.V. All rights reserved.

Binary decision diagrams (BDDs) are commonly used for handling Boolean functions because of their excellent efficiency in terms of time and space. However, the conventional BDD manipulation algorithm is strongly based on the hash table technique, so it always encounters the memory overflow problem when handling large-scale BDD data. This paper proposes a new streaming BDD manipulation method that never causes memory overflow or swap out. This method allows us to handle very large-scale BDD stream data beyond the memory limitation. Our method can be characterized as follows: (1) it gives a continuous tradeoff curve between memory usage and stream data length, (2) valid solutions for a partial Boolean space can be obtained if we break the process before finishing, and (3) easily accelerated by pipelined multiprocessing. An experimental result demonstrates that we can succeed in finding a number of solutions to a SAT problem using a commodity PC with a 64 MB memory, where as the conventional BDD manipulator would have required a 100 GB memory. BDD manipulation has been considered as an intensively memory-consuming procedure, but now we can also utilize the hard disk and network resources as well. The method leads to a new approach to BDD manipulation.

In this paper an efficient method to synthesize all-optical synchronous digital finite state machines is suggested. The synthesis is based on the design of purely combinational circuits composed of a cascade of iterative cells that perform the same logical functions of the corresponding synchronous Finite State Machine (FSM). This allows high bit rates and a high degree of modularity, so an easy integration of the circuit is possible. These characteristics make the method suitable to be adopted in a photonic environment in which clocked digital memory elements are still a critical aspect.

Conference of 14th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2014 ; Conference Date: 14 July 2014 Through 17 July 2014; Conference Code:114504; International audience; The complexity of SystemC virtual prototyping is continuously increasing. Accelerating RTL/TLM SystemC simulations is essential to control future SoC development cost and time-to-market. In this paper, we present RAVES, a highly-parallel special-purpose multicore architecture that achieves simulation performance more efficiently by parallel execution of light-weight user-level threads on many small cores. We present a design study based on the virtual prototype of RAVES processors running a co-designed custom SystemC kernel. Our evaluation suggests that a 64-core RAVES processor can deliver up to 4.47× more simulation performance than a high-end x86 processor.

This paper presents a methodology for the automatic generation of clock trees in an ASIC design at the gate level. New algorithms and heuristics are described: they have been inserted with success in an industrial ASIC design flow, after the logic synthesis and optimization step. Our algorithms, by different heuristic methods, particularly take into account those elements connected as transmitter-receiver couples which represent the most critical configurations for circuit synchronization. Improvement of clock tree performance has also been obtained by means of an interaction strategy between logic and physical design phases. Such a strategy drives the placement of the clock tree elements in an equidistant way, in order to obtain a controlled routing.

SRAM arrays are used especially in memory structures inside the processor. Static energy dissipation caused by leakage currents is increasing with every new technology and large SRAM arrays are the main source of the leakage current. We analyzed the content distribution of columns of SRAM arrays and based on the majority of the content, the body-bias of transistors are changed to reduce the static energy dissipation of these SRAM arrays. Our simulations reveal that when our technique is used in the register file of the processor, the leakage energy dissipation decreases by 39% and the total energy dissipation by 14% with an area overhead of 11%.

The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for traditional SRAM designs in the future technologies. In this paper, we propose to use embedded-DRAM (eDRAM) as an alternative in future GPGPUs. Compared with SRAM, eDRAM provides higher density and lower leakage power. However, the limited data retention time in eDRAM poses new challenges. Periodic refresh operations are needed to maintain data integrity. This is exacerbated with the scaling of eDRAM density, process variations and temperature. Unlike conventional CPUs which make use of multi-ported RF, most of the RFs in modern GPGPU are heavily banked but not multi-ported to reduce the hardware cost. This provides a unique opportunity to hide the refresh overhead. We propose two different eDRAM implementations based on 3T1D and 1T1C memory cells. To mitigate the impact of periodic refresh, we propose two novel refresh solutions using bank bubble and bank walk-through. Plus, for the 1T1C RF, we design an interleaved bank organization together with an intelligent warp scheduling strategy to reduce the impact of the destructive reads. The analysis shows that our schemes present better energy efficiency, scalability and variation tolerance than traditional SRAM-based designs.

With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.

With the increasing demand of mobile communication industry and highly progressive VLSI technology, muti-million gates silicon chips are in the market. And to have fault free, reliable chips, extended facility of testable circuit has to be added into the original design. The design technique which includes the testability logic into the design at the logical synthesis level is known as Design for Test abbreviated as DFT [1]. To achieve better fault coverage, I have chosen full scan chain insertion technique for OR1200 design. OR1200 is a 32-bit microprocessor with 5-stage pipeline [12]. Its RTL code is taken from opencores.org and Cadence RTL Compiler version 11.1 is used for logic synthesis. For testing and verification, Encounter Test Version 11.1 and NCVerilog simulator is used. To improve the testability of the design, Deterministic fault analysis and Random Resistant Fault Analysis techniques are also added to the design. Effects of all hardware DFT techniques are analysed in terms of area, dynamic power dissipation and gate count. Main low power technique i.e. clock gating is also inserted along with DFT to achieve better performance in terms of power dissipation. DFT causes 25% of increase in die area and 12% of increase in dynamic power. This is acceptable as we will get OR1200 design with 99.67% fault coverage area.

Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting data-level parallelism. Previous research on vector architectures predominantly focused on performance, so vector processors require a new design space exploration to achieve low power. In this paper, we present a design space exploration of adder unit for vector processors (VA), as it is one of the crucial components in the core design with a non-negligible impact in overall performance and power. For this interrelated circuit-architecture exploration, we developed a novel framework with both architectural- and circuit-level tools. Our framework includes both design- (e.g. adder's family type) and vector architecture-related parameters (e.g. vector length). Finally, we present guidelines on the selection of the most appropriate VA for different types of vector processors according to different sets of metrics of interest. For example, we found that 2-lane configurations are more EDP (Energy×Delay)-efficient than single lane configurations for low-end mobile processors.

International audience; Dynamic reconfiguration of hardware resources is increasingly used in applications as a way to increase performances, resources integration or energy efficiency. As this evolution induces a change of the application execution paradigm, various tools have been set up to develop and manage these applications. But most do not allow direct re-use of legacy code, needing adaptation to match the provided environment. Moreover, partial reconfiguration is only at its early stages, and lacks easy ways of handling. We propose a design methodology and a runtime environment bringing fast integration of legacy hardware accelerators for partial and dynamic reconfigurable hardware architectures. Thanks to it, applications making use of dynamic hardware can be run directly on an Embedded Linux without noticing the reconfiguration flow. Moreover, our design methodology allows providing various implementations of a computation kernel, including both hardware and software ones. The implementation can then be chosen at execution time depending on available resources. In this article, we introduce the generic IP interface description making the re-use process possible. Furthermore, we present the results of a sample application running on our platform using software and hardware implementations. For hardware implementations, we obtain reconfiguration overhead as low as 0.16\% of the total kernel execution time.

Low power is one of the most important issues in today’s ASIC (Application Specific Integrated Circuit) design. As the transistors scale down, power density becomes high and there is immediate need of reduction in power. There are different techniques available for reduction of power like Operand isolation (OI), Clock Gating (CG) and Multi Vth Library Utilization (MVLU). In this report, we present two approaches for power reduction. The first approach gives two algorithms that show how power and performance matrix is improved compared to conventional MVLU technique. In the second approach, it shows the implementation of constrained fanout clock gating and its benefits over conventional clock gating techniques in ASIC design methodology. This report also presents two analyses. The first analysis shows how the design metrics area, power and performance change due to different techniques of low power (Operand Isolation, Clock Gating and Multi Vth Cell Utilization). The second analysis demonstrates the effect of different CG cells in design and presents how the same design metrics are affected for each CG cell. There are two variations in each CG cell, one is with Reset and the other is without Reset. In this report, we also demonstrate how the design metrics are affected by insertion of Reset signal in each CG cell

This paper presents MASCOT (MicroArchitecture Synthesis of ConTrol paths). This synthesis system constructs the optimal microarchitecture for a control path of an instruction set processor. Input to the system is the behavioural specification of a control path. This specification is in finite state machine form which is mapped initially onto a single programmed logic array (PLA) microarchitecture. The synthesis strategy then applies a sequence of decompositions on this initial microarchitecture. This strategy follows a decision scheme until all design objectives are met. It transforms the initial microarchitecture into a complex microarchitecture of several PLAs and ROMs. Where it is impossible to meet the design objectives, the system constructs a microarchitecture which comes as close as possible to given design objectives. Design objectives are allowed on floorplan dimensions and delay. Our strategy integrates a number of known optimization methods for specific microarchitectures. Therefore this synthesis method explores a larger part of the design space than do other control path synthesis methods. Other methods are mostly bound to one microarchitecture which they optimize. Our system is not only very flexible in microarchitecture construction but also open for extension by other optimizations.

A novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) matrix for Low-Density Parity-Check (LDPC) decoder is presented in this paper. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMax, WLAN and DVB-S2. In addition, different combinations of permuted random sub-matrices are embedded in layers, to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated by using the proposed technique has bit error rate (BER) performance very close to that of unstructured random matrices. A prototype model of partially-parallel decoder architecture has been designed by using the various matrix configurations available in the proposed technique. FPGA design results show that the proposed decoder is resource efficient and the power requirements are comparable to that of ASIC based decoders. Refereed/Peer-reviewed

Hardware customization is an effective approach for meeting application performance requirements while achieving high levels of energy efficiency. Application-specific processors achieve high performance at low energy by tailoring their designs towards a specific workload, i.e., an application or application domain of interest. A fundamental question that has remained unanswered so far though is to what extent processor customization is sensitive to the training workload's input datasets. Current practice is to consider a single or only a few input datasets per workload during the processor design cycle - the reason being that simulation is prohibitively time-consuming which excludes considering a large number of datasets. This paper addresses this fundamental question, for the first time. In order to perform the large number of runs required to address this question in a reasonable amount of time, we first propose a mechanistic analytical model, built from first principles, that is accurate within 3.6% on average across a broad design space. The analytical model is at least 4 orders of magnitude faster than detailed cycle-accurate simulation for design space exploration. Using the model, we are able to study the sensitivity of a workload's input dataset on the optimum customized processor architecture. Considering MiBench benchmarks and 1000 datasets per benchmark, we conclude that processor customization is largely dataset-insensitive. This has an important implication in practice: a single or only a few datasets are sufficient for determining the optimum processor architecture when designing application-specific processors.

This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.

Field Programmable Gate Array (FPGA) can be used to enhance the efficiency and the flexibility of digital controller. FPGA implementation of digital controllers leads to real time realizations with small size and high speed. Also it offers advantages such as complex functionality, fast computation, and low power consumption for high volume production. This thesis presents realization of FPGA based speed control of brushless dc (BLDC) motor - a real time application. The construction and the operation of the BLDC motor are described. The different control strategies for speed controller and digital pulse width modulation (PWM) control technique are implemented and tested on BLDC motor. Also their performance is evaluated. Proportional Integral (PI) controller and Fuzzy Logic Controller (FLC) are implemented in FPGA as a digital controller. The PI controller is governed by the values of proportional gain and integral gain, while FLC behaves in much similar way as human controls the system. Logics of both controllers: PI controller and fuzzy logic controller are written in High Description Language (HDL). The performance of the PI controller is better than the fuzzy logic controller in case of the complete known plant.

In this paper, a reduced complexity Low-Density Parity-Check (LDPC) decoder is designed and implemented on FPGA using a modified 2-bit Min-Sum algorithm. Simulation results reveal that the proposed decoder has improvement of 1.5 dB Eb/No at 10-5 bit error rate (BER) and requires fewer decoding iterations compared to original 2-bit Min-Sum algorithm. With a comparable BER performance to that of 3- bit Min-Sum algorithm, the decoder implemented using modified 2-bit Min-Sum algorithm saves about 18% of FPGA slices and can achieve an average throughput of 10.2 Gbps at 4 dB Eb/No. Refereed/Peer-reviewed

The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus on the resources directly. In this work transistor sizing is approached via an MOP and solved by set-oriented numerical techniques. A comparison of the Pareto optimal designs to elements of a commercial standard cell library indicates that for some gates the performance can even be significantly improved.

A readout system for microstrip silicon sensors has been developed. This system is able to measure the collected charge in one or two microstrip silicon sensors by reading out all the channels of the sensor(s), up to 256. The system can operate either with non-irradiated and irradiated sensors as well as with n-type and p-type microstrip silicon sensors. Heavily irradiated sensors will be used at the Super Large Hadron Collider, so this system can be used to research the performance of microstrip silicon sensors in conditions as similar as possible to the Super Large Hadron Collider operating conditions. The system has two main parts: a hardware part and a software part. The hardware part acquires the sensor signals either from external trigger inputs, in case of a radioactive source setup is used, or from a synchronised trigger output generated by the system, if a laser setup is used. The software controls the system and processes the data acquired from the sensors in order to store it in an adequate format. The main characteristics of the system will be described. Results of measurements acquired with n-type and p-type non-irradiated detectors using both the laser and the radioactive source setup will be also presented and discussed.

Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing. To verify the proposed techniques, a 32 kb array of the proposed 10T bit-cell is fabricated in 90 nm CMOS technology. The hardware measurement results demonstrate that this bit-cell array successfully operates down to 160 mV. For leakage power comparison, we also fabricated 49 kb arrays of the 6T and the proposed 10T bit-cells. Measurement results show that the leakage power of the proposed bit-cell is close to that of the 6T (between 0.96x and 1.22x of 6T).