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The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.

Image processing is one of the major techniques that are used for computer vision. Nowadays, researchers are using machine learning and deep learning for the aforementioned task. In recent years, digit recognition tasks, i.e., automatic meter recognition approach using electric or water meters, have been studied several times. However, two major issues arise when we talk about previous studies: first, the use of the deep learning technique, which includes a large number of parameters that increase the computational cost and consume more power; and second, recent studies are limited to the detection of digits and not storing or providing detected digits to a database or mobile applications. This paper proposes a system that can detect the digital number of meter readings using a lightweight deep neural network (DNN) for low power consumption and send those digits to an Android mobile application in real-time to store them and make life easy. The proposed lightweight DNN is computationally inexpensive and exhibits accuracy similar to those of conventional DNNs.

In this paper, a negative high voltage DC-DC converter using a new cross-coupled charge pump structure has been proposed, which can solve the shoot-through current problem of the conventional charge pump by using a four clock phase scheme. Also, by switching the power supply to each stage based on the supply voltage, a variable voltage gain can be obtained. A complete analysis of the interaction between the power efficiency, area, and frequency have been presented. The proposed negative charge pump is designed to deliver 40μA with a widesupply range from 2.5V to 5.5V using 0.18μm high voltage LDMOS technology.

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

Electrocardiogram (ECG) classification has become an essential task of modern day wearable devices, and can be used to detect cardiovascular diseases. State-of-the-art Artificial Intelligence (AI)-based ECG classifiers have been designed using various artificial neural networks (ANNs). Despite their high accuracy, ANNs require significant computational resources and power. Herein, three different ANNs have been compared: multilayer perceptron (MLP), convolutional neural network (CNN), and spiking neural network (SNN) only for the ECG classification. The ANN model has been developed in Python and Theano, trained on a central processing unit (CPU) platform, and deployed on a PYNQ-Z2 FPGA board to validate the model using a Jupyter notebook. Meanwhile, the hardware accelerator is designed with Overlay, which is a hardware library on PYNQ. For classification, the MIT-BIH dataset obtained from the Physionet library is used. The resulting ANN system can accurately classify four ECG types: normal, atrial premature contraction, left bundle branch block, and premature ventricular contraction. The performance of the ECG classifier models is evaluated based on accuracy and power. Among the three AI algorithms, the SNN requires the lowest power consumption of 0.226 W on-chip, followed by MLP (1.677 W), and CNN (2.266 W). However, the highest accuracy is achieved by the CNN (95%), followed by MLP (76%) and SNN (90%).

In this paper, we proposed a nano-power tunable bump circuit. It incorporates a novel source-degenerated transconductor using pseudo-resistor as source resistor to control the width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS process under 1.8V power supply. The results show that the transconductance is tuned with pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3V to 1.8V. Also, this circuit is compact and only dissipates 16.7nW power which makes it perfect for large-scale machine learning applications such as classifier and support vector machine.

Recent advances in the field of AI have proved that deep neural networks perform and recognize arrhythmia better than cardiologists when trained with a large chunk of data. However, despite the better performance, deep neural networks demand more resources. Therefore, in this paper, a new deep neural network using low resources has been proposed while maintaining high performance, and it is enhanced with a depthwise separable convolution layer for Electrocardiogram (ECG) classification. The algorithm is performed on the Physikalisch-Technische Bundesanstalt (PTB) diagnostic dataset taken from Physionet consisting of two classes: Myocardial Infarction (MI) and Normal (N). Our simulation results show that the proposed lightweight DNN provides high performance with almost the same accuracy as conventional SquezeNets.

Multi-threshold null convention logic (MTNCL) is a novel low power paradigm for designing asynchronous null convention logic (NCL) circuits. To further reduce the dynamic power consumption, a new methodology that utilizes gate diffusion input technique is proposed. The proposed approach is used to realize MTNCL gates and a decrease in the transistor count is observed that tend to reduce the dynamic power consumption. Compared to SMTNCL approach, the proposed methodology shows a 5.6% is reduction in the power consumption for the MTNCL gates.

A single-inductor dual output boost converter behavioral model was designed using a 180nm CMOS technology and VerilogA. The converter adopts time-multiplexing control by providing independent supply voltages (3.0V and 4.0V) and adjustable peak current for dual output system loads including battery charging. The converter was analyzed and compared to existing architectures presented in literature in the aspects of power path and control scheme. The proposed topology and control loop can be extended to include additional outputs. Implementation of the power stage, controller, and functional blocks are discussed.

In this work, the modeling of spiking neurons and their VLSI implement issues are evaluated and discussed in detail in terms of silicon area, power, and stability considering nanometer technologies process, voltage, and temperature variations. Considering low power requirement and stability, Hindmarsh-Rose model turns out to be the best choice for neural network implementation because of its affordable cost and rich neural features. Although other models such as Leaky Integrate-and-Fire model costs less, it is limited by its poor neural plausibility.

Multi-threshold null convention logic (MTNCL) is a commonly used asynchronous paradigm for designing low power NCL circuits. Traditionally, MTNCL circuits implemented using complementary metal oxide semiconductor (CMOS) technique that tends to occupy a large area. To address this limitation, a gate diffusion input (GDI) methodology is introduced for implementing MTNCL circuits. This GDI technique enables complex logic to be implemented using only two transistors that helps to reduce area utilization. In this paper, a novel approach to implement MTNCL designs based GDI methodology is proposed. The proposed approach has been verified by implementing TH23 MTNCL gate. Comparing to the conventional CMOS implementation, the proposed approach shows a 45% reduction in the area overhead.

Null convention logic is a commonly used delay insensitive paradigm for designing asynchronous circuits. Traditionally, NCL circuits are implemented using static complementary metal oxide semiconductor (CMOS) technology that tends to have large area overhead. To address this issue, a gate diffusion input (GDI) methodology is introduced for realizing NCL circuits. This GDI is a low-power design approach that uses only two transistors to design complex circuits. By using this design technique, a significant reduction area utilization was observed at the expense of latency overhead. To address this limitation, a novel design approach based on GDI methodology is proposed in this paper. The proposed fast GDI (FGDI) approach uses GDI functions F1 and F2 to reduce latency without affecting performance. To evaluate the performance of the FGDI technique, a one-bit full adder was realized in Cadence virtuoso 45nm technology. Compared to GDI implementation, FGDI approach shows a 76% reduction in the latency.

Graphical Processing Units (GPUs) are always criticized for high power consumption due to its massive performance that it can deliver. While GPUs are getting into the mobile market, more power constraints are established. In this work, we evaluate the power gating techniques for GPU cache arrays. The leakage power in active mode is measured at 2.28 µW whereas is sleep mode leakage power is measured at 0.61 µW (26.7% of active mode leakage) and 0.034 µW at off mode (1.5% of active mode leakage) at 1.0V power supply using 45nm standard CMOS process.

Cardiovascular diseases (CVDs) are the number one cause of death today. Therefore, the early detection of arrhythmia is very important for cardiac patients. This paper proposes the heartbeat classification algorithm using the electrocardiogram(ECG) signals. An ECG is a 1D signal that is the result of recording the electrical activity of the heart using an electrode. In this paper, a single-layer Tensorflow LSTM model has been proposed to classify a biological time-series consisting of normal and abnormal heartbeats. The method was evaluated using the publicly available Physio net's MIT-BIH Arrhythmia dataset. The dataset has been divided into training and testing data. As a result, the classifier achieved a 95% average accuracy. Compared with the other CNN and RNN models used for the heartbeat classification, the simulation result shows the proposed algorithm has higher accuracy.

The paper presents standing wave oscillator-based clock distribution minimizing equivalent capacitance (c d ) for process and temperature variation. The SWOs have been proposed to enhance the negative resistance g d (an equivalent transconductance per ccp) to cancel the conductance in a transmission line. However, the SWOs have a parasitic capacitance which affects clock phase and unit length of the transmission line. In the proposed SWO, a MOS varactor, C var (V) (voltage-controlled capacitance), is added to minimize c d (equivalent capacitance per ccp). A phase locked loop and other peripherals are added to adjust the frequency and c d because the target frequency in the SWO varies due to process and temperature variation The design is simulated by a 180nm CMOS technology node with 1.8V power supply, and the total power consumption is 31.841 mW for the proposed architecture.

Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based computations, however, are not only susceptible to noise and other skin color segments but also inherently sequential and difficult to efficiently parallelize. In this paper, we implement and accelerate our in-house distance image based approach using CPU-GPU heterogeneous computing. Using emerging CPU-GPU heterogeneous computing technology, we achieved 5.0 times speed-up for 320x240 images, and 17.5 times for 640x480 images and our experiment demonstrates that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate, 80.4% of which have more than 3 fingers detected on commodity processors.

The increasing power consumption in the synchronous circuits is the major concern in the semiconductor industry. The major contributor to this power consumption is the clock generator and the clock distribution. This problem can be addressed by using the asynchronous circuits. Null Convention Logic (NCL) is one of the most commonly known delay insensitive approach for designing asynchronous designs. However, realizing the NCL circuits using the commonly used complementary metal oxide semiconductor (CMOS) technique is said to increase the area and the power consumption. The low power design technique known as Gate Diffusion Input (GDI) can be used for implementing the NCL circuits to reduce both the area and the power. Application of the external input to the sources of the pMOS and nMOS transistors, allows to reduces the area and the dynamic switching. Thus, decreasing the transistor count and the power. The proposed GDI NCL technique is used for designing the 4-bit un-pipelined NCL multiplier. The design was realized and simulated in gpdk045 Cadence Virtuoso. In comparison to the CMOS model, the GDI model shows 21.6 % in transistor count and the dynamic power is reduced by 13.7 %.

Stochastic computing as a computing paradigm is currently undergoing revival as the advancements in tech-nology make it applicable especially in the wake of the need for efficient reduced precision computing for emerging applications. Recent research in stochastic computing exploits the benefits of approximate computing, called Approximate Stochastic Computing (ASC), which further reduces the op-erational overhead in implementing stochastic circuits. A new generalized adaptive method improving on ASC is proposed in this work. The proposed method has been discussed with two possible implementation variants - Area efficient and Time efficient. The proposed method has also been implemented in Matlab to compare against ASC and is shown to perform better than previous approaches for error-tolerant applications.

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

Null Convention Logic (NCL) is the one of the well-known clock-less approaches for designing asynchronous logic circuits. The complementary metal oxide semiconductor (CMOS) technology is usually used for implementing the NCL circuits, which as a major drawback of large area consumption and power dissipation. These limitations have been addressed by adopting a low-power design technique called Gate Diffusion Input (GDI) in this work. GDI technique allows implementing primitive logic gates using only two transistors. Thus, it not only reduces the transistor count but also the power consumption. However, GDI technique suffers a significant voltage drop across the circuit, due to its inherent voltage swings. Thus, to ensure full swing output regenerative buffers are added at the output stage which tends to increase the overall latency. In this work, a novel GDI and HYBRID (CMOS+GDI) designs are proposed to overcome the limitations of the CMOS-NCL designs. The proposed approaches were tested by realizing NCL Ripple Carry Adder (RCA). The proposed model was simulated in Cadence Virtuoso and power reduction of 14.9 % and 9.8 % has been observedfor GDI and HYBRID models, respectively.

Lately, stochastic computing (SC) has been found to be significantly advantageous in image processing applications because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to excessive run-time requirement. In this paper, a new technique called the variable bit truncation approximate stochastic computing (ASC) approach focusing on image processing applications is proposed to reduce the computation time of a SC with an acceptable trade-off in accuracy. The proposed technique is to variably truncate the low-order bits of the image pixel value depending on the application and the accuracy limits. Experimental results on standard test images for multiple image processing applications suggest that by using this approach acceptable output images can be generated using stochastic computation at a much faster way.

This paper presents a low power and small area temperature sensor with interlaced hysteresis delay cells (IHDCs) instead of using inverter-based buffers. IHDC consumes lower power and occupies smaller silicon area than inverter-based buffers. A pulse width which is proportionate to temperature is produced by the proposed temperature-to-pulse generator. Two different delay lines and an XOR gate are employed to detect pulse width for temperature measurement. Temperature dependent and thermal insensitive delay lines are used as the two different delay lines. The output of the temperature-to-pulse generator is converted to digital output by a time-to-digital converter. This temperature sensor is simulated with 0.18um CMOS technology and 1.8V supply voltage, and it shows a good linearity with lower power consumption compared to conventional ones. The proposed temperature sensor consumes 1.185 mW.

The clothing materials are ubiquitous part of our everyday life for thousands of years. However, despite this they have largely not been considered as an input surface in human device interactions, but that is until more recently as today's developments of wearable sensors, that are small and flexible in nature, have open this platform. The clothing materials' shape-changing nature enables the users to perform gestures (e.g., bend or stretch) not possible when compared to the interaction methods of flat touchscreens of mobile devices. In addition, the clothing-based interfaces by default have the unique advantage of being placed anywhere on the body and always being with the wearers and their devices. In this paper, we validate the use of clothing-based wearable sensors to support interacting with mobile devices and present some challenges to be overcome for clothing-based interfaces to be adopted more widely.

Nowadays, robots take more charges of human activities, especially in repeated tasks, daily homecare and emergency rescue. Instead of using a solo robot to execute specific tasks, it calls for multi robots to cooperate in more scenarios, especially doing complex and difficult tasks that a single robot could not complete. In this paper, firstly it demonstrates a simplified model of the real disaster rescue scenario where requires robots to remove rocks from the road. Then it discusses the system how multi robots communicate wirelessly and cooperate together based on this abstract scenario. Finally, it evaluates and reflects the built system.

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. 4×4 multipliers have been designed in a 45nm predictive technology using the proposed SG-SCL gates and pipeline structure and using the conventional MTNCL (Safe SECRII architecture), and they have been compared in terms of speed, power consumption, energy and size. The simulation results show that the proposed design reduces 60% energy, 54% leakage power and 25% area compared to the MTNCL (Safe SECRII architecture) design.