Search

In the era of Artificial Intelligence (AI), bio-inspired perceptual computing system design brings favorable opportunities, while still facing considerable challenges in the meantime. Especially for tasks of image recognition in power-limited vision-based Internet of Things (IoT) devices, energy constraints due to the end of Dennard scaling limit the performance of Neural Network (NN) algorithms on popular digital platforms, which would not reach the energy efficiency requirement for embedded AI applications. In this paper, a processing near sensor architecture in mixed-signal domain with CMOS Image Sensor (CIS) of convolutional-kernel-readout method is proposed. Visual data is collected from a smart CIS, which can realize maximum $5 \times 5$ kernel-readout with minimum one slide step for convolutional operations. The outputs of CIS are directly processed by analog processing units locating near CIS without the constraint of digital clock and bottleneck of Analog-to-Digital Converter (ADC). By analyzing the effects of analog noise on classification accuracy, we further evaluate the fault-tolerance of the system to circuit noise and the device imperfection, such as mismatch and process variation. A mixed-signal visual perception chip is fabricated with a $32\times32$ image sensor and a Binarized Neural Network (BNN) processing array integrated with SMIC 180nm standard CMOS mixed-signal process. Measurement results show up to 545.4 GOPS/W energy efficiency with 1.8mW power consumption taking the advantages of ADC-free processing architecture. This work provides a promising alternative for low-power vision-based IoT intelligent applications.

In always-on intelligent visual perception applications, Convolution Neural Network algorithm has been widely applied. However, the implementation of it's processing is limited by hardware resources and energy budgets, which come from data access, interface overhead and inflexible configuration. In this paper, we present a novel analog architecture that implements low-precision Binary Neural Network and fuses with CMOS image sensor for always-on applications. By enabling current-mode computation in analog domain, the overhead of analog-to-digital converter as well as analog buffer is eliminated. And in order to relax the overhead of CIS, conventional correlating-double-sampling is moved to Computation Module. Moreover, the architecture is also dynamic-configurable, which is optimized specifically for CIS data flow. Simulations with HSPICE show that the peak energy efficiency of proposed architecture can achieve 13.91 TOPS/W at the 8-bit percision of multiplication-and-accumulation analog computation, while accuracy loss is only about 5.66%.

Direction of arrival (DOA) is a critical component in the conventional smart acoustic system for navigation, noise canceling hearing aids and so on. However, conventional DOA has encountered power consumption and processing speed bottlenecks dominated by analog-to-digital converter (ADC) and fast fourier transform (FFT). Especially in the always-on applications, the power-hungry ADC and time-consuming FFT take up most of the system's computation cost. We propose a novel processing architecture with analog-domain processing for DOA. The whole processing procedure of DOA is implemented in the analog domain without ADC and frequency-domain transformation. In order to verify the performance of the architecture, we simulate a generic DOA algorithm. Under the CMOS 0.18µm process, the results show the 94.5% reduction in power consumption and 4724× improvement in processing speed compared to conventional digital realization. We simulate the simple task with the direction accuracy of 80.74%, which can be extended to a more complex scenario.

Approximate memory is a significant improvement in a variety of application domains, especially which are both computationally intensive and memory intensive just as image classification. In this paper, we proposed an approximate on-chip memory optimization method with bit-width scaling and random bit flipping suited the deep residual neural network, which can be used to take the image classification. We evaluate the power and area benefits of our method. It demonstrated about 66.51% improvement in memory power and 56.93% improvement in memory areas with 0.91% quality loss for ResNet-50 across ImageNet. We also use this method for ResNet-101 and ResNet152, and achieve similar results.

Convolutional Neural Network (CNN) is a powerful model for image classification, but it is insufficient to deal with the spatial variance of the input. This paper presents a Maxout-based and input-normalized transformation invariant neural network (MINTIN), which aims at addressing the nuisance variation of images and accumulating transformation invariance. We introduce an innovative module, the Normalization, and combine it with the Maxout operator. While the former focuses on each image itself, the latter pays attention to augmented versions of input, resulting in fully-utilized information. This combination, which can be inserted into existing CNN architectures, enables the network to learn invariance to rotation and scaling. While the authors of TI-POOLING acclaimed that they reached state-of-the-art results, ours reach a maximum decrease of 0.71%, 0.23% and 0.51% in error rate on MNIST-rot-12k, half-rotated MNIST and scaling MNIST, respectively. The size of the network is also significantly reduced, leading to high computational efficiency.

Process Variation (PV) may cause accuracy loss of the analog neural network (ANN) processors, and make it hard to be scaled down, as well as feasibility degrading. This paper first analyses the impact of PV on the performance of ANN chips. Then proposes an in-situ transfer learning method at system level to reduce PV's influence with low-precision back-propagation. Simulation results show the proposed method could increase 50% tolerance of operating point drift and 70% ∼ 100% tolerance of mismatch with less than 1% accuracy loss of benchmarks. It also reduces 66.7% memories and has about 50× energy-efficiency improvement of multiplication in the learning stage, compared with the conventional full-precision (32bit float) training system.

AICNN architecture is presented in this work to map the state-of-the-art machine-learning algorithms of CNN to power-constrained embedded hardware. As the combination of analog-to-information conversion and typical CNN algorithms, AICNN can realize ultra-highly efficient computation by using massive parallel analog signal processing circuits, which could also significantly reduce ADC devices cost of converting sensors' outputs. As a design example, the specific AICNN-3 implementation is evaluated, which realize the minimum system of typical CNN task using AICNN architecture, with SMIC 0.18 µm CMOS process. Simulation results show that the AICNN-3 can classify a 28x28 MNIST image with only 1.47nJ. Compared with baseline implementation on CPU, the AICNN-3 could achieve 67000x energy-efficiency improvement, however the accuracy loss is less than 1%. Moreover, the influences of devices mismatch and process variations are evaluated using Monte Carlo statistical method, for the imperfection of analog processing paradigm, as well as the scalability of AICNN architecture is also discussed.