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A piezoelectric (PE) energy harvesting system with one-cycle maximum power point (MPP) sensing is presented. The one-cycle MPP sensing method uses a very small size sensing capacitor and it can make the transducer output voltage reach the open circuit voltage within one cycle. The proposed MPP sensing block can sense the open circuit voltage with a proposed peak detector and stores the MPP voltage using charge sharing blocks. The one-cycle MPP sensing approach simplifies the design of an MPP tracking algorithm and greatly reduces the tracking time. All control blocks are self-biased and choose the higher voltage between the input or output voltages of the switching converter as a supply voltage (V $_{DD}$ ). Therefore, a voltage multiplexer and a low-power ramp generator with V $_{DD}$ independence are also proposed to control the system without additional DC to DC converter. The entire system has been implemented in a 0.35 µm BCDMOS process. It operates at 90 kHz with a 10-mH inductor. The total power dissipation of the controller is 10 µW at a V $_{DD}$ of 2.7 V. The MPP tracking time is only 9.09 ms/V when the input voltage of the switching converter is changed from 3.4 V to 1.2 V.

Design of low-voltage and efficient energy-harvesting circuits is becoming increasingly important, particularly, for autonomous systems. Since the amount of energy that can be harvested from the surrounding environment is limited, the available output voltage of a harvester is low. Therefore, the design of a low-input-voltage (low-VIN) up-converter is critical to self-powered systems [1-3]. Moreover, the form factor is very constrained in applications such as wearable electronic devices and sensor networks. Recently, low-VIN charge pumps (CPs) for energy harvesting has been compared with DC-DC converters using a large inductor [1-3]. CPs introduced in [1] and [2] use the advanced process technology to push VIN down to the subthreshold region. The CP in [1] introduces a forward-body-biasing (FBB) technique, which improves the voltage conversion efficiency (VCE) for low VIN but shows poor power conversion efficiency (PCE). The CP in [2] achieves the lowest operation voltage. However, the design with a 10-stage CP provides low output power. This paper presents a CP with switching-body-biasing (SBB), adaptive-dead-time (AD), and switch-conductance (SW-G) enhancement techniques to improve the PCE for low VIN as well as to extend the maximum load current.

An ac-dc rectifying system for vibration energy harvesting is proposed to generate outputs of four different voltage levels with a single power source. The proposed dual-output rectifier uses only four diodes, similar to a conventional single-output full-bridge rectifier. A switched-capacitor down-converter provides two output voltages from a single input from the voltage doubler by using the proposed load balancer with a low design complexity. The proposed system is implemented in a 0.35-μm CMOS process, and it occupies an area of 0.143 mm 2.

This paper presents a dc-dc boost converter with the maximum power point tracking (MPPT) technique for thermoelectric energy harvesting applications. The technique realizes variation tolerance by adjusting the switching frequency of the converter. A finely controlled zero-current switching (ZCS) scheme together with the accurate MPPT technique enhances the overall efficiency of the converter because of an optimal turn-on time generated by a one-shot pulse generator that is proposed. Moreover, the ZCS technique can deal with low- and high-temperature differences applied to the thermoelectric generator. This allows a wider range of conversion ratios compared to those of conventional converters used for thermal energy harvesting. Experimentally, the converter implemented in a 0.35-μm BCDMOS process had a peak efficiency of 72% at the input voltage of 500 mV while supplying a 5.62-V output.

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5× to 8× of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-μm CMOS process occupies an active area of 0.27 mm2 and consumes 15.56 mA.

Coarse grained arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design on-chip communication networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This paper presents a silicon-proven design of a 64-PE circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. A proof-of-concept test chip fabricated in a 0.13 μm CMOS process occupies a silicon area of 23 mm2 and consumes a peak power of 200 mW @ 128 MHz and 1.2 Vcc, at room temperature. The OCN overhead consumes 9.4% of the area and 18% of the power of the total chip. Experimental results and analysis show that the proposed OCN fabric with its dynamic path-setup is suitable for use in an embedded CGA supporting fast run-time reconfigurability.

This brief presents a regulated charge pump (CP) with an integrated optimum power point tracking (OPPT) algorithm designed for indoor solar energy harvesting. The proposed OPPT circuit does not require a current sensor that consumes power proportionally to the load. The solar cell voltage is regulated at the optimum power point; the CP output is regulated according to the target voltage. The controller of the OPPT circuit and CP dissipates only 450 nW; thus, the proposed technique is appropriate for indoor solar energy harvesting applications under dim lighting conditions.

A voltage-mode DC-DC converter with a novel oscillator and ramp generator is presented. The proposed oscillator and ramp generator has a simple structure and does not need an external reference signal generator to set the upper and lower levels of the ramp signal. The DC-DC converter was fabricated in a standard 0.5µ m CMOS process. The converter can operate from 465kHz to 556kHz with a supply voltage from 3 to 5.5V, which is appropriate for portable electronic devices that are powered by a single-cell lithium-ion battery. The output ripple voltage is about 10mV with a 10µ F off-chip capacitor and a 10µ H off-chip inductor. The power conversion efficiency is over 80% for load currents from 30 to 400mA.

This paper presents a boost converter with the maximum power point tracking (MPPT) technique for thermoelectric energy harvesting (EH) applications. The technique realizes variation tolerance by adjusting the switching frequency fSW of the converter. A finely controlled zero-current switching (ZCS) scheme together with the accurate MPPT technique enhances the overall efficiency (η) of the converter because of an optimal turn-on time generated by a one-shot pulse generator that is proposed. Moreover, the ZCS technique can deal with low and high temperature differences applied to the thermoelectric generator. Experimentally, the converter implemented in a 0.35 um BCDMOS process had a peak of 72% at the input voltage VIN of 500mV while supplying a 5.62V output.

This paper describes a time-limited power distribution control (TPDC) technique that can be used for single-inductor multiple-output (SIMO) DC-DC converter with many unbalanced loads. Furthermore, the true all-comparator control technique that raises no stability or complexity issues is proposed. This all-comparator technique for SIMO converters is realized only with a single shared hysteresis comparator at a constant switching frequency of 800 kHz. The maximum efficiency reaches 92%. The fabricated chip with 8-channel outputs occupies 2.4×2.1 mm2 in a 0.35-um CMOS process.

This paper presents a low-voltage high-efficiency voltage doubler for thermoelectric energy harvesting. A negative charge pump is used to reduce on-resistance of PMOSFET load switches. Additional circuitry for achieving high efficiency just requires small chip-area and low-cost. The voltage doubler is implemented in 0.13-μm 1.2V CMOS process. The proposed doubler improves the low-voltage power efficiency by 17%, compared to conventional voltage doublers. Moreover, the proposed doubler can support wider load range. The maximum power efficiency reaches 52% at the input voltage of 0.2V.

This paper presents a regulated charge pump (CP) with an integrated optimum power point tracking (OPPT) algorithm designed for indoor solar energy harvesting. The proposed OPPT circuit does not require a current sensor that consumes power proportionally to the load. The solar cell voltage is regulated at the optimum power point; the CP output is regulated according to the target voltage. The controller of the OPPT circuit and CP dissipates only 450nW, so the proposed technique is appropriate for indoor solar energy harvesting applications under dim lighting conditions.

A compact soft-start technique, with an internal circuitry, is presented for the start-up of current mode DC-DC converters for biomedical applications. Examples of medical applications in DC-DC converters include bio-patch, wireless medical sensor node, RFID applications and medical instruments that must have a high stability. To achieve this, a soft-start circuit is proposed to prevent inrush current and output voltage overshoot, during the start-up of the current mode DC-DC converters. The output of the error amplifier is controlled by a stair-case waveform signal generator during the start-up period. The proposed soft-start circuit is fully integrated on chip for portable and wireless medical devices, so that the external components are not required, leading to a reduction in the PCB space and cost. The new soft-start circuit which is digitally-controlled unlike conventional ones was fabricated in a CMOS 0.35-µm process and occupies an active area of 0.19 mm2 with a 3.3 V supply voltage.

This paper describes an integrated current-mode buck converter with reliable hysteretic mode controller and modulators for fast dynamic voltage scaling (DVS). The proposed mode controller and modulators enable the DC-DC buck converter to perform its smooth mode transitions at optimal points. The continuous current-limiting and DCM controls drive the DVS to track the reference at the maximum speed in both PWM and PFM modes. The DC-DC buck converter is implemented in a 90-nm 3.3V CMOS process. The maximum efficiency reaches 94.5%. The hysteretic mode controller keeps its efficiency always at more than 75% for any load conditions. During a mode transition, the output voltage has no overshoots, and it can track the reference voltage instantly.

This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-mum CMOS process. The implemented DVS circuit provides a supply voltage from 1.4 V to 1.8 V and the DFS circuit dynamically generates the system clock from 7.5 MHz to 120 MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm2 and 0.27 mm2 active areas, respectively.

A high-performance wide-V DDH-range level converter (LC) is presented for mixed-signal systems. The proposed LC achieves a low power-delay product over a wide range of V DDH with V DDL in the near-threshold region. The proposed LC uses a feed-forward signal to pull down the output voltage at low V DDH, without increasing the size of the nMOS diode for the pseudo-V DDL. A comparison with conventional LCs shows that the proposed LC not only supports high V DDH but is also robust at low V DDH while exhibiting high performance.