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The use of capacitive sensors in the automotive context opens new possibilities in the development of new interfaces for machine interaction with the vehicle occupants. Large smart surfaces with gesture recognition will possibly be part of such new interfaces. However, the data processing cost of such new sensors should be maintained at a minimum while increasing the complexity of their gesture recognition accuracy by using modern deep-learning approaches. In this paper, we introduce the use of Bayesian optimization with execution platform constraints to implement accurate gesture recognition sensors based on 1D capacitive sensor arrays. Various RNN-based designs are implemented and optimized for their execution on embedded automotive microcontrollers. We show that LSTM and GRU-based designs are especially adequate achieving an average recall of the gesture classes over 95% in less than 100 optimization steps.

The advent of machine learning (ML) methods for the industry has opened new possibilities in the automotive domain, especially for Advanced Driver Assistance Systems (ADAS). These methods mainly focus on specific problems ranging from traffic sign and light recognition to pedestrian detection. In most cases, the computational resources and power budget found in ADAS systems are constrained while most machine learning methods are computationally intensive. The usual solution consists in adapting the ML models to comply with the memory and real-time (RT) requirements for inference. Some models are easily adapted to resource-constrained hardware, such as Support Vector Machines, while others, like Neural Networks, need more complex processes to fit into the desired hardware. The ADAS hardware (HW platforms) are diverse, from complex MPSoC CPUs down to classical MCUs, DPSs and application-specific FPGAs and ASICs or specific GPU platforms (such as the NVIDIA families Tegra or Jetson). Therefore, there is a tradeoff between the complexity of the ML model implemented and the selected platform that impacts the performance metrics: function results, energy consumption and speed (latency and throughput). In this paper, a survey in the form of systematic review is conducted to analyze the scope of the published research works that embed ML models into resource-constrained implementations for ADAS applications and what are the achievements regarding the ML performance, energy and speed trade-off.

Gait analysis has evolved significantly during last years due to the great development of the Medical Internet of Things (MIoT) platforms that allow an easy integration of sensors (inertial, magnetic and pressure in our case) to the complex analytics required to compute, not only relevant parameters, but also meaningful indexes. In this paper, we extend a previous development based on a fully wireless pair of insoles by implementing an updated version with more reliable and user-friendly devices, smartphone app and web front-end and back-end. We also extend previous work focused on fall analysis (with the corresponding fall risk index or FRI) with the proposal of a new surgery recovery index (SRI) to account for the individual speed recovery speed that can be measured either at clinical facilities or at home in a telemedicine environment or while doing daily life activities. This new index can be personalized for different types of surgeries that affect gait such as hip, knee, etc. This paper presents the case of hip recovery and is built on top of the clinical standard SPPB test and allows obtaining quantitative parameters directly from the sensors.

Gait analysis has evolved significantly during last years due to the great development of the Medical Internet of Things (MIoT) platforms that allow an easy integration of sensors (inertial, magnetic and pressure in our case) to the complex analytics required to compute, not only relevant parameters, but also meaningful indexes. In this paper, we extend a previous development based on a fully wireless pair of insoles by implementing an updated version with more reliable and user-friendly devices, smartphone app and web front-end and back-end. We also extend previous work focused on fall analysis (with the corresponding fall risk index or FRI) with the proposal of a new surgery recovery index (SRI) to account for the individual speed recovery speed that can be measured either at clinical facilities or at home in a telemedicine environment or while doing daily life activities. This new index can be personalized for different types of surgeries that affect gait such as hip, knee, etc. This paper presents the case of hip recovery and is built on top of the clinical standard SPPB test and allows obtaining quantitative parameters directly from the sensors.

Laser Marking is a very common part of many manufacturing processes usually performed at the last stages of production lines after the packaging of goods. The speed of production lines are key determinants of the output capacity of many industries, but their scalability could be hindered by some fundamental limits of current laser marking technologies. In this paper, we review related technologies, their limiting factors, and analyze how future systems could overcome them.

This paper discusses the semiotic dimension of patent interpretation. Patent documents are at the same time disclosure of information (by the inventors to society) and a granting of rights (by society to the inventors). The claim section expresses the granted rights. In this paper, we view the claims as signs that express the granted rights (mental concept). The semantics to interpret the signs is given by the all-elements rule, as pragmatics. The description and drawings sections of the patent document provide metapragmatics in the form of lexicon and syntax to help the understanding the claims as signs that express the granted rights. This semiotic approach for patent interpretation has important practical consequences to the correct structuring of a patent document. We highlight this contribution through an instance of a patent application in which a claim includes examples of use. Examples are not allowed in the claim text, as examples do not describe the invention, but consist of metapragmatics to better understand the invention. In this way, examples consist of metapragmatics and belong to the description section of the patent, which has the goal to facilitate the understanding of claims (by providing the necessary metapragmatics in the form of lexicon and syntax). In the patent application used to highlight our semiotics approach for patent interpretation, the examples initially presented in the claims were rephrased in the final granted patent, significantly reducing the scope of the claim.

Augmented reality is showing a continuous evolution due to the increasing number of smart glasses that are being used for different applications (e.g. training, marketing, industry, risk avoidance, etc.). In this paper, we present an implementation that uses augmented reality (AR) for emergency situations in smart buildings by means of indoor localization through the use of sub-GHz beacons. This also includes the mapping of emergency elements in the three-dimensional building, together with some example cases.

Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.

Ajudes: National Key Research and Development Program of "Strategic Advanced Electronic Materials" under Grant 2016YFB0401100 and in part by the NSFC of China under Grant 61274083 and Grant 61334008. Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper providesa comprehensive reviewof the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

Neural Architecture Search (NAS), which allows for automatically developing neural networks, has been mostly devoted to performance on a single metric, usually accuracy. New approaches have added more objectives, such as model size, in order to find networks suitable for resource-constrained platforms. SpArSe [1] is a multi-objective Bayesian optimization framework for automatically developing image classification convolutional neural networks (CNNs) for micro-controller units (MCUs). In this work, we first implement SpArSe and modify it to reduce search time, obtaining similar results regarding accuracy, model size, and maximum working memory but in less optimization time. Moreover, we extend the search space to include recurrent neural networks (RNNs) and add an inference latency objective for time-constrained tasks. Finally, we test our implementation in a gesture recognition task obtaining better results than previous manually tuned approaches for size and performance metrics, which validates the approach and its utility.

Capacitive sensing offers new possibilities for HMI product development. Its short range of interaction entails robustness against environmental noise and its flexibility for integration makes it a genuine technology for embedded systems. In the automotive context, capacitive sensing is explicitly devoted to driver interaction with car functionalities. However, the increasing complexity of captured signals and related interaction procedures impose severe difficulties for a classic modelling approach. Neural networks have demonstrated unbeatable performance in tasks with abundant data. Specifically, recurrent neural networks (RNNs) show excellent performance for tasks with inherent temporal structure. In this article, we develop a capacitive-sensing module that includes RNN-based dynamic gesture recognition, which has a suitable implementation size for embedded automotive applications.

In this paper we present a novel method to print paper and cardboard without ink. The method is based on the carbonization of paper by a combination of lasers working on different wavelengths. A prove of concept system is created based on combining existing commercial systems to demonstrate the viability of the method. The results show that no debris is generated and the quality of the mark is superior in terms of contrast and resolution with previously known methods.

The creation of visible changes marked onto object surfaces by laser has become an effective way of coding industrial products. Industrial applications for printing solutions drive the demand for higher speed and higher throughput for in-line digital laser marking. Currently, most laser marking equipment is based on a single laser beam with the corresponding sequential processing that culminates in a performance bottleneck which limits printing production line speed to a de facto barrier of 8 m/s. In this paper, we present a system that overcomes this barrier by using a matrix of laser beams controlled by an embedded high-performance computing platform. The industrialized solutions presented in this paper can print images of 50 to 200 dpi resolution on printing substrates widths ranging from 6 mm to 50 mm, at product line speeds of up to 16 m/s. The analysis we have performed suggests that even higher speeds could be achieved by investing in additional laser beams.

Organic electronics is one of the most promising technologies for creating flexible electronic devices using low temperature plastic compatible processes. However, contact resistances of organic transistors remain one of the most significant hurdles to achieving high performance circuits in this technology. Short channel devices (

Implementation of organic digital circuits (or printed electronic circuits) has been under an extensive investigation, facing some critical challenges such as process variability, device performance, cell design styles and circuit yield. Failure in any single Organic Thin Film Transistor (OTFT) often causes the whole circuit to fail since integration density is still low. For the same reason, the application of fault tolerant techniques is not that popular in these circuits. In this paper, we propose an approach for the direct mapping of digital functions on top of new prefabricated structures: Inkjet-Configurable Gate Arrays (IGA). This alternative has two main advantages. First, it helps to obtain high yield circuits out of mid-yield foils, and second, it allows implementing individual circuit personalization at a very low cost by using additive mask-less printing techniques thus avoiding the need for OTPROM-like (or E2PROM) devices. All along the design process of IGA cells and structures we used the scalability and technology-independent strategies provided by parameterizable cells (PCell) what helps dealing with current fast technology evolution.

In the last years there has been a growing interest in the realization of low-cost, flexible and large area electronic systems such as item-level RFID tags, flexible displays or smart labels, among others. Specifically, inkjet printing technology has been increasingly applied as advanced deposition technology in the field of printed electronics due to the high flexibility in terms of patterns (mask-less) and materials, and its low cost approach as only a small amount of materials is required in comparison to other solution-based deposition techniques. Our work focuses on the development of Organic Thin Film Transistors (OTFTs) by using organic, inorganic inks and low-cost all-inkjet purely printing process, thus centring the effort in the design, manufacturing and characterization point of view in order to fabricate all-inkjet printed organic integrated circuits. Electrical and morphological characterizations were performed in order to obtain device statistics to investigate the origins of the failures responsible for the low yields. Most of research works are based on laboratory inkjet equipment for manufacturing using single nozzle systems to fabricate small numbers of devices. The variability and mismatch of the printed devices are underrepresented in literature and are key factors towards commercialization of printed electronics.

We report on the development of inkjet-printed thin-film resistors using both organic and inorganic ink formulations. The passive devices were manufactured on flexible polymer substrates in ambient condition without the need for a cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. By using the same manufacturing process, the rapid electrical sintering (RES) method is demonstrated as effective for the fabrication of inkjet-printed, programmable Write-Once-Read-Many (WORM) memories. Several hundred fully inkjet-printed resistors with different parameters were fabricated and subsequently morphologically and electrically characterized with the aim of obtaining statistically significant data. From a manufacturing process viewpoint, the procedures based on inkjet printing herein described are highly attractive: they do not require high temperatures, low pressures, special atmospheric conditions, and any masks, therefore providing a versatile low-cost approach to fabricate passive electrical components and simple circuits useful for the electronic industry. Printing can be carried out at a sufficiently low temperature to avoid damage to the fabric substrate and these devices can be used in a range of applications requiring flexible and conformal devices from embedded passive filters in PCBs to wearable electronics.

This paper presents two main contributions toward efficient VLSI circuits mapped with simple cells: (1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and (2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. We show that efficient implementations in terms of inverter count, transistor count, area, power and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while (i) optimizing the number of added inverters; and (ii) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.

Over the last decades, Organic Electronics has been emerging as a multidisciplinary and innovative way to generate electronic devices and systems. It is intended to provide a platform for low-cost, large-area, and low-frequency Printable Electronics on a variety of substrates, including flexible plastic substrates. Just as the first information revolution caused by integrated silicon circuits, PE is expected to cause another revolution characterized by the distribution of information systems in all aspects of life. Although the integrated circuits, based on Organic Thin Film Transistors (OTFT), are not meant to compete with the silicon-based high-end industry, their performance have already reached to a level enabling the use of organic technology to an ever-increasing number of emerging applications, such as flexible optical displays, sensors, and low-end microelectronics. Currently, most of the digital integrated circuits are yet designed by specifying the layout of each individual transistor and their interconnections. Full-custom design is extremely labor-intensive, time consuming for complex circuits and it requires advanced computer software in the design process, and several expensive mask sets in the fabrication process. Besides, taking the soft and hard faults at transistor level into account, the yield at system level is expected to be very low, since failure of one transistor causes the entire circuit to fail. This is more important for technologies based in non-crystalline materials (such as silicon) in which deposition and layer formation is more irregular. On the other side, organic electronics is more complex than Printed Circuit Boards (PCB) in the sense that these do not include active devices and do not reach high integration level. Furthermore, similar to any new-born technology, the performance of organic electronic circuits is degraded due to some limitations in technological and materials sides. That being said, the question arises as to whether circuit design techniques can be employed to compensate these bottlenecks so as to meet yield and performance requirements. The work presented in this thesis contributes to overcome the above-mentioned issues by proposing the novel concept of Inkjet-configurable Gate Array (IGA) as a designmanufacturing method for the direct mapping of digital functions on top of new prefabricated structures. IGA brings together the advantages of semi-custom gate array methodology, field-configurability, and fault-tolerance, and adopt it to Application Specific Printed Electronic Circuit (ASPEC), which is the equivalent term to Application Specific Integrated Circuit (ASIC), but for PE. This alternative has two main advantages. Firstly, it allows implementing individual circuit personalization at a very low cost through the best use of additive mask-less digital printing techniques (e.g. Inkjet, Superfine Jet, and etc.) "in the field", thus avoiding the need for One Time Programmable ROM-like (or E2PROM) devices. Secondly, fault tolerance technique allows the adoption of a failure map to use only working transistors for circuit implementation, thus, it helps to obtain high yield circuits out of mid-yield foils.

This paper discusses the modeling of patent claims in ontology based representation of patent information. Our contributions relate to the internal structure of the claims and the use of the all-element rule for patent coverage. Starting from the general template for the structure of the claim, we present contributions to (1) visualization of claims, (2) storing claim information in a web semantics framework, and (3) evaluating claim coverage using Description Logic.

This article describes the web application called S3Doodle. It is an initial example of the combination of a stereoscopic graphical user interface that produces stereoscopic content and is controlled by hand gestures. The web application uses core stereo 3D concepts and implements them with cutting edge technology to create a differentiated experience. We use a spatial input control as an interface that allows us to introduce depth into the created compositions. S3Doodle’s creation is documented, and the experience we had while building it is explained, shedding light on which are the technical decisions behind. We also gather user’s comments from the utilization of the web app. This application serves us as a case study for exploring gestural and stereo interactions, from which we get initial reactions upon which we can provide a better experience for future applications.

Detection of QRS complexes in ECG signals is required to determine heart rate, and it is an important step in the study of cardiac disorders. ECG signals are usually affected by noise of low and high frequency. To improve the accuracy of QRS detectors several methods have been proposed to filter out the noise and detect the characteristic pattern of QRS complex. Most of the existing methods are at a disadvantage from relatively high computational complexity or high resource needs making them less optimized for its implementation on portable embedded systems, wearable devices or ultra-low power chips. We present a new method to detect the QRS signal in a simple way with minimal computational cost and resource needs using a novel non-linear filter.

A process design kit (PDK) or Technology Design kit (TDK) is a set of files which describes manufacturing parameters that are relevant for the designers (fabrication layers, electrical parameters and design rules) for a certain technology of a given foundry. PDKs customize CAD/EDA tools used by designers, providing enough abstraction of technological details to facilitate the design of (organic electronics) circuits. Design rules are a set of geometric restrictions imposed to the different layers fabricated by the foundry that designers have to respect. By taking the geometric design rules into account, the design engineers address physical layout to develop devices and circuits without the need of a deep knowledge of process and materials. These rules guarantee their manufacturability and enable working circuits with an optimal balance of yield versus integration density. Design rules for inkjet printing are similar to general design rules for photolithographic processes but also need to cope with the failures related to additive printing of inks and related curing. In this paper, parameterizable cells (PCells) have been used to automate the generation of a complete set of structures to formalize and arrive at technology-independent design rules. A set of test vehicles has been designed, printed and characterized demonstrating the methodology to comprehensively capture the design criteria for inkjet printing technology. For improving design rules and scaling down device dimensions, we present a design approach that combines pre-patterned, high-resolution substrates with digital inkjet fabrication as a demonstration of the capabilities of combining inkjet with other fabrication technologies.

Pedestrian detection is a vital function of the emerging autonomous vehicle industry. HOG is widely used as the feature extractor for pedestrian detection thanks to its high accuracy despite the fact that it is computationally expensive. Hardware accelerators using GPUs or FPGAs are used in several proposals to address its real-time execution. There is always a trade-off between real-time processing, energy efficiency and accuracy in the existing solutions. In this paper, we present a pipelined implementation of HOG feature extraction on a low-cost Cyclone V SoC FPGA platform. The design is provides a latency of 4ms for every 640×480 input frame, which corresponds to 250fps. The whole detection system reduces the power consumption by 53.3% and 96% compared with state of the art FPGA and GPU alternatives.

Constant monitoring of gait in real life conditions is considered the best way to assess Fall Risk Index (FRI) since most falls happen out of the ideal conditions in which clinicians are currently analyzing the patient's behavior. This paper presents the WIISEL platform and results obtained through the use of the first full-wireless insole devices that can measure almost all gait related data directly on the feet (not in the upper part of the body as most existing wearable solutions). The platform consists of a complete tool-chain: insoles, smartphoneamp; app, serveramp; analysis tool, FRI estimation and user access. Results are obtained by combining parameters in a personalized way to build individual fall risk index assessed by experts with the help of data analytics. New FRI has been compared with standards that validate the quality of its prediction in a statistically significant way. That qualitatively relevant information is being provided to the platform users, being either end-users/patients, relatives or caregivers and the related clinicians to ideally assess about their long term evolution.

In this paper we focus on the creation of a tool that alows us to put stereoscopic depth into a web page. We also explore with an experiment to what extent this stereoscopic depth may control a user's gaze pattern while performing a search task. The tool uses HTML5 to create 3D stimuli compatible with stereo displays. The stimuli created consists of a search engine result page created in a 2D and 3D side by side format. We then test the stimuli with eye tracking equipment and perform a questionnaire that gathers information about participants' opinion towards a stereoscopic 3D experience. While this experiment is a first pilot and more research is needed, it is indicative of user behavior. In this paper we describe preparations for the study, hardware and software tools used to carry out the experiment, and results analysis.

The operational stability of all-inkjet printed transistors is reported. At room temperature the threshold voltage shifts following a stretched exponential with a relaxation time τ=1x103 s. Two distinct trap sites active in different temperature ranges, one at 200-250 K and other above 310 K cause the electrical instability. Both types of traps capture holes and can be fast neutralized by photogenerated electrons. Optically induced detrapping currents confirm the differences in trap signature. It is proposed, that the traps have a common physical origin related to water.

Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network-on-chip (NoC)-based multiprocessor systems-on-chip (MPSoCs) platforms. In these type of systems, the overall system performance may be affected due to congestion, and therefore parallel programming stacks must be assisted by quality-of-service (QoS) support to meet application requirements and to deal with application dynamism. In this paper, we present a hardware-software QoS-driven reconfigurable parallel computing framework, i.e., the NoC services, the runtime QoS middleware API and our ocMPI library and its tracing support which has been tailored for a distributed-shared memory ARM clustered NoC-based MPSoC platform. The experimental results show the efficiency of our software stack under a broad range of parallel kernels and benchmarks, in terms of low-latency interprocess communication, good application scalability, and most important, they demonstrate the ability to enable runtime reconfiguration to manage workloads in message-passing parallel applications.

The benefits of stereoscopic vision in medical applications were appreciated and have been thoroughly studied for more than a century. The usage of the stereoscopic displays has a proven positive impact on performance in various medical tasks. At the same time the market of 3D-enabled technologies is blooming. New high resolution stereo cameras, TVs, projectors, monitors, and head mounted displays become available. This equipment, completed with a corresponding application program interface (API), could be relatively easy implemented in a system. Such complexes could open new possibilities for medical applications exploiting the stereoscopic depth. This work proposes a tool for production of interactive stereoscopic graphical user interfaces, which could represent a software layer for web-based medical systems facilitating the stereoscopic effect. Further the tool's operation mode and the results of the conducted subjective and objective performance tests will be exposed.

We present a new Placement and Routing (P&R) strategy for implementing digital Organic/Flexible/Printed Electronics (PE) circuits based on an Inkjet-configurable Gate Array (IGA) design style together with digital printing personalization.

We perform clustering over the Product Reactions Cards in order to group the terms in 8 groups and 41 subgroups. A card sorting exercise among software engineers and UX practitioners was performed in order to achieve this. We present a preliminary case study using this classification with a retailing application in order to see the difference in connotations that result introducing stereoscopic depth to the GUI.

This paper presents the development of a complete end-to-end solution for the broadcast of Multi-Stream Multi-view Real-Time Life Video Content that makes use of the new chips implementing full-spectrum receiver chips that can decode up to 16 TV channels simultaneously and pass them to the video processing chips of the Set-Top Boxes. Managing that complex video content from a user’s perspective requires adding interactive ways to increase user experience.Interactivity can either be directly managed on the main screen through the Set Top Box or on a Second Screen that is wireless connected to the Set Top Box. Several underlying technologies have been implemented that involve: the production head ends that include adding time stamps in the protocol for synchronizing streams and views; the GStreamer technology for scaling videos in real-time and the responsive design used for the 2nd screen apps management.

Learnability is a fundamental usability factor. It is included in several well known and widely used software usability evaluation models such as: IBM’s Computer Usability Satisfaction Questionnaire (CUSQ), System Usability Measurement Inventory (SUMI), System Usability Scale (SUS), and others. However, all of them assess learnability only subjectively. Taking into account the fact of presence of differences in perceived duration in interaction between human and computer, development of a new approach targeting usability, as well as learnability, in objective measures could be of great interest. This paper describes our endeavour in pursuing this task. We present our approach to the problem, introduce an instrument for calculating objective learnability out of times of completion, and reveal results of a user study among 101 participants conducted to test adequacy of the method.

Inkjet printing is a promising and challenging technique that could potentially revolutionize large area and organic electronics fabrication. Inkjet systems are designed to construct devices and circuits drop by drop, which would lead to a new paradigm in electronics fabrication. However, inkjet technology for Printed Electronics is still under development and several challenges remain. While there is significant progress being made in the development of electronic devices, such as transistors or sensors, there is a lack of work on circuit and system level design. Designing devices and circuits implies a wide knowledge of process aspects, requiring a complex interaction among concepts, tools and processes coming from different science and engineering disciplines. An explicit methodology is needed to separate design from fabrication in a similar way as in silicon design, to design devices and systems without a deep knowledge of process and materials; thus making it possible to open up inkjet technology to a larger community and undergo more rapid design implementations. In this paper we present the main aspects of such a methodology and we discuss the key topics on inkjet technology that allow us to propose these new specific steps.

Embedded multimedia devices are now a common element of our environment, such as mp3 players, handheld devices, and so on. Choosing the right main processing element is a key issue for the success of these devices, and their consumption, performance, retargetability, and development time are some of the elements that need to be analyzed and well-balanced. In this paper, we map the same multimedia application (MPEG-4 main profile) into various target platforms generally used in the embedded area. The design flow of our work starts with a single MPEG-4 encoder description which is later refined and optimized to be implemented on different platforms: an embedded platform formed by a high performance digital signal processor and an embedded processor, an application specific instruction processor, a specific hardware implemented in a field-programmable gate array for accelerating the data-flow part of the system with a soft-core for the control part, and an application specific integrated circuit. The main contribution of this paper is to illustrate a methodology that can be generalized to different data dominant applications. This paper describes a new methodology to obtain near optimal implementation from concept to silicon for all platforms and it can be extended to any hybrid HW/SW multimedia platform. We evaluate the different transformations of each platform to arrive at an optimal implementation. These higher level transformations allow achieving better results than using more precise efforts in mapping the design in the physical level. This methodology can be extended to any data dominant application.

Nowadays embedded systems are growing at an impressive rate and provide more and more sophisticated applications characterized by having a complex array index manipulation and a large number of data accesses. Those applications require high performance specific computation that general purpose processors can not deliver at a reasonable energy consumption. Very long instruction word architectures seem a good solution providing enough computational performance at low power with the required programmability to speed up the time to market. Those architectures rely on compiler effort to exploit the available instruction and data parallelism to keep the data path busy all the time. With the density of transistors doubling each 18 months, more and more sophisticated architectures with a high number of computational resources running in parallel are emerging. With this increasing parallel computation, the access to data is becoming the main bottleneck that limits the available parallelism. To alleviate this problem, in current embedded architectures, a special unit works in parallel with the main computing elements to ensure efficient feed and storage of the data: the address generator unit, which comes in many flavors. Future architectures will have to deal with enormous memory bandwidth in distributed memories and the development of address generators units will be crucial for effective next generation of embedded processors where global trade-offs between reaction-time, bandwidth, energy and area must be achieved. This paper provides a survey of methods and techniques that optimize the address generation process for embedded systems, explaining current research trends and needs for future.

While silicon based technologies are evolving towards very advanced nanometric nodes (≤ 20nm), the emerging thin-flexible-organic-large-area electronics (a.k.a. printed electronics, PE) based on flexible substrates and functional inks are starting again the history of microelectronics at technology and device levels trying to grow up to applications looking at the silicon path but far away from its costs and performances.

In this article, we present a drawing toolkit developed to create stereoscopic side-by-side 3D stimuli. The toolkit is based in the HTML5 canvas element and drawing is achieved using intermediate stereo scripting methods that correspond to the ‘2d’ context of the canvas. We include performance marks of the toolkit running on desktop and mobile browsers. Also, a discussion of how the tool is used for implementing a stereo 3D UI is specified.

Creating the layout of an application graphical user interface is an important part of any system development process. Mock-ups, usability studies, focus groups and sketching are techniques that help define this layout and ship the best UI for the required task. But with the addition of 3D depth into the GUI assortment, a gap is exposed when trying to draft the GUI due to the fact that depth cannot be easily represented using traditional 2D methods like paper or existing software. With this article we present a tool that allows designers and developers to draft graphical user interfaces that comply with stereoscopic side-by-side formats. The tool is created using the HTML5 canvas element, in conjunction with the browser’s console to live edit any sketch, and created layouts can be saved and shared in devices capable of showing compatible stereoscopic images.

Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

The benefits provided by the stereoscopic vision have been thoroughly studied for more than a century. The results of this research state that S3D, when properly implemented, enhances efficiency of different applications. At the same time, the market of 3D-enabled technologies is blooming, revealing new devices to the public. 3D cameras, TVs, projectors, monitors, and mobiles are becoming more and more affordable and are not considered as something exotic anymore. Yet this technology is far from being widely implemented. The scarcity of tools for production of such content along with the absence of proper guidelines establishing the rules for S3D depth implementation could be the main reason. With this work we present a tool for generation of interactive stereoscopic HTML compositions. We describe the tool’s operation mode and expose results of the performance test.