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In this work, we present an embedded DRAM utilizing logic-compatible 2T gain cell. The memory cells are composed of a high-V TH write NMOS and a standard read NMOS. Due to the combination of low off-leakage write device and high mobility read device, this NMOS-based hybrid gain cell provides much improved data retention and read performance. At 1.2 V and 85 °C, the proposed bit-cell achieves 1.1× longer standby retention and 4.4× longer write disturbance retention compared to the PMOS-only 2T cell. The memory arrays operate with a logic-compatible supply voltage; /CS controlled 128-row refresh; and nondestructive read with speed comparable to 6T SRAM but 65 % smaller cell area. Design results from a test chip in a 130 nm logic CMOS technology exhibit the effectiveness of the proposed embedded memory techniques.

In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 µm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30 % reduction in read power and 42 % reduction in write power compared to the conventional 6-transistor (6T) SRAM.