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The growing popularity of edgeAI requires novel solutions to support the deployment of compute-intense algorithms in embedded devices. In this article, we advocate for a holistic approach, where application-level transformations are jointly conceived with dedicated hardware platforms. We embody such a stance in a strategy that employs ensemble-based algorithmic transformations to increase robustness and accuracy in Convolutional Neural Networks (CNNs), enabling the aggressive quantization of weights and activations. Opportunities offered by algorithmic optimizations are then harnessed in domain-specific hardware solutions, such as the use of multiple ultra-low-power processing cores, the provision of shared acceleration resources, the presence of independently power-managed memory banks, and voltage scaling to ultra-low levels, greatly reducing (up to 60% in our experiments) energy requirements. Furthermore, we show that aggressive quantization schemes can be leveraged to perform efficient computations directly in memory banks, adopting in-memory computing solutions. We showcase that the combination of parallel in-memory execution and aggressive quantization leads to more than 70% energy and latency gains compared to baseline implementations.

Entering the Big Data era leads to the rapid development of web applications which provide high-performance sensitive access on large cloud data centers. HTTPS has been widely deployed as an extension of HTTP by adding an encryption layer of SSL/TLS protocol for secure communication over the Internet. To accelerate the complex crypto computation, specific acceleration instruction set and hardware accelerator are adopted. However, energy consumption has been ignored in the rush for performance. Actually, energy efficiency has become a challenge with the increasing demands for performance and energy saving in data centers. In this paper, we present the EECA, an Energy-Efficient Crypto Acceleration system for HTTPS with OpenSSL. It provides high energy-efficient encryption through HW/SW co-design. The essential idea is to make full use of system resource to exert the superiorities of different crypto acceleration approaches for an energy-efficient design. Experimental results show that, if only do crypto computations with typical encryption algorithm AES-256-CBC, the proposed EECA could get up to 1637.13%, 84.82%, and 966.23% PPW (Performance per Watt) improvement comparing with original software encryption, instruction set acceleration and hardware accelerator, respectively. If considering the whole working flow for end-to-end secure HTTPS based on OpenSSL with cipher suite ECDHE-RSA-AES256-SHA384, EECA could also improve the energy efficiency by up to 422.26%, 40.14% and 96.05% comparing with the original Web server using software, instruction set and hardware accelerators, respectively.

Nowadays, the growing diffusion of Cyber-Physical Systems brings strict requirements for the cyber-side, managed with complex HW/SW systems. In this paper, we discuss an action research experience to contribute to recent interest from the HCI community in frontier topics, at the intersection with Cyber-Physical Systems. HW/SW designers, experts in their application domain, are often not supported in their specific and daily tasks, as for example those associated to the design of cyber-side HW/SW components of Cyber-Physical Systems. This paper is an invitation to the HCI community to look at HW/SW designers as frontier users to serve. Indeed, the paper mainly describes the design issues raised within the European FitOptiVis project – aiming at developing a framework to support the design of video-based Cyber-Physical Systems – within which the action research experience has been conducted with the goal of supporting designers in the design of some crucial HW/SW components of the cyber-side: the monitoring systems.

This work faces the problem of theElectronic System-Level(ESL) HW/SW co-design of dedicated electronic digital systems based on heterogeneous multi-processor architectures. In particular, the work presents a prototypeSystemC-based environment that exploits aDesign Space Exploration(DSE) approach able to suggest an HW/SW partitioning of the system specification and a mapping onto an automatically defined architecture. The descriptions of the reference HW/SW co-design methodology and the main design issues related to the developed DSE SW tools, supported by two reference use cases that allows to understand the role of the DSE step in the whole design flow, represent the core of the paper.

Heterogeneous parallel devices are becoming widely diffused in the embedded systems application field since they allow to improve time performances and other orthogonal metrics (e.g., cost, power, size, etc.) at the same time. In such a context, the introduction of safety requirements, as dictated by the relevant standards (i.e., DO-178 B/C and RTCA/DO-254 in airborne systems, ARINC 653 for avionics software, ISO-26262 in automotive domain, etc.) while considering shared resources on a heterogeneous parallel HW platform, adds further challenges to industrial and academic research. This kind of platforms that execute tasks with different levels of criticality are commonly called mixed-criticality embedded systems. So, the main problem in their management is to ensure that low criticality tasks do not interfere with high criticality ones. The final goal is to allow several applications to interact and coexist on the same platform. For this, the exploitation of virtualization technologies (i.e., hypervisors) allows to guarantee isolation and to satisfy certification requirements but introduces scheduling overhead and new HW/SW partitioning challenges. In such a scenario, this work focuses on a framework for modeling, analysis, and validation of mixed-criticality and real-time systems based on an existing "Model-Based Electronic System Level HW/SW Co-Design" methodology. The main contribution of this work is the integration of the considered framework with Xamber tool in order to provide systems implementations by exploiting a design space exploration able to consider Xtratum-based SW partitions.

This work focuses on the definition of a methodology for handling embedded real-time applications, starting from an existing HW/SW co-design methodology able to support the design of dedicated heterogeneous parallel systems. The state-of-the-art related to similar tools and methodologies is presented and the reference framework with the proposed extension to the realtime world is introduced. A case study is then described to show a design space exploration able to consider such an extension.

This workfocuses on Design Space Exploration for embedded systems based on heterogeneous parallel architectures and subjected to mixed-criticality constraints. In particular, it presents a criticality-aware evolutionary approach integrated into a reference Electronic System Level HW/SW Co-Design flow

Hardware-software (HW-SW) co-design allows to meet system-level objectives by exploiting the synergy of hardware and software. Current tools and approaches for HW-SW co-design face difficulties coping with the increasing complexity of modern-day application due to, e.g., concurrency and energy constraints. Therefore, an automated modeling approach is needed which satisfies modularity, extensibility and interoperability requirements. Model-Driven Engineering (MDE) is a prominent paradigm that, by treating models as first-class citizens, helps to fulfill these requirements. This paper presents a state-of-the-art MDE-based framework for HW-SW co-design of dataflow applications, based on synchronous dataflow (SDF) graph formalism. In the framework, we introduce a reusable set of three coherent metamodels for creating HW-SW co-design models concerning SDF graphs, hardware platforms and allocation of SDF tasks to hardware. The framework also contains model transformations that cast these models into priced timed-automata models, the input language of the well-known model checker Uppaal Cora. We demonstrate how our framework satisfies the requirements of modularity, extensibility and interoperability in an industrial case study.

The top-down approach to system design allows obtaining separate specifications for each subsystem. In the case of vision systems, this means propagating system-level specifications down to particular specifications for e. g. the image sensor, the image processor, etc. This permits to adopt different design strategies for each one of them, as long as they meet their own specifications. This approach can lead to over-design, which is not always affordable. Conversely, if higher-level specifications are too tight, they can lead to impossible specifications at the lower levels. This is certainly the case for embedded vision systems in which high-performance needs to be paired with a very restricted power budget. In order to explore alternative architectures, we need tools that allow for simultaneous optimization of different blocks. However, the link between low-level non-idealities and high-level performance is missing. CAD tools for the design and verification of analog and mixed-signal integrated circuits are not well suited for the simulation of higher-level functionalities. Our approach is to extract relevant data from circuit-level simulation and to build an OpenCV model to be employed in the design of the algorithm. The utility of this approach is illustrated by the evaluation of the effect of column-wise and pixel-wise FPN at the sensor on the performance of Viola-Jones face detection.

In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation. Verilog, VHDL and C/C++ frontends. Hardware generation in VHDL and BLIF, a retargetable compiler back-end and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts.

RESUMEN: Con este proyecto se pretende realizar un estudio sobre la utilidad del lenguaje SystemC como herramienta de evaluación de sistemas co-diseñados HW/SW para las empresas. Además se intentará preparar al autor del mismo para un perfil profesional acorde a este tipo de trabajos, mediante un estudio en profundidad del lenguaje SystemC y el codiseño de este tipo de sistemas, así como con el aprendizaje sobre la codificación de audio y video. Para ello se ha elegido transformar un sistema en código C para realizar pruebas sobre una posible implementación Hardware de un conversor de audio y video de alta calidad bajo el estándar H.264/MPEG-4. Con esto se pretende crear un sistema software que nos permita simular y verificar el futuro elemento, a nivel de comportamiento y de rendimiento. Como no es posible calcular el rendimiento real del elemento final, estas medidas de rendimiento serán relativas, es decir, no será un rendimiento absoluto sino un speedup del elemento con respecto al código original y al aplicarle diferentes estrategias de mejora. Como H.264/MPEG-4 es un estándar, se utilizará la implementación libre ofrecida por el Fraunhofer Heinrich Hertz Institute como código del que partir para trabajar después. Se realizará un encapsulado de las funciones más importantes en módulos propios de un lenguaje de descripción de Hardware (como pueden ser Verilog o VHDL) y a continuación se realizarán pruebas sobre el sistema para comprobar su funcionamiento correcto. Además de estas pruebas, puramente de comportamiento, para demostrar que el nuevo sistema trabaja igual que el original, también se van a realizar pruebas sobre los distintos elementos para obtener una descripción y un conocimiento más profundo sobre el sistema que estamos creando. ABSTRACT: This project aims to realize and study about the usability of SystemC as an evaluation methodology of HW/SW co-design of systems to companies. Furthermore, the author attempts to prepare a professional profile in this kind of jobs, through the study of SystemC and the HW/SW co-design, as well as learning about audio and video encoding. For that, we have chosen to transform a C code into a future and fiction Hardware encoder under H.264/MPEG-4. We want to create a software system that let us simulate and verify the behavior and performance of the element. As it is not possible to know the final performance, we'll use a reference measure for that. We will use that measure to calculate the speedup about the original code. As H.264/MPEG-4 is a standard, we will use the free implementation offered by the Fraunhofer Heinrich Hertz Institute like initial code. The most important functions will be encapsulated into modules, specifics of a hardware description language (like Verilog or VHDL), and there'll be some tests on the system. In addition of these tests, which only try the behavior of the new system, there'll be some proofs about the elements and modules that compose the final system, to get a high description and knowledge about it. Ingeniería en Informática

This paper presents a prototype environment for HW/SW co--design of embedded systems based on the Unified Modeling Language (UML) and SystemC. The environment supports a model-driven SoC design methodology which provides a graphical high-level representation of hardware and software components, and allows either C/C++/SystemC code generation from models and a reverse engineering process from code to graphical UML models.

Novelty detection is based on the creation of a space with similarity metric. It is discussed that the design of a neural detector is a compromise between promptness, universatility, robustness and sensitivity. The feed-forward topology is chosen from three alternatives for its ability to design that compromise by applying structural redundancy. A generic FPGA implementation supports the use in adaptive intelligent systems.

Novelty detection is based on the creation of a space with similarity metric. It is discussed that the design of a neural detector is a compromise between promptness, universatility, robustness and sensitivity. The feed-forward topology is chosen from three alternatives for its ability to design that compromise by applying structural redundancy. A generic FPGA implementation supports the use in adaptive intelligent systems.

System-level design decisions such as HW/SW partitioning, target architecture selection and scheduler selection are some of the main concerns of current complex system-on-chip (SOC) designs. In this paper, a novel window-based heuristic is proposed that addresses the issue of design space exploration in applications that have a data flow characteristic. The objective in this paper is to partition the application into HW and SW components such that the execution time of the application is minimized while simultaneously satisfying the hard area constraints of the HW units. In this algorithm, the search space is divided into smaller intervals, referred to as windows. For each window the full search is performed to find the optimum partitioning and scheduling solution for that specific window. Moreover, in this paper a novel indexing mechanism is presented for identifying the nodes in the task graph. The proposed index specifies not only the relation of each node with respect to the other nodes in the graph, but also its position in the task graph. With the help of the proposed windowing and indexing techniques, the time required for partitioning is reduced significantly. Simulation results indicate that the proposed algorithm improves the search time by 74% compared to conventional optimization heuristics namely Genetic Algorithm (GA), Simulated Annealing (SA) and Tabu Search (TS), while providing comparable results in terms of the overall execution time of the partitioned system.

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has moved on the number of cores. Consequently, the fundamental feature of system designs and their associated design flows and tools need to change, so that, to support the scalable parallelism and the design portability. The same feature can be exploited to design reconfigurable hardware, such as FPGAs, which leads to rethink the mapping of sequential algorithms to HDL. The sequential programming paradigm, widely used for programming single processor systems, does not naturally provide explicit or implicit forms of scalable parallelism. Conversely, dataflow programming is an approach that naturally provides parallelism and the potential to unify SW and HDL designs on heterogeneous platforms. This study describes a dataflow-based design methodology aiming at a unified co-design and co-synthesis of heterogeneous systems. Experimental results on the implementation of a JPEG codec and a MPEG 4 SP decoder on heterogeneous platforms demonstrate the flexibility and capabilities of this design approach.

The Zynq-7000 based platforms are increasingly being used in different applications including image and signal processing. The Zynq system on chip (SoC) architecture combines a processing system based on a dual core ARM Cortex processor with a programmable logic (PL) based on a Xilinx 7 series field programmable gate arrays (FPGAs). Using the Zynq platform, real-time hardware acceleration can be performed on the programmable logic and controlled by a software running on the ARM-based processing system (PS). In this paper, a design and implementation of a gas identification system on the Zynq platform which shows promising results is presented. The gas identification system is based on a 16- Array SnO2 gas sensor, principal component analysis (PCA) for dimensionality reduction and decision tree (DT) for classification. The main part of the system that will be executed on the PL for hardware acceleration takes the form of an IP developed in C and synthesized using Vivado High Level Synthesis for the conversion from C to register transfer level, a hardware design for the entire system that allows the execution of the IP on the PL and the remaining parts of the identification system on the PS is developed in Vivado using IP Integrator. The communication between the processing system and programmable logic is performed using advanced extensible interface protocol (AXI). A software application is developed and executed on the ARM processor to control the hardware acceleration on the programmable logic of the previously designed IP core and the board is programmed using Software Development Kit. The maximum accuracy achieved by the system to classify three types of gases CO, C2H6O and H2 is 96.66%. 2006-2015 Asian Research Publishing Network (ARPN). This paper was made possible by National Priorities Research Program (NPRP) grant No. 5 - 080 - 2 - 028 from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors. Scopus

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. We also present an automated way to perform NoC features exploration using the interaction HW/SW on an FPGA. Our experimental results show a speed-up of four orders of magnitude with respect to cycleaccurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.