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©2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Fourth-generation (4G) communication systems based on orthogonal frequency division multiplexing (OFDM) and the proposed backwards compatible fifth-generation (5G) variants, like filter-bank multicarrier (FBMC), are based on modulation techniques that allow significantly increased spectral efficiency and capacity in mobile radio access networks (RANs). However, the use of these modulation techniques impacts the requirements of the radio base stations, which have been traditionally the most energy-consuming element of mobile networks, accounting for up to 80% of the energy consumption of RANs [1]. Non-constant envelope-modulation techniques with high peak-to-average power ratios (PAPRs) require highly linear power amplifier (PA) amplitude and phase responses to fulfill stringent spectral mask and modulation accuracy requirements. This is often achieved with significant PA back-off, which considerably reduces PA efficiency because the PA's maximum efficiency is achieved near the saturation point.

This paper shows the implementation in a digital signal processor (DSP or FPGA) of a Digital Adaptive Predistorter (DAPD) for power amplifier (PA) linearization based on a Nonlinear Autoregressive Moving Average (NARMA) structure. The distinctive characteristic of this DAPD is its straightforward deduction from the NARMA PA model, without the need of using an indirect learning approach to identify the DAPD function. The DAPD itself presents a NARMA structure, and hence it can be quickly implemented by means of Look-Up Tables (LUTs). WCDMA modulated signals, collected from a 3-stage LDMOS class-AB power amplifier, with a maximum output power of 48 dBm CW have been used to validate the linearizer performance. The developed DSP and FPGA based platform for prototyping digital predistortion linearizers eases the process of meeting transmission linearity requirements, depending of the degree of impairments added by the transmitter chain, and enables a quick migration between different DAPD schemes. Details on the internal DAPD organization and abilities are provided, giving an insight on actual development scenarios of predistorter systems considering memory effects. Experimental results obtained from the linearization of a 10 W class-AB LDMOS amplifier (2 GHz band) are provided.

This paper presents an Envelope Tracking Pow- er Amplifier whose architecture includes a Hybrid Envelope Amplifier (HEA) and an algorithm to adapt the envelope’s characteristics to the HEA’s limitations. The HEA attempts to combine the high efficiency of a switched amplifier with the wide band capabilities of a linear amplifier. A modified Slew Rate (SR) reduction algorithm cope with the bandwidth and SR limitations of the HEA. On the other hand, the non-linearities introduced by this Envelope Amplifier (EA) and by the dynamic supply are compensated using Digital Pre-Distortion. Results show that these non-linearities are compensable and that the architecture offers higher efficiency figures compared to the conventional linear EA

This paper presents a comparative study on the suitability of using Hammerstein or Wiener models to identify the power amplifier (PA) nonlinear behavior considering memory effects. This comparative takes into account the operational complexity regarding the identification process as well as their accuracy to follow the PA behavior. Both identified PA models will be used to estimate a Hammerstein based predistorter in order to see which model combination provides better linearization results. In addition, two adaptive algorithms for predistorting both PA models are compared in terms of accuracy and converge speed.

With the increasing demands for higher data rate, wider signal bandwidth is required, and this imposes high sampling rate converters in the communications equipment. This paper provides and analyzes experimental results obtained from testing some of the most promising techniques able to reduce the sampling rate speed of the Analog to Digital Converters and Digital to Analog Converters to be used in the implementation of Digital Predistorters. In a first section, an overview of several of the recently published sampling rate reduction techniques is done, and later it’s included a section where the author’s activities related to the digital predistortion of wideband signals are explained, and some of their last research activities and results in sampling rate and bandwidth reduction are provided.

This paper presents a multiple LUT digital adaptive predistorter based on a Hammerstein model that uses the return channel to feed back information from the receiver, concretely the bit error rate (BER), in order to train and later adapt the specific LUT gains that permit always operating at the best back-off level. This new predistorter architecture is aimed at coping with modern communication standards that use adaptive modulation (such as IEEE 802.11 or IEEE 802.16) and therefore continuously searching the best linear amplification to maximize power efficiency at the time that a certain quality of service (BER) in reception is guaranteed. Simulations provided will show the advantages of this multi-LUT configuration, where in front of different channel conditions, linear and efficient amplification (minimum back-off) is achieved at the time that a certain level of BER at reception is ensured. Index terms – Lookup tables (LUT), digital adaptive predistortion, Hammerstein models, adaptive modulation systems, peak to average power ratio (PAPR), bit error rate (BER).

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

A Doherty power amplifier (DPA) is an effective structure born in 1936 which, after a scarce revival around year 2000), had been strengthened from 2005 because its capability to combine linear amplification with power efficiency. Despite the conceptual simplicity of its basic operation, a lot of practical drawbacks shrink the theoretical behavior, thus leading a significant number of research works to overcome them. The main objective in DPA research is to increase efficiency while maintaining linearity and filling the specified bandwidth. This paper presents a survey of the state of the art of DPA advanced design aspects. After a short review of the DPA operation principles, aspects regarding improvements for linearity, power efficiency and amplification bandwidth are introduced. Besides, some alternative structures and technologies, as well as practical design aspects and some trade-offs which the designer usually has to face are also presented.

This paper analyzes different resource management strategies for SDR base stations implemented as SDR clouds. SDR clouds describe distributed antennas that connect to a data center for digital signal processing. The data center employs cloud computing technology, providing a virtualized computing resource pool. The service area of a single SDR cloud may be a medium sized metropolitan area with a high user density. Hence, the data center will execute thousands of SDR applications—waveforms associated to different radio cells—in parallel. Whenever a user initiates or terminates a wireless communications session, computing resources need to be allocated or deallocated in real time. We therefore propose a hierarchical resource management approach and present simulation results that demonstrate its feasibility

The use of digital predistortion for linearizing a millimeter-wave power amplifier (PA) is investigated. A PA operating at 38 GHz is designed using an accurate non-quasi-static transistor model, taking into account both short- and long-term memory effects. A realistic test signal is then used for the identification of a nonlinear auto-regressive moving average (NARMA) behavioral model of the PA. The NARMA-based digital predistorter is then derived and formulated in terms of basic predistortion cells, especially suitable for efficient implementation in an FPGA. The performance of the predistortion solution is preliminarily assessed by means of computer simulations.

In this paper, an overview of emerging techniques for overcoming the current limit in the solution to the linearity versus efficiency trade-off in wireless transmitters is presented. Starting with the combination of digital predistortion and impedance synthesis techniques for dealing with wideband communication formats in I/Q transmitters, the attractive capability of envelope tracking for improving average efficiency in those architectures with available technology is highlighted. Finally, and due the intrinsic limitations of the Cartesian transmitter, the polar concept is considered. Its nonidealities are put under analysis, as they may restrict current introduction of this promising architecture. The solutions under consideration are due to the joint work from the groups of Univ. Cantabria, Univ. Zaragoza and Univ. Polit. Cataluña (UPC) under a Coordinated Project from the Spanish National Plan.

With the rise of modular system architecture for distributed satellite systems with multiple small payloads instead of conventional larger spacecrafts, the efficient characterization of power budget and available power constraints become even more vital. In order to establish high data rate downlink com munications in small satellite applications, use of highly efficient, non - conventional power amplification techniques is going to be a key factor in future communication systems. The concept of having small, less power consuming and high data rate transmis sion system extends to vast number of applications like light weight Unmanned Aerial Vehicle (UAV) and hand - held communication modules etc. The idea is to study and develop an adaptive envelope tracking technique which should be able to dynamically supply power to Radiofreq uency power amplifier. Consequently, a n optimal control over system power consumption leads to enhanced efficiency. The amplifiers intended for such systems exhibit nonlinear behavior when it comes to operating at maximum output power an d cause distortion in adjacent bands. Introducing a power supply modulation block in combination with digital linearization techniques such as DPD offers considerable improvement. Th is thesis tests a dynamic power supply adaptive shaping technique f or LTE signals. In comparison to conventional fixed supply RF PAs, Envelope Tracking PA has resulted in improved linearity at the output as well as reduced unwanted power leakage into adjacent frequency channels. By imposing an isogain trajectory trough th e shaping function, we can optimize the available power for high data rate communications while keeping the intermodulation distortion at acceptable levels by considering a tradeoff between efficiency and computational load

Nowadays, the Unmanned Aerial Vehicle (UAV) become more and more popular in aerial photography, especially in mini and micro size UAV. The UAV used for aerial photography usually use a high power video transfer communication block to send the real time video signal to the ground station, which is high power consuming. It is important to increase the power efficiency of on-board communication system for improving the endurance of small-scale UAVs. The power amplifier (PA) is the most power consuming component among all the units in communication system. Given the nature feature of the PA, it tends to be either linear response or higher power efficiency, but rarely both. The PA with high power efficiency always has a horrible non-linear distortion performance that discards its use. There are several available linearization methods to compensate the non-linear behavior of PA. Among them the digital predistortion (DPD) method is widely used with the development of digital electronic technology. However, the design cost of DPD block itself should be taken into consideration. The DPD linearizer requires a feedback path to monitor the PA behavior and the analog to digital convertor (ADC) is a critical component from the cost and efficiency point of view. The price of ADC makes a prominently contribution to the total cost of DPD linearizer. The price of the ADC is usually proportional to the sampling frequency, which, according to the Nyquist-Shannon sampling theorem, should be higher than twice the bandwidth of the communication's signal. In this thesis, we will present an under sampling method and its supporting algorithm aimed to decrease the frequency rate requirements of the ADC to perform the DPD linearization. In this way, ADC with lower sampling frequency is able to be used in the DPD feedback loop and thus decrease the total cost without compromising the linearization performance. The theoretical analysis will be first presented in this thesis and then experimental results showing the performance of the DPD with under-sampling method will be shown and discussed.

The PA is one of the most important subsystems of the RF transmitter and it is responsible of the main part of the overall transmitter's power consumption. In order to increase the efficiency of the PA, this project proposes designing in a FPGA adaptive filtering techniques to update the coefficient of digital predistortion linearizers. More precisely, the least squares (LS) algorithm is design to be implemented in soft-core processor as the Xilinx MicroBlaze, while the least mean squares (LMS) algorithm is design for real-time operation in the FPGA. The experimental results obtained show a promising performance of the multi look-up table (M-LUT) based digital predistorter (DPD). Good linearity levels are reported. However, an exhaustive study on the required arithmetic resolution has yet to be carried out in order to mitigate the quantization noise and lead to a higher performance of the DPD using these kind of quadratic minimization algorithms.

Design of FPGA Mezzanine Card VITA 57 compatible. VHDL programmation over FPGA carrier SPEC and ADC characterization

Aquest TFC consisteix en l'estudi i desenvolupament en matlab d'algunes de les tècniques de reducció de la potència de pic dels senyals OFDM. L'objectiu és la reducció del peak-to-average power ratio (PAPR)dels senyals a fi d'obtenir una amplificació en el transmissor que sigui, no tant sols lineal, sinó que també el més energèticament eficient possible.

An adaptive filter is a device that attempts to model the relationship between signals in real time in an iterative way. Among all the adaptive filters, the most outstanding among them is the Least Mean Square (LMS). Least Mean Square was created in 1960 by Professor Bernand Widrow and his student Ted Hoff. Least Mean Square is used to calculate the coefficients from the desired output signal with the output signal that we obtain from the coefficients that we have calculated. The LMS has several ways to get its coefficients: LMS, NLMS, Sign-LMS, etc. NLMS, normalize the input signal when we calculate coefficients and the Sign-LMS from the input signal, when calculating the coefficients and Sign-LMS from the input signal, error or both at once, where if the number is positive we will give value equal to 1 and if we obtain a negative number, the value is -1. With each form of LMS, we can see who is the fastest when it comes to obtaining coefficients or we can also which one has the least error.

El TFC consistirà en el disseny i posterior implementació en DSP's d'un predistorsionador digital per a la linealització d'amplificadors de potència. El TFC es dividirà en tres parts: - Període de documentació i aprenentatge de la predistorsió digital - Elaboració d'un model de predistorsionador en MATLAB - Implementació del predistorsionador en un Processador de Senyal Digitals (DSP). La predistorsión digital es una técnica para la linealización de amplificadores de potencia. Los amplificadores de potencia son dispositivos activos presentes en las etapas de potencia de los sistemas de comunicación RF y consumen gran parte de la energía disponible (alrededor de un 70%). Interesa pues aprovechar al máximo su eficiencia energética. Sin embargo, si se trabaja en las zonas donde la eficiencia es mayor, el amplificador de potencia se comporta de forma muy no lineal, introduciendo distorsión dentro y fuera de banda que no es fácilmente eliminable mediante el filtrado. El compromiso entre linealidad y eficiencia está presente en el diseño de los amplificadores de potencia, ya que el conjunto del sistema de comunicaciones debe cumplir las recomendaciones propuestas por los diferentes estándares de comunicación. Para conseguir el objetivo de maximizar ambas características, se están investigando numerosas técnicas de linealización. Una de ellas es la predistorsión digital que puede ser implementada en un procesador DSP (Digital Signal Processor) ya presente actualmente en muchos sistemas de comunicación. El proyecto de fin de carrera aquí presentado ha consistido en desarrollar un predistorsionador digital basado en el modelo de Hammerstein (con sus variantes FIR e IIR) en el entorno del procesador DSP C6711. Primero, se ha obtenido el modelo de comportamiento (behavioral model) paso bajo de un amplificador de potencia a partir de las muestras de entrada y salida medidas en un amplificador real. Posteriormente, una vez estimado el modelo paso bajo (de envolvente compleja) del amplificador, se ha procedido a la estimación del modelo del predistorsionador. Para ello, se han utilizado las mismas muestras de entrada y salida medidas, así como un método de estimación indirecto a fin de no necesitar el modelo del amplificador para estimar el modelo del predistorsionador, evitando así, una posible acumulación de errores. Por otro lado, se han generado secuencias pseudo-aleatorias de símbolos para las diferentes modulaciones M-QAM (de 8 a 64) y se han suavizado con un filtro RRC (Root Raised Cosine). Estas muestras se han aplicado al modelo estimado del amplificador de potencia para disponer de muestras de salida del amplificador. Las muestras de entrada y salida del amplificador han permitido estimar nuevos coeficientes del predistorsionador. Pensando en una futura implementación del predistorsionador en una FPGA, donde los coeficientes del modelo del predistorsionador se deben actualizar continuamente, se ha implementado el modelo del predistorsionador mediante unas tablas de ganancia compleja denominadas Look-Up-Tables (LUTs). Las LUTs permiten de una forma rápida asignar la ganancia compleja correspondiente a cada valor de la señal de entrada del predistorsionador, aplicando así correcciones en el módulo y en la fase de la señal de entrada. El resultado es una relación lineal entre la entrada y la salida de las etapas predistorsionador y amplificador de potencia. Se han hecho las simulaciones necesarias para verificar el correcto funcionamiento de la estimación del amplificador de potencia y del predistorsionador con LUT, aportando resultados y conclusiones al respecto.

Este TFC se centra en el diseño de un linealitzador de Predistorsión Digital (Digital Predistortion - DPD) capaz de compensar la dinámica y los efectos no lineales introducidos por los amplificadores de Potencia (Power Amplifiers - PAS). Uno de los rasgos más relevantes de este predistorsionador digital y adaptativo consiste en ser deducible a partir de un modelo de PA llamado Nonlinear Auto-Regressive Moving Average (NARMA). Además, su arquitectura multi-LUT (multi-tabla) permite la implementación en un dispositivo Field Programmable Gate Array (FPGA). El hecho de que este DPD tenga en cuenta los efectos de memoria introducidos por el PA, representa una clara mejora de las prestaciones conseguidas por un simple DPD sin memoria. En comparación con otros DPDs basados en modelos computacionalmente más complejos, la estructura recursiva del DPD propuesto permite reducir el número de LUTs necesarias para compensar los efectos de memoria del PA. En una primera aproximación al diseño del DPD, es necesario identificar el modelo NARMA del PA. Uno de los mayores ventajas que presenta el modelo NARMA es su capacidad para encontrar un compromiso entre la fidelidad en la estimación del PA y la complejidad computacional introducida. Una vez obtenido el modelo NARMA del PA, se procede a la obtención de la función de predistorsión a través del método de identificación predictivo. Este método se basa en la continua identificación del modelo NARMA del PA y posteriormente, a partir del modelo obtenido, se fuerza al PA para que se comporte de manera lineal. Para poder implementar la función de predistorsió en la FPGA, es necesario primero expresarla en forma de combinaciones en paralelo y en cascada de las llamadas Celdas Básicas de Predistorsión (BPCs), que son las unidades fundamentales que componen el DPD. Una BPC está formada por un multiplicador complejo, un puerto RAM dual que actúa como LUT (tabla de registros) y un calculador de direcciones. Las LUTs se indexan mediante el módulo de la envolvente de la señal.

Objective of modern small satellite communication is to provide the end users with higher data rate downlink capability, in addition to, reliability and system efficiency. A significant device, with respect to power consumption and influence on system linearity, use in the transmission chain of small satellites, is power amplifier. The power amplifier tends to add distortion and non-linearity in the transmitted signal, when operating close to saturation point. For avoiding the non-linearity addition by the PA, it should be operated in linear region which causes the degradation in power efficiency. Therefore, for having the maximum power efficiency and improving linearity, the predistortion should be performed before inputting the signal to power amplifier. For compensating non-linear distortion, linearization scheme based on digital predistortion is used, which requires a feedback path for adaptation and extraction of new coefficients for DPD. Hence for making the DPD adaptive, ADC is required to add in the system. As a consequence of performing digital predistortion, the spectral regrowth occurs which causes the increase in bandwidth up to five times of original signal. Due to this reason, digital to analog converter has to sample the signal at five times of nyquist frequency which increases the cost and power consumption of DAC. This master thesis presents the methodology implementation for compensating the non-linear distortion in PAs, applicable for small satellite communication, with a cooperative technique of digital and analog predistortion. This thesis provides with the solution for the increased sampling rate of signal at analog to digital converter with a use of combination of digital and analog predistortion. The predistortion (digital and analog) is design to focus on maximizing the linearity and minimizing the distortion and spectral regrowth. While the adaptive scheme of combined digital predistortion and analog predistortion (simulated) is designed, with an ideal low-pass filter between them, for implementation ease of the digital-to-analog converter and decrease in signal sampling rate. The results provided in the thesis have shown that same linearity and efficiency can be achieved at amplifier's output by implementing the above mentioned solution with a benefit of reducing the signal sampling frequency at DAC. A comparative analysis of power amplifier behavior in various configuration is presented in the dissertation.

Este proyecto pretende implementar en una FPGA la transmisión y recepción de datos. Estos datos se transmitirán modulados en amplitud por cuadratura (QAM) o por división ortogonal en frecuencia (OFDM), implementando todo ello de la manera más eficiente posible. Se programarán tres niveles diferentes para la modulación de datos: 4-QAM, 16-QAM y por último 64-QAM. La programación de una FPGA utiliza un lenguaje VHDL. Para desarrollar todo el sistema utilizaremos las librerías System Generator de Xilinx, que permite hacer simulaciones reales de diseños basados en FPGAs mediante modelos de Simulink. Estos modelos, realizados con los bloques que se suministran, generan de forma automática una implementación basada en VHDL. Una vez diseñado el sistema se podrá simular y visualizar los resultados mientras la simulación se está ejecutando, y además, se podrá transferir los resultados al espacio de trabajo Matlab, dónde será posible cambiar los parámetros y de forma inmediata, visualizar éstos cambios. Se utilizarán los bloques proporcionados por el System Generator porque, además de hacer su función, no utilizan muchos más recursos de los necesarios. Para probar el buen funcionamiento del sistema de manera teórica, se ha implementado un sistema de modulación y demodulación de señal que comprende dos modos: Single-carrier y multi-carrier. De esta manera se puede comprobar de manera teórica antes de enviar los datos a la FPGA donde el funcionamiento debería ser similar al teórico para el buen funcionamiento del sistema y la posterior funcionalidad del sistema total. Como parte final de este proyecto y parte principal, la transmisión de esta señal se hará en polares utilizando la técnica EE&R para maximizar la eficiencia del amplificador o bien la técnica Envelope Tracking.

The increase in the demand for wireless communications from the user-end point of view calls for an infrastructure that is constantly more capable, reliable and efficient. One of the critical nodes in the telecommunications process, from the hardware perspective, is the power amplifier (PA): it is not only the more powerconsuming device in the transmission chain but it also has a highly nonlinear behaviour which can compromise the well-functioning of the communications infrastructure. This thesis addresses the digital predistortion (DPD) technique, whose goal is to reduce the nonlinear influence of the PA in the transmitted signal, and enhances it with two contributions which can allow for a bigger computational and economic efficiency without compromising the effectiveness of DPD. These contributions are the Reduced Observational Bandwidth and the Reduced Model Order. In the former, the observational path required for the implementation of the DPD is redesigned to permit the capture of wideband signals using multiple reduced bandwidth observations. The latter, on the other hand, aims at reducing the number of coefficients needed for DPD by discarding the less contributive modes of the PA behavioural model. Additionally, the technique of reducing the signal PAPR is applied in order to seek a more effective predistortion. The experimental campaign in a real DUT proved that the reduction of the observational bandwidth was feasible and produced similar results when compared to a full spectrum observation.