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This paper presents a new mission concept and details its system design for Earth observation, utilizing fractionated payloads onboard CubeSats to meet the Sentinel-2 mission specifications at lower costs with enhanced scalability and robustness characteristics. The fractionated spacecraft system consists of twelve CubeSats, each in an eight-unit form factor, which is responsible for taking raw images and sending them to a mothership, while the mothership constructs wide-range images and transmits them to Earth. The pre-Phase-A design of the CubeSats is detailed using available off-the-shelf components with flight heritage. The performance and failure analyses of the proposed fractionated system compared to its Sentinel-2 counterpart, using Monte-Carlo simulations, indicate that the scalability and robustness of the mission can be enhanced while achieving similar specifications. Moreover, the mass and cost analyses show that they can also be reduced notably by fractionating the payload compared to the equivalent Sentinel-2 mission.

Miniaturization is an inherent trend in ubiquitous computing. Insect-scale robots add new capabilities to disaster management, tiny headphones are emerging as complete computing devices, and small wearable health monitors can track vital signs around the clock. Advancements in sensing technologies play a pivotal role in this development. Spatial sensing at this form factor, however, is a skill yet to be mastered, particularly at low-frequency signals like audible sounds. Traditionally, spatial sensing requires sampling in both time and space using an array of microphones, which comes with a strict size requirement and multiplies its power requirement. In this article, we explore the possibility of an alternative design for spatial sensing for miniaturized and power-constrained devices.

Purpose This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes. Design/methodology/approach This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results. Findings Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature. Research limitations/implications The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials. Practical implications This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process. Social implications The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment. Originality/value The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

Green transit-oriented development (TOD) is an evolution of the TOD theory, influenced by sustainable development and green urbanism. This advancement expands the environmental and ecological dimensions of conventional TOD. However, relevant research has only just started, particularly in combination with high-density cities in Asia. This study measures the built environment of Green TOD and identifies the key factors and characteristics of the Green TOD built environment. An evaluation method for the Green TOD built environment is developed on the basis of the 5D (density, diversity, design, destination, and distance) built environment framework and combined with green urbanism theories. Data from 23 rail station areas in Singapore were collected and analyzed using factor and cluster analysis. Five factors, namely, neighborhood spatial form factor, facility completeness factor, open space factor, high-density mixed land-use factor, and walking amenity factor, are extracted. Twenty-three station areas are classified into five clusters. The characteristics and optimization strategies of each cluster are analyzed on the basis of the statistical and graphical analyses. This research displays the characteristics and typology of the Green TOD built environment in an empirical way and offers a foundation for further research in diverse urban contexts.

Nearly 50 years ago, Intel created the world’s first commercially produced microprocessor—the 4004 (ref. 1), a modest 4-bit CPU (central processing unit) with 2,300 transistors fabricated using 10 μm process technology in silicon and capable only of simple arithmetic calculations. Since this ground-breaking achievement, there has been continuous technological development with increasing sophistication to the stage where state-of-the-art silicon 64-bit microprocessors now have 30 billion transistors (for example, the AWS Graviton2 (ref. 2) microprocessor, fabricated using 7 nm process technology). The microprocessor is now so embedded within our culture that it has become a meta-invention—that is, it is a tool that allows other inventions to be realized, most recently enabling the big data analysis needed for a COVID-19 vaccine to be developed in record time. Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). Separate from the mainstream semiconductor industry, flexible electronics operate within a domain that seamlessly integrates with everyday objects through a combination of ultrathin form factor, conformability, extreme low cost and potential for mass-scale production. PlasticARM pioneers the embedding of billions of low-cost, ultrathin microprocessors into everyday objects. Flexible electronic platforms would enable the integration of functional electronic circuitry with many everyday objects; here, a low-cost and fully flexible 32-bit microprocessor is produced.

Soft robots often show a superior power-to-weight ratio using highly compliant, light-weight material, which leverages various bio-inspired body designs to generate desirable deformations for life-like motions. In this letter, given that most material used for soft robots is light-weight in general, we propose a volumetrically enhanced design strategy for soft robots, providing a novel design guideline to govern the form factor of soft robots. We present the design, modeling, and optimization of a volumetrically enhanced soft actuator (VESA) with linear and rotary motions, respectively, achieving superior force and torque output, linear and rotary displacement, and overall extension ratio per unit volume. We further explored VESA's proprioceptive sensing capability by validating the output force and torque through analytical modeling and experimental verification. Our results show that the volumetric metrics hold the potential to be used as a practical design guideline to optimize soft robots’ engineering performance

There is an increasing importance of memory technologies in our ever-digitalizing society, which is characterized by the generation and use of a tremendous amount of real-time data. Beyond traditional performance requirements, mechanical flexibility of memory systems becomes therefore critical to enabling emerging applications such as the Internet of things. Graphene, now an established nanomaterial platform, is a promising element for building such high-performance memories with an unconventional form factor because of its exceptional electrical conductivities, outstanding mechanical properties, and processing versatility desirable for hybrid integration. Here, we provide an overview of recently developed flexible memory devices based on graphene and its functionalized counterparts. A defining feature of this review is that it exclusively compares and analyzes the devices that meet the following two criteria: (i) an explicit demonstration of working devices on a flexible substrate is reported; (ii) graphene is employed as an active channel rather than as an electrode. Our primary focus is to systematically classify various types of memories, in view of their materials, structural, and functional characteristics. For this, the shapes and compositions of the conductive channel, the key operational mechanisms underlying the electrical functionalities, and the major characteristics of representative device structures and materials systems are carefully evaluated. Furthermore, the applicability of flexible graphene memories to the neuromorphic computing area is discussed. Finally, we address several remaining issues that need to be solved for future technological advancements.

On-skin displays are emerging as a wearable form factor for the display of information; however, the perception of using such devices in public could determine whether they are eventually adopted or rejected. This study investigated the means by which on-skin notification displays are perceived by the general public. We adopted a mixed-methods approach to the analysis of results from an online survey (n = 254) and in-lab interviews (n = 36) pertaining to the novel form factor, device materiality, and envisioned use cases. The study was conducted in the US and Taiwan in order to examine cross-cultural attitudes toward device usage. The results of this structured examination provide valuable insights into the design of on-skin notification displays for everyday use across cultures.

With the help of augmented reality (AR) and virtual reality (VR) systems, users can receive information and connect with each other via near-eye displays (NEDs). However, several challenges need to be addressed, and the optics are the major bottlenecks. Users wearing current NEDs typically suffer from vergence-accommodation conflict (VAC). Furthermore, people with refractive errors need a pair of prescription lenses to clearly see the virtual image and/or environment. Hence, VAC-free AR/VR systems with vision correction functions should be developed. Furthermore, the AR/VR systems must be designed with slim form factors. Liquid crystal (LC) optical elements with a thin form factor have been demonstrated for light modulation in versatile optical systems; thus, LC-based solutions have been proposed for AR/VR systems in the past decade. Herein, we provide a comprehensive review on the existing literature on LC-based optical systems and suggest possible solutions to realize a better NED system. This review provides an overview of the state-of-the-art progress of LC optics in AR and VR systems. It focuses on the fundamental optics of NEDs, origins of VAC and current LC-based solutions, LC lenses for vision correction function, and the guidelines for solving the two aforementioned challenges using LC lenses.

Due to their low size, mass, development cost and time, nanosatellites have become an increasingly popular tool at universities for providing students with hands-on experience in aerospace education. Among spacecraft subsystems, the attitude determination and control one surely represents a fruitful resource for practicing aerospace control applications. To enable on-ground verification of spacecraft attitude control hardware and software, however, the biggest challenge to overcome is that of providing a representative testing environment. Towards this end, at the µ3S laboratory at the University of Bologna a dynamic hardware in the loop facility has been developed, which allows for testing attitude control subsystems of nanosatellites in the range of 1U to 3U, according to the CubeSat form factor. This paper describes the educational impact that the facility has been having, during both its development and commissioning phases, as well as its early use as a testbed for CubeSats attitude control, which is currently focused on magnetic-based actuation.

Organic electrochemical transistors (OECTs) are highly versatile in terms of their form factor, fabrication approach that can be applied, and freedom in the choice of substrate material. Their ability to transduce ionic into electric signals and the use of bio-compatible organic materials makes them ideally suited for a wide range of applications, in particular in areas where electronic circuits are interfaced with biologic matter. OECT technology has attracted widespread interest in recent years, which has been accompanied by a steady increase in its performance. However, this progress was mainly driven by device optimization and less by targeting the design of new device geometries and OECT materials. To narrow this gap, this review provides an overview on the different device models that are used to explain the underlying physics governing the steady and transient behavior of OECTs. We show how the models can be used to identify synthetic targets to produce higher performing OECT materials and summarize recently reported materials classes. Overall, a road-map of future research in new device models and material design is presented summarizing the most pressing open questions in the understanding of OECTs.

According to statistics provided by Cisco, the Internet of Things market will grow rapidly and will reach 50 billion devices connected to the Internet by 2020. All these connected devices, in smart Home/Building should make life easier, sweeter and more enjoyable. Ideally, each device must work immediately and not require people to try to make them work. However, connected things come from different manufacturers using different protocols of communication. The diversity of protocols and sometimes their incompatibilities stay a major issue. Although, efforts have been made in recent years to improve the compatibility of the protocols, but these interactions remain limited. One solution to address this issue is to use an Internet of Things (IoT) platform to facilitate their interaction, control them intelligently using a web interface or a voice assistant. In this paper, we define connectivity requirements to improve interoperability between devices that make up the Internet of Things (IoT). An implementation of a Web application and virtual assistance that ensures interoperability regardless of form factor, operating system, service provider or transport technology, creating a" network of everything".

Smart electronic devices are becoming ubiquitous due to many appealing attributes including portability, long operational time, rechargeability and compatibility with the user-desired form factor. Integration of mobile power sources (MPS) based on photovoltaic technologies with smart electronics will continue to drive improved sustainability and independence. With high efficiency, low cost, flexibility and lightweight features, halide perovskite photovoltaics have become promising candidates for MPS. Realization of these photovoltaic MPS (PV-MPS) with unconventionally extraordinary attributes requires new ‘out-of-box’ designs. Natural materials have provided promising designing solutions to engineer properties under a broad range of boundary conditions, ranging from molecules, proteins, cells, tissues, apparatus to systems in animals, plants, and humans optimized through billions of years of evolution. Applying bio-inspired strategies in PV-MPS could be biomolecular modification on crystallization at the atomic/meso-scale, bio-structural duplication at the device/system level and bio-mimicking at the functional level to render efficient charge delivery, energy transport/utilization, as well as stronger resistance against environmental stimuli (e.g., self-healing and self-cleaning). In this review, we discuss the bio-inspired/-mimetic structures, experimental models, and working principles, with the goal of revealing physics and bio-microstructures relevant for PV-MPS. Here the emphasis is on identifying the strategies and material designs towards improvement of the performance of emerging halide perovskite PVs and strategizing their bridge to future MPS.

The article is devoted to the study of the stability authentication signs of personal computers; possibility of authentication follows from their physical differences as complex electronic devices. This approach provides the ability to remotely automatic authentication in real time. The authentication template was calculated from the sequence of values of the auto-correlation function of the internal electrical noise. It was demonstrated that the noise instability of noise leads to the error in the computer authentication. In order to reduce the error's probability, it was proposed to use the form-factor of autocorrelation function histogram for automatic sorting of noise files. The character of the noise instability had allowed the use of several authentication templates for one computer with instable noise. Each template was designed for the separate stability area. The probability of false authentication was reduced by using two authentication templates for one computer with instable noise, it was 30%. The recommendations were made about determining the priority of access to confidential information for computer with instable noise.

Recent work has shown the feasibility of producing knitted capacitive touch sensors through digital fabrication with little human intervention in the textile production process. Such sensors can be designed and manufactured at scale and require only two connection points, regardless of the touch sensor form factor and size of the fabric, opening many possibilities for new designs and applications in textile sensors. To bring this technology closer to real-world use, we go beyond previous work on coarse touch discrimination to enable fine, accurate touch localization on a knitted sensor, using a recognition model able to capture the temporal behavior of the sensor. Moreover, signal acquisition and processing are performed in real-time, using swept frequency Bode analysis to quantify distortion from induced capacitance. After training our network model, we conducted a study with new users, and achieved a subject-independent accuracy of 66% in identifying the touch location on the 36-button sensor, while chance accuracy is approximately 3%. Additionally, we conducted a study demonstrating the viability of taking this solution closer to real-world scenarios by testing the sensor's resistance to potential deformation from everyday conditions. We also introduce several other knitted designs and related application prototypes to explore potential uses of the technology.

IoT devices become more and more popular which implies a growing interest in easily maintainable and battery-independent power sources, as wires and batteries are unpractical in application scenarios where billions of devices get deployed. To keep the costs low and to achieve the smallest possible form factor, SoC implementations with integrated energy harvesting and power management units are a welcome innovation.On-chip energy harvesting solutions are typically only capable of supplying power in the order of microwatts. A significant design challenge exists for the functional blocks of the IoT-SoC as well as for the power management unit itself as the harvested voltage has to be converted to a higher and more usable voltage. Simultaneously, the power management blocks have to be as efficient as possible with the lowest possible quiescent currents.In this paper, we provide a look at on-chip microwatt power management. Starting with the energy-harvesting from RF power or light, we then show state-of-the-art implementations of ultra-low power voltage references and ultra-low power low-dropout regulator (LDO) designs.

Editor’s notes: Mobile and IoT devices have proliferated our daily lives. However, these miniaturized computing systems should be highly energy-efficient due to their ultrasmall form factor. Hence, energy management is of utmost importance for both mobile and IoT devices. This article presents a comprehensive survey on this topic. — Partha Pratim Pande, Washington State University

Cable-driven robotic manipulators are desirable for medical applications, for their form factor flexibility after separating actuation from the distal end. However, intended to work under high spatial constraints such as dental or other surgical applications, severe cable elongations will raise control challenges from inaccuracy to excessive compliance. It is critical to proactively regulate the system compliance, in order to achieve both compliant behavior to avoid tissue damage, and rigid behavior necessary for dental drilling. Both ends of this challenges have been extensively studied in literature, with rigidity achieved by cable elongation compensation, and virtual compliance regulation by impedance control. However, each approach worked within its own turf, with very little being studied in how to blend the two sources of compliance strategically. In this work, blending virtual compliance modulated by impedance control with transmission compliance induced by cable elasticity was investigated and demonstrated in a modified design of our proprietary dental manipulator. It was shown that direct application of impedance control in a cable-driven system would not bluntly increase compliance, and may cause instability. Instead, we proposed a compliance-blending framework with Cartesian-space super-positioning of cable motion compensation and impedance control, and validated the efficacy on the 6-DOF dental manipulator platform. Desirable results were achieved using highly common approaches in both impedance control and cable compensation, making the proposed approach applicable to a wide range of cable-driven robotic systems for impedance control.

High-density integration and packaging technologies are highly desired to integrate more functionality into a smaller form factor with improved performance, in which the polymer-based electronic packaging materials play a key role. In this short review, we will give a brief summarization of some key polymer-based electronic packaging materials, including flip-chip underfill, thermal interface material, dielectric material and EMI shielding material. The key factors influencing the performance of polymer-based electronic packaging materials, such as the surface modification of filler, orientation of polymer chains and microstructures of materials are discussed. In addition, prospective research opportunities toward the development of advanced polymer-based electronic packaging materials are highlighted and the challenges and outlook of polymer composites for electronic packaging are prospected.

At present, the politics of digital tools are predominantly discussed in terms of the data they collect, analyze, and circulate. Through my analysis of electronic ankle monitors’ visual characteris...

A flexible hybrid integration strategy combing both advantages of the silicon chip and the printed polymer sensors is demonstrated for low cost smart packaging with internet-of-things connectivity. In the system, the silicon chip, as the general part, performs wireless energy harvesting, sensor signal acquisition, data processing and transmission through mature standard interfaces. The functions, form factor, and substrate of the printed polymer sensors can be customized according to the packaging requirements. To prove the feasibility, a 13.56 MHz radio frequency identification (RFID) chip with multi-sensor interface is designed and taped out. Ammonia and anti-open sensors are fabricated using the same conducting polymer (PEDOT:PSS) through solution printing processes. After characterization of their performance individually, a flexible smart packaging system is implemented with packed pork by integrating the RFID chip and the sensors onto a packaging film. Both the product quality and the integrity of the packaging are able to be conveniently inspected with a smartphone.

Active fibers with electro-optic functionalities are promising building blocks for the emerging and rapidly growing field of fiber and textile electronics. Yet, there remains significant challenges that require improved understanding of the principles of active fiber assembly to enable the development of fiber-shaped devices characterized by having a small diameter, being lightweight, and having high mechanical strength. To this end, the current frameworks are insufficient, and new designs and fabrication approaches are essential to accommodate this unconventional form factor. Here, we present a first demonstration of a pathway that effectively integrates the foundational components meeting such requirements, with the use of a flexible and robust conductive core carbon nanotube fiber and an organic-inorganic emissive composite layer as the two critical elements. We introduce an active fiber design that can be realized through an all solution-processed approach. We have implemented this technique to demonstrate a three-layered light-emitting fiber with a coaxially coated design.

The flexible laser micromilling technology for ceramic MEMS production of microhotplates in the surface mount device (SMD) package is described. Current results demonstrate that using described technology makes it possible to manufacture all parts of MEMS sensor in the SMD with form factor of SOT-23 package type.

This article introduces the accessory dock, a 3D printed multi-purpose extension for consumer-grade XR controllers that enables flexible mounting of self-made and commercial accessories. The uniform design of our concept opens new opportunities for XR systems being used for more diverse purposes, e.g., researchers and practitioners could use and compare arbitrary XR controllers within their experiments while ensuring access to buttons and battery housing. As a first example, we present a stylus tip accessory to build an XR Stylus, which can be directly used with frameworks for handwriting, sketching, and UI interaction on physically aligned virtual surfaces. For new XR controllers, we provide instructions on how to adjust the accessory dock to the controller’s form factor. A video tutorial for the construction and the source files for 3D printing are publicly available for reuse, replication, and extension (https://go.uniwue.de/hci-otss-accessory-dock).

Bioelectronic interfaces have been extensively investigated in recent years and advances in technology derived from these tools, such as soft and ultrathin sensors, now offer the opportunity to interface with parts of the body that were largely unexplored due to the lack of suitable tools. The musculoskeletal system is an understudied area where these new technologies can result in advanced capabilities. Bones as a sensor and stimulation location offer tremendous advantages for chronic biointerfaces because devices can be permanently bonded and provide stable optical, electromagnetic, and mechanical impedance over the course of years. Here we introduce a new class of wireless battery-free devices, named osseosurface electronics, which feature soft mechanics, ultra-thin form factor and miniaturized multimodal biointerfaces comprised of sensors and optoelectronics directly adhered to the surface of the bone. Potential of this fully implanted device class is demonstrated via real-time recording of bone strain, millikelvin resolution thermography and delivery of optical stimulation in freely-moving small animal models. Battery-free device architecture, direct growth to the bone via surface engineered calcium phosphate ceramic particles, demonstration of operation in deep tissue in large animal models and readout with a smartphone highlight suitable characteristics for exploratory research and utility as a diagnostic and therapeutic platform., The development of high-performance implantable soft electronics as diagnostic platforms is key to realizing improved health monitoring. Here, the authors design wireless, battery-free, implantable bioelectronics that interface with the osseosurface for chronic musculoskeletal system monitoring.

Freeform optics and metasurfaces are two emerging optical technologies that show promise for addressing the needs of modern consumer devices like augmented and virtual reality (AR/VR) displays and mobile cameras. Recent advances in fabrication and testing have been critical to the success of freeform optics. In parallel, various methods for metasurface fabrication, including electron-beam lithography (EBL), have been researched and well established in the last decade but have been limited to fabrication on flat substrates. Metaform is a new optical component that consists of a metasurface conformed to a freeform substrate. We will explore the advances in nodal aberration theory, freeform design methodology, nanofabrication, and metrology necessary to make metaform optics a reality. To validate the developed processes and highlight the advantages of metaforms, we will examine a compact metaform imager inspired by the needs of AR displays. By leveraging the benefits of both metasurfaces and freeform optics, metaforms can thus be used to navigate critical design tradeoffs between optical performance, system volume, and form factor.

Medical ultrasound has become a crucial part ofmodern society and continues to play a vital role in the diagnosis and treatment of illnesses. Over the past decades, the development of medical ultrasound has seen extraordinary progress as a result of the tremendous research advances in microelectronics, transducer technology and signal processing algorithms. However, medical ultrasound still faces many challenges including power efficient driving of transducers, low-noise recording of ultrasoundechoes, effective beamforming in a non-linear, high-attenuation medium (human tissues) and reduced overall form factor. This paper provides a comprehensive review of the design of integrated circuits for medical ultrasound applications. The most important and ubiquitous modules in a medical ultrasound system are addressed, i) transducer driving circuit, ii) low-noise amplifier, iii) beamforming circuit and iv) analog-digital converter. Within each ultrasound module, some representative research highlights are described followed by a comparison of the state-of-the-art. Thispaper concludes with a discussion and recommendations for future research directions.

The heart of the a GNSS payload is an atomic clock which controls the accuracy of the transmitted signal. Conventional thinking is to use the best clock and you get the best accuracy from a GNSS satellite. The problem with this approach is you get negligible improvement for the majority of users and the approach doubles the price of the GNSS payload. This paper will show that by adopting a different clock architecture, a majority of GNSS users will experience two orders of performance improvement for autonomous driving, UAV operations and pedestrian navigation plus improve timing for networks and comm systems. The estimated form factor will larger than the current atomic clock factor but with the size of GNSS satellites, it will not be a problem. The cost will be less than the present fountain and full optical clocks. It is estimated to take 26 months to develop a TRL 6 demonstration unit.

Face detection and verification based on the camera have progressed to such an extent that they may be integrated into several applications. Traditional cameras are shrinking and driven, adopted by innumerable applications like from household to IOT’s in drones. Some of these applications inflicted by some limitations like form factor, weight and cost. But they require lens. Flat cams have no lens and these can be fabricated like microchips and thinner than dime. However, lens less detectors cannot at yet give their optics equivalents the same spatial resolution and clarity. With almost acceptable same resolution, speed and much lesser cost these flat cams are available. These are even flexible, foldable, wearable and even disposable and can find myriad applications in security. We suggest the use of certain approaches to detect and verify the lens less cameras nowadays for resolution, noise and artifacts. The images acquired from lens less cameras, which pave the door to their integration into new applications, can be conducted with great exactitude both facial detection and verification.

Some of the biggest challenges in applying Augmented Reality (AR) technologies to the industry floor are in the form factor, and safety requirements of the head worn display. This includes alleviating issues such as peripheral view occlusion, and adaptation to personal protective equipment. In this work we present the design of Project Ariel, an Open Source 3D printable display specifically designed for use in industrial environments. It is our hope that with this technology, the average tradesman can utilize the powerful visualizations AR has to offer, significantly improving their daily work flow.

For the past decade, optics and display hardware developments for mixed reality and smart glasses were merely a shot in the dark, providing enough display immersion and visual comfort for developers to build up apps, especially for the enterprise field. Today, as universal use cases for consumer emerge such as co-presence, digital twin and remote conferencing, new optical functionalities are required to enable such experiences. It is not only a race to smaller form factor and light weight devices for large field of view (FOV) and lower power, but the requirements are also on additional display and sensing features specifically tuned to implement such new universal use cases. Broad acceptance of wearable displays especially in the consumer field is contingent on enabling these new display and sensing requirements in small form factors and low power. This talk will focus on waveguide combiner technologies and how these architectures have evolved over the past years to address such new requirements

The rise in life expectancy of humans, COVID-19 pandemic and growing cost of medical services has brought up huge challenges for the government and healthcare industry. Due to unhealthy lifestyle, there is an increased need for continual health monitoring and diagnosis of diseases. Wireless Body Area Network (WBAN) is attracted attention of researchers as various biosensors can be embedded in or worn on the body of human beings for the measurement of health parameters. The patient's health data is then sent wirelessly to the physician for health analysis. The biosensors used to measure physiological parameters have limited power due to its small size and hence smaller form factor. For the longevity of the network, it is imperative to transmit the data in an energy-efficient manner. Moreover, the health information of the patient is stringently private. Hence, the privacy and security of transmitted information needs to be ensured. It necessitates the development of effective, lightweight and secure routing protocols that provides security with minimal use of resources. This paper has identified the numerous security requirements in WBANs and has provided the extensive review on existing secure routing protocols reported in the literature. A comparative analysis of the various existing state-of-the art secure routing protocols and critical analysis based on security techniques along with different performance parameters has been presented.

Hydrosat's VanZyl-1 demonstration payload is representative of an emerging class of small satellite payloads, with a goal to enable infrared measurements relevant to Earth science applications in a small size, weight, and power (SWaP) footprint. In order to optimize the performance of an infrared instrument within the confines of a hosted payload allocation or other SmallSat form factor, careful attention must be paid to the radiometric calibration sources that will be available on orbit. This paper explores the state of the art in compact blackbody sources and alternative on-board calibration sources, as well as established practices for vicarious calibration such as oceans or the lunar surface. These options will be summarized in terms of high-level calibration goals including relative detector calibration, absolute response calibration, and reference target radiometric knowledge over time.

Wrist-worn devices hold great potential as a platform for mobile health (mHealth) applications because they comprise a familiar, convenient form factor and can embed sensors in proximity to the human body. Despite this potential, however, they are severely limited in battery life, storage, band-width, computing power, and screen size. In this paper, we describe the experience of the research and development team designing, implementing and evaluating Amulet - an open-hardware, open-software wrist-worn computing device - and its experience using Amulet to deploy mHealth apps in the field. In the past five years the team conducted 11 studies in the lab and in the field, involving 204 participants and collecting over 77,780 hours of sensor data. We describe the technical issues the team encountered and the lessons they learned, and conclude with a set of recommendations. We anticipate the experience described herein will be useful for the development of other research-oriented computing platforms. It should also be useful for researchers interested in developing and deploying mHealth applications, whether with the Amulet system or with other wearable platforms.

We present recent progress in developing miniaturized optical transmitters and receiver amplifiers for space communications. Three C-band high-speed optical transmitter designs are presented: a bespoke 300 mW version as part of TNO’s “SmallCat” terminal to fly on-board NordSat and two variants that provide 300 mW and 3 W of optical power complying to standard cubesat form factors. In addition to these transmitters, an ultra-small form factor, high gain, low noise amplifier, for boosting received signals is presented.

In the data economy more memory, more speed, lower power, smaller form factor is needed for data-hungry workloads and real-time computations from data-center to edge. Advanced packaging is key to building such solutions for memory and memory-logic integration. In this talk, we will go over core enabling packaging technologies and challenges that need to be overcome to realize them.

A elegant extremely flexible Fan-Out Wafer-Level Packaging (FOWLP) based fully integrated bipolar multi-channel (up to 12 channels) surface electromyography (sEMG) device and assembly is demonstrated for intraoperative neurological monitoring (IONM) for complex spine surgeries and post-op physiological monitoring. It includes twenty gold-capped vertically corrugated flexible dry copper electrodes, Bluetooth wireless data transfer, a multichannel sEMG data acquisition and processing dielet, rechargeable energy storage and an ergonomic reusable adhesive for ease of use. This completely biocompatible and wearable system is highly flexible, thin (1 mm), light weight (< 5 g) and can be used to monitor neuro-muscular activations for IONM as well as for general physiological monitoring.

As the final step of IC fabrication, packaging is the process to encapsulate the chip and provide the interconnections for the I/O of the final form factor. The demand for increasingly higher I/O density, shrinking device size and lower cost that drive wafer processing also apply to the packaging process. Various technologies have been developed in order to achieve these goals with most of them being wafer-level packaging (WLP). Unlike traditional packaging process, most I/O interconnections are done at the wafer-level with redistribution layers (RDLs). RDLs are the layer where copper lines and vias form the electrical connections. Depending on the applications' market such as mobile, memory or the Internet of Things (IoT), fan-out wafer level packaging (FOWLP) provides the most promising method to support the I/O density requirements and fine RDL line/space. Moreover, fan-out panel level packaging (FOPLP) was also developed in order to capitalize on economies of scale and optimize substrate utilization. In this technology, a rectangular substrate is used in the process instead of a round-shape substrate like a wafer. Processes and equipment have long been developed for the wafer substrate market, but the previous developments cannot be directly applied to panel substrates. For instance, in the wafer line, spin on processes are very prevalent but these are not at all practical for a panel line. Some capital equipment manufacturers have been reluctant to embrace panel-level manufacturing due to the uncertainty as to whether it will prevail. Struggles with yield have been very common; some of which are due to die placement and others due to the lack of process control capabilities. With the explosion and adoption of FOWLP to enhance package shrinkage and performance the panel market becomes more and more viable. The companies that have embraced panel level manufacturing from the beginning have a distinct advantage due to their intimate knowledge and experience with the substrates as well as the relationship developed with capital equipment suppliers to develop the necessary technology in order to process the panels. However, there is still a great need to ensure the product mix deployed in panel form can have an acceptable yield; automated optical inspection and die placement metrology bridge that gap. Automated optical inspection allows for defect detection with traditional bright field (BF) or dark field (DF) illumination and also a new novel illumination technique that enables the detection of organic particles and/or residues that are often used in panel-level packaging processes. A system capable of macro defect detection with sub-micron capabilities allows for multi-purpose panel inspections. The system is also equipped with metrology capabilities for critical dimension and die placement measurements which meet the process node dimensional requirements. These features allow for process control of pick and place, overlay as well as feed-forward capabilities for die placement corrections. In a FOWLP/FOPLP process, chip first and chip last can be concluded among all available methods in the market. Die placement either start from the initial phase of the process or in the final phase of the process. In the chip first scenario, the chips are placed on a carrier by a pick-and-place system and then followed by an encapsulating molding process to reconstitute a substrate (reconstituted wafer or reconstituted panel). At this point a semi-additive process (SAP) is typically followed which includes a photo resist layer being coated, exposed and developed following copper (Cu) plating in order to form the redistribution layer. In this workflow, the die position are dominated by the accuracy of the pick-and-place tool and coefficient of thermal expansion (CTE) mismatch of the molding material and carrier. The trade-off between throughputs, placement accuracy and a feedback mechanism is the main impact from the pick-and-place tool in this process step. This affects both the chip first and chip last scenarios. The thermal expansion of the molding process not only adds additional die shift but also causes warpage of the reconstituted substrate that becomes an issue for automated handling systems and local process variation. Therefore, to know the actual die position and orientation after the die placement and molding process is crucial for matching with the following redistribution layers development. In one scenario it is possible to utilize the lithography system to perform die position metrology, however, this is time consuming and impacts the cost of ownership and overall throughput for the lithography process. A solution to this problem is provided by implementation of an optical metrology system. Since this information needs to be passed to the lithography tool in a usable manner for variable exposure positioning, the alignment of the stage coordinate system between the die metrology tool and lithography tool is a key point to ensure the correctness of the feed forward loop. For RDL development overlay between die and RDL via directly impact yield and are just as critical to the process as defect inspection and critical dimension measurements. Based on the corrections for each die, a yield prediction can be made and provides different strategies for the lithography tool's exposure field in order to balance throughput and exposure yield rate. In this paper, we demonstrate a solution using an automatic optical inspection (AOI) system to perform the die metrology for chip placement and RDL development in FOPLP and FOWLP. This includes die shift, die rotation, RDL inspection as well as the overlap between a reconstituted substrate and RDLs. This solution provides comprehensive coverage for packaging process control and significantly impacts yield optimization and throughput enhancement. With a multifunctional AOI system, it also reduces the cost of ownership for packaging processes.

For the first time, a fully 3-D electric circuit was modeled in a 3-D environment and manufactured via an automated hybrid direct-write 3-D printing process. The implications and applications of this significant achievement are enormous because it allows circuits to be designed and manufactured in virtually any form factor. To accomplish this, a custom computer-aided design (CAD) tool was programmed into an open-source modeling software to layout components and route interconnects. The custom CAD tool imports the netlist and component geometries from a schematic capture program. Components can be placed at any position and be oriented at any angle. Interconnects can meander smoothly throughout the circuit following 3-D splines. The interconnects can be placed manually or automatically between components. After laying out the components and routing interconnects, the tool exports Standard Tessellation Language files of the dielectric and metal portions of the final circuit to be 3-D printed. To manufacture the circuit, fused-deposition modeling of acrylonitrile butadiene styrene plastic and microdispensing ( $\mu \text{D}$ ) of DuPont CB028 silver paste was used. To demonstrate, a functional 555 timer circuit was designed and built to flash an LED.

The fan-out package is designed to provide increased I/O density within a reduced form factor at a lower cost, as well as good electrical performance and heterogeneous integration capabilities, which has gained significant attention in recent years. However, warpage control during manufacturing process is a key character for fan-out packages. This paper focuses on the warpage prediction and optimization of embedded silicon fan-out (eSiFO) wafer-level package. An extended theoretical calculation model is applied and demonstrated, and the effects of various parameters on warpage were analyzed for optimization. By comparison with the experimental results, the finite-element modeling (FEM) simulation results and classic bimaterial model, the proposed extended theoretical calculation model is proven to be simple, fast, and effective for eSiFO wafer-level package. The effects of process steps, structural parameters, and material parameters were studied based on the extended theoretical model, and some advice on reducing warpage was given in the end. This paper offers an insight work for the warpage study of other embedded and fan-out packages.

In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

A three-dimensional (3D) glass integrated passive device (IPD) is an evolutionally advanced configuration to dramatically reduce the electronics form factor and manufacturing cost of current IPDs by introducing ultra-thin glass with through-glass-vias (TGVs). A defect-free TGV formation technology in polymer-laminated glass substrates is required to realize a highly reliable 3D glass IPD. This paper discusses mechanisms of each defect formation in the use of several types of lasers to explore suitable technology for defect-free drilling in polymer-laminated glass.

Reductions in wireless-sensor-node form factor and cost have enabled new applications for remote sensing in a variety of areas, such as grid infrastructure, building automation, medicine, factory automation and control, and automobiles. The projected number of sensor nodes is so large that battery replacement for all of them is impractical. Therefore, for market success, power consumption must be low enough that power can be supplied through energy harvesting or a small battery capable of lasting the lifetime of the sensor node.

This paper reports on the status of a comprehensive ten-year research and development effort toward hybrid system-in-foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion in and on a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity and form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on- and off-chip implementation of sensor, actuator, microwave, and energy supply components are addressed.

INTRODUCTION High-density advanced packaging (HDAP) continues to be the promising “More” in the “More than Moore” approach for improved form factor, functionality, and integration of multiple dies built using different technology nodes. HDAP offerings from outsourced assembly and test (OSAT) companies and foundries are continuously increasing. However, the full commercial productization of such offerings will require the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuits (ICs), will come from the availability of proven and qualified electronic design automation (EDA) tools and flows that can be used by the design houses to build HDAPs with the confidence that they are compliant with the foundry/OSAT requirements and recommendations. The need for and general concept of assembly design kits (ADKs) that provide proven, qualified flows for HDAPs has been previously discussed in multiple white papers. In addition, there have been analyses of the need for assembly-level layout vs. schematic (LVS) verification for HDAPs. Best practices for an assembly-level LVS process have been proposed, including the required inputs (data, formats, etc.), and likely hurdles and potential errors have been highlighted. There has even been discussion of how parasitic extraction could be achieved for packages. However, as HDAP technologies and flows mature, system-level designers want to know if package design rule checking (DRC), assembly-level LVS, and layout vs. layout (LVL) verification (die-to-package alignment, scaling, orientation, etc.) are sufficient to guarantee correct functionality and successful manufacturing of the HDAP. While this question may depend on how complicated the HDAP is, in general, the answer (for now) is no. As HDAP technologies become more and more similar to IC technologies, it is clear that, although the physical verification steps for HDAP may be considered good progress, they are only part of a much more comprehensive flow, one that must account for a more in-depth, system-level electrical analysis. Of course, at the same time, expanded EDA tool support is required to ensure fast, accurate, automated flows that ensure package designers can meet their market schedules and expectations. HDAP POST-LAYOUT ELECTRICAL ANALYSIS In the case of an HDAP design, the foundry/OSAT expects that each component is designed and validated to meet the required HDAP constraints and specifications. For an analog-based flow, the designer must simulate the HDAP system circuitry, including parasitics, to ensure it meets the intended performance specifications. For a digital-based flow, the designer must run static timing analysis (STA) on the complete HDAP system, including parasitics, to ensure it meets the overall system timing budget. From an EDA perspective, building an automated flow to support these checks/analyses provides assurance that these processes can occur in a consistent, repeatable manner while ensuring accuracy and minimizing runtime. In general, EDA approaches take one of two paths. SINGLE COCKPIT In the cockpit approach, an EDA supplier builds a single simulator infrastructure to support HDAP circuit simulation, parasitic extraction (PEX), and static timing analysis (STA). Although a single interface seems convenient, it forces the designer to use the same design tool for all components at all levels (die and package). This approach may be too restrictive, given that HDAP design and verification typically require the involvement of multiple groups with varying backgrounds and tool preferences. Although this approach would be useful when building “fully live” heterogeneous HDAPs (i.e., both die and package are under development simultaneously, and can both be edited for performance), this is rarely the case. More commonly, known good dies (which have already been taped out) are used to build an HDAP. TOOL-AGNOSTIC In the tool-agnostic approach, an EDA supplier enables the user to construct the needed system-level connectivity of the HDAP (including parasitics), regardless of which design tools are used to build any one die or the package. Once the system-level connectivity is available, it can be exported in the required format to any circuit simulation/STA tool to simulate or analyze the entire HDAP system. This approach introduces minimum disruption to existing tools/methodologies used for die and package design. This paper discusses the implementation of a system-level parasitic netlist process for the HDAP using the tool-agnostic approach.