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The thermal modeling of electronic components is more and more crucial to prevent ageing phenomena when the component temperatures exceed their operating limits.At board level, the analysis of their mutual thermal interactions is done using multi-port RC networks as thermal models. Those compact models are usually extracted from a full physical representation of the component and its thermal behavior for a set of boundary conditions. Unfortunately, that fine description of the device requires a set of information about the package that is often not available.To complete the missing thermal properties, transient measurements of the junction-to-case behavior proved to be very useful. Using step function responses, a set of network identification by deconvolution of RC thermal model was conducted using iterative methods such as Bayesian ones.As a main result, a practical procedure is proposed that allows a direct extraction from discrete time constant spectrum of a very low-stage RC thermal model in the form of Foster ladder. The derived RC model demonstrates a high agreement with experimental data. The comparison is done on a set of devices mounted on a test vehicle.Further, the network identification procedure is conducted on the detailed numerical model of each device for calibration prospect. That calibration procedure of unidirectional responses permits to fix model discrepancies with the aim of creating relevant Boundary-Condition-Independent multipath RC networks.

Ceaseless efforts have been made by the electronic companies to increase the density of electronic boards. A new design concept consists of burying active and passive electronic components inside inner layers of a Printed Wiring Board (PWB). However this alternative leads to higher thermal stress due to heat concentration at the core of a temperature-sensitive substrate. In order to help the electronic designers to find the optimum placement of these heating devices, a guideline based on analytical approach model is proposed. This presented work focuses on the steady-state solution of the heat equation, resolved by separation of variables and the use of Fourier's series. The domain is an anisotropic, multi-layer parallelepiped, submitted to uniform heat transfer coefficients on its upper and lower surfaces and assumed adiabatic edges. These assumptions can be employed, with confidence, to valid the predictions of chip temperatures at laboratory conditions. To determine its ability to predict the maximum operating temperature of a set of buried chips, that practical solution is compared to its corresponding numerical model representing all the layers of realistic electronic board. Moreover the need to consider each PWB's layer is debated with the aim to faster the chip temperature evaluation. Thus a layer-selection method is investigated to find the best balance between accuracy and computation time. By using such optimised approach the computation time can be shortened by a factor of 600, compared to a detailed numerical analysis, while keeping a similar accuracy. Further, it could be a practical way to proceed to a smart simplification of the numerical model of PWB substrate for actual equipment.

Board-level simulation has to consider, at the earliest stage of the conception, the impact of the vicinity of numerous high- and medium-powered devices. In 1996, the European consortium DELPHI defined the concept of a surrogate, or compact thermal model (CTM), to minimize the computation times from days to minutes. A DELPHI-style CTM resumes an electronic component as a simple cuboid form and a network of resistors that links a single temperature-sensitive node to the major surfaces of heat extraction. That steady-state network is derived from a detailed numerical model, which is subjected to a set of boundary conditions (BCs) applied on its external surfaces. At first, this paper investigates the combinations of various sets of scenarios to generate and to test a multiport surrogate model. The objective is to define the lowest number of numerical simulations required while keeping the highest accuracy level of the derived BC-independent (BCI) thermal network. Then, this paper demonstrates the need of a smart selection of the isothermal surfaces to create a most relevant surrogate model. Finally, using that calibrated steady-state model, an extension of the DELPHI method to create multiport dynamic surrogate model is proposed as well as a set of BCs dedicated to transient network fitting.

Purpose Latest Computational Fluid Dynamics (CFDs) tools allow modeling more finely the conjugate thermo-fluidic behavior of a single electronic component mounted on a Printed Wiring Board (PWB). A realistic three-dimensional representation of a large set of electric copper traces of its composite structure is henceforth achievable. The purpose of this study is to confront the predictions of the fully detailed numerical model of an electronic board to a set of experiment results to assess their relevance. Design/methodology/approach The present study focuses on the case of a Ball Grid Array (BGA) package of 208 solder balls that connect the component electronic chip to the Printed Wiring Board. Its complete geometrical definition has to be coupled with a realistic board layers layout and a fine description of their numerous copper traces to appropriately predict the way the heat is spread throughout that multi-layer composite structure. The numerical model computations were conducted on four CFD software then compare to experiment results. The component thermal metrics for single-chip packages are based on the standard promoted by the Joint Electron Device Engineering Council (JEDEC), named JESD-51. The agreement of the numerical predictions and measurements has been done for free and forced convection. Findings The present work shows that the numerical model error is lower than 2 per cent for various convective boundary conditions. Moreover, the establishment of realistic numerical models of electronic components permits to properly apprehend multi-physics design issues, such as joule heating effect in copper traces. Moreover, the practical modeling assumptions, such as effective thermal conductivity calculation, used since decades, for characterizing the thermal performances of an electronic component were tested and appeared to be tricky. A new approach based on an effective thermal conductivity matrix is investigated to reduce computation time. The obtained numerical results highlight a good agreement with experimental data. Research limitations/implications The study highlights that the board three-dimensional modeling is mandatory to properly match the set of experiment results. The conventional approach based on a single homogenous layer using effective thermal conductivity calculation has to be banned. Practical implications The thermal design of complex electronic components is henceforth under increasing control. For instance, the impact of gold wire-bonds can now be investigated. The three-dimensional geometry of sophisticated packages, such as in BGA family, can be imported with all its internal details as well as those of its associated test board to build a realistic numerical model. The establishment of behavioral models such as DELPHI Compact Thermal Models can be performed on a consistent three-dimensional representation with the aim to minimize computation time. Originality/value The study highlights that multi-layer copper trace plane discretization could be used to strongly reduce computation time while conserving a high accuracy level.

Thermal behavior of electronic devices can be more and more finely predicted using the latest thermo-fluidic simulation tools. But when realistic three-dimensional geometric descriptions of the device and duty cycle phenomenon need to be analyzed, the parametric calculation times rapidly become unbearable. Numerous model reduction concepts were explored to determine the most efficient ways to report the sensitive temperature of a component, such as DELPHI method. This later promotes the replacement of time-consuming numerical simulations of large detailed model by a simpler multi-port thermal resistances network. The presented work discloses a method, coupling Model-Order-Reduction (MOR) technique and a metaheuristic optimization, allowing to reduce both creation and simulation times of a suitable model of a sophisticated Ball-Grid-Array (BGA) package. The developed reduction process enables generating a Modal Reduced-Order Model (M-ROM) then deriving a practical Dynamic Compact Thermal Models (DCTM), which will be highly reliable whatever the environment conditions. The performances of both deduced models are compared in terms of precision and calculation time with the original three-dimensional model over an extended set of operating conditions scenarios. The final model presents a good agreement, with a discrepancy lower than 2%, while greatly improving simulation speed and optimization run times.

The present work completes the toolbox of analytical solutions that deal with resolving steady-state temperatures of a multi-layered structure heated by one or many heat sources. The problematic of heating sources having non-rectangular shapes is addressed to enlarge the capability of analytical approaches. Moreover, various heating sources could be located on the external surfaces of the sandwiched layers as well as embedded at interface of its constitutive layers. To demonstrate its relevance, the updated analytical solution has been compared with numerical simulations on the case of a multi-layered electronic board submitted to a set of heating source configurations. The comparison shows a high agreement between analytical and numerical calculations to predict the centroid and average temperatures. The promoted analytical approach establishes a kit of practical expressions, easy to implement, which would be cumulated, using superposition principle, to help electronic designers to early detect component or board temperatures beyond manufacturer limit. The ability to eliminate bad concept candidates with a minimum of set-up, relevant assumptions and low computation time can be easily achieved.

A novel approach for the extraction of a Delphi-like Boundary-Condition-Independent (BCI) Dynamic Compact Thermal Model (DCTM) of a multi-chip package from its Detailed Thermal Model (DTM) was previously introduced. Such methodology is firstly based on the extraction of a MOR-based BCI model from the DTM, then on its simplification by means of a Genetic Algorithm into a Delphi-like BCI DCTM. In order to compare the accuracy of the DTM with that provided by both the MOR-based and the Delphi-like BCI DCTMs, a set of experimental measurements have been performed on test-board vehicles. In particular the JEDEC-standard thermal resistance “Junction-to-Case” of Semiconductor Devices with Heat Flow through a Single Path was examined. The agreement with experiment results of the initial DTM, its deduced MOR-based and its practical Delphi-like BCI DCTMs, is reported. The comparison highlights the ways to adjust DTM parameters as well as solder joint issues dictated by the brazing method.

The need for miniaturization leads IC packaging technologies toward more and more complex threedimensional geometries, which should be carefully addressed when dealing with thermal management. In order to model these devices in the necessary CFD simulations, Boundary Conditions Independent (BCI) Compact Thermal Models (CTM) were developed in the scope of the DELPHI consortium using Genetic Algorithm (GA) as the optimization technique. But at each level of packaging technology breakthrough, the ability to achieve the right balance between accuracy, reproducibility and speed of GA procedure shrank. The paper describes the first results when using a Particle Swarm Optimization (PSO) in place of genetic programming. So instead of reproduction, the swarm method updates the position and speed of each particle over time. This study presents different PSO variants found in the literature and implemented on 2 real test cases. They confirm that the PSO tends to fall easily in local optimums and even more as the component-model complexity grows. Trying to combine the benefits of both algorithms, a parallel GA-PSO hybridization is discussed in terms of methodology, accuracy, speed and robustness. Thus the promoted GA-PSO hybridization succeeds supplying the best solution 8 times more often, in half the computation time, for a multi-chip package. The study results confirm the feasibility to create blackbox models of various components having low-discrepancy in comparison with the authentic thermal behaviour.

Planar Magnetic Components, as called PMC, are now interesting alternatives to classic high frequency transformers. Based on the combination of a low profile magnetic core and Printed Circuit Board (PCB), these devices allow large reduction in terms of weight and size, which exacerbates power density constraints. In order to circumvent the potential thermal issues of a multi-layer embedding of flatten high-current-density copper windings at the heart of a PCB substrate, an investigation is conducted to define the proper way for building a simple thermal model that can take into account the electro-thermo-magnetic combined effects. At first, to better understand the mutual interactions of conjugated copper and iron losses as well as the heat conduction capability of the core structure, a set of numerical simulations were performed to calibrate a fine Detailed Thermal Model (DTM). Then the concept of Compact Thermal Model dedicated to planar transformer devices, inspired by DELPHI'S method, is defined for minimizing the computation time while keeping a high accuracy level to monitor the sensitive temperatures of primary and secondary windings as well as those of core structure. The presented results demonstrate the ability to deduce such a resistor network from time-consuming simulations. Designers can then perform trivial calculations to analyse the thermal impact of planar transformers.

Delphi-like Boundary Condition Independent (BCI) Compact Thermal Models (CTMs) are the standard for modelling single die packages. However their extraction, particularly in the transient case, will be time consuming due to complex numerical simulations for a large number of external conditions. Lately, new approaches to extract a BCI Dynamical CTM (DCTM), based on Model Order Reduction (MOR) have been developed. Despite the numerous advantages of this recent method, the lack of numerical tools to integrate reduced-order models (ROM) makes it difficult to use at board level. In this study, a novel process flow for extracting Delphi-inspired BCI DCTMs is investigated. Thus a detailed three-dimensional model is replaced by a BCI-ROM model using FANTASTIC matrix reduction code to generate the data used in the creation of a Delphi-style BCI DCTM. That hybrid reduction method has been applied to an industrial single-chip package, named QFN16. Its derived CTM and DCTM have been compared in term of accuracy and creation time for both approaches: in-house Delphi-inspired and MOR based. The results show that for a similar accuracy, the integration of MOR technique allows minimizing the time-consuming numerical simulations and so to reduce the thermal network creation time by 80%.

Burying active chips into internal layers of a Printed Wiring Board (PWB) allows increasing the density of an electronic board but leads to higher thermal stress inside its structure. To help the designers for analyzing the limits of the in-layer power dissipation, various analytical approaches were investigated. So the present work focuses on the thermal model based on a three anisotropic layers. The active chips are assumed as planar or volumetric heat sources. These assumptions are compared to a state-of-art numerical model which details all PWB layers. As expected the accuracy is depending of the geometrical representation of the source. Thus, the planar-source model is within ±16% of relative error with the numerical results when volumetric-source model is ±8%. Nevertheless, both source-models demonstrate their high capability to quickly predict the thermal behavior of embedded chips placements. Moreover, the three-dimensional representation of the chip is discussed in terms of computation effort.

Board-level simulation has to consider, at the earliest stage of the conception, the impact of the vicinity of numerous high and medium powered devices. In 1996, the concept of Compact Thermal Model was defined, by the European consortium DELPHI to minimize the computation times, from days to minutes. A CTM resumes an electronic component as a simple cuboid form and a network of resistors that links a single temperature-sensitive node to major surfaces of heat extraction. Unfortunately the DELPHI method is restricted to steady-state model for mono-chip component. More complex issues such as multi-chip module or transient thermal model remain today for worldwide companies a non-trivial challenge. Our latest improvements made to generate steady-state multi-source CTM for System-In-Package devices showed that the number of boundary-condition scenarios is quite prohibitive when several nodes need to be monitored. The present work investigates the use of fractional factorial experiment, such as N-variables Doehlert design. The objective of this study is to define the lowest number of numerical simulations while keeping the highest accuracy level of the derived Boundary-Condition-Independent thermal network.

Latest Computational Fluid Dynamic tools allow modelling more finely the conjugate thermo-fluidic behaviour of a single electronic component mounted on a Printed Wiring Board. A realistic three-dimensional representation of a large set of electric copper traces of its composite structure is henceforth achievable. So it is possible to confront the predictions of the fully detailed numerical model of an electronic board to a set of experiment results in order to assess their relevance. The present work shows that the numerical model error is lower than 2% for various boundary conditions. Moreover the practical modelling assumptions, such as effective thermal conductivity calculation, used since decades, for characterizing the thermal performances of an electronic component were checked and appeared to be very tricky. New approaches must be developed. Further the establishment of a realistic numerical model of electronic components permits to properly apprehend multi-physics design issues.

The capability to efficiently transfer the heat away from high powered electronic devices is a ceaseless challenge. More than ever, the aluminium or copper heat spreaders seem less suitable for maintaining the component sensitive temperature below manufacturer operating limits. Emerging materials, such as Annealed Pyrolytic Graphite (APG), propose a new alternative to conventional solid conduction without the gravity dependence of a heat-pipe solution. Unfortunately, the ultrahigh performance rising of APG core is restricted to in-plane thermal conductivities which can be 200 times higher than its through-the-thickness conductivity. So a lower-than-anticipated cross-plane thermal conductivity or a higher-than-anticipated interlayer thermal resistance would compromise APG-based material as efficient heat spreaders. In order to analyse the sensitivity of these parameters on the effective thermal performances, an analytical model for predicting the temperature distribution over an APG flat-plate was developed. To demonstrate its relevance, it was compared to numerical simulations for a set of boundary conditions. The comparison shows a high agreement between both calculations to predict the centroid and average temperatures of heating sources. The pertinence of the practical expression used for modelling APG flat-plates thermal behaviour appears quite relevant for early stage design, our concern.

The latest low-profile high-power inductors, used in DC-DC converter to power an assortment of applications, are going endlessly smaller and submitted to larger amount of current. This surface-mounted magnetic component is commonly constructed using a wound copper coil which is over-moulded in a Soft Magnetic Composite (SMC) based on an iron-resin material mixture. The performances of that high-power density device are closely depending on the coupled interaction of magnetic phenomenon, joule effect and thermal behaviour, which are difficult to apprehend at board level simulation. In order to better characterize the behaviour of high-power inductor devices, a set of coupled electromagnetic and thermal simulations were performed on the case of an industrial demonstration electronic board. Further, the influence of surrounding active electronic components upon the acceptable temperature rise of the inductor parts has been investigated. The numerical simulations were completed by electrical characterizations and thermal measurements of the test vehicle for various operating conditions with the purpose to establish a more realistic thermal model of the inductor device. The agreement of the fine detailed model with experiment results is quite relevant: the divergence is lower than 10%. Moreover, the present study highlights the electromagnetic phenomena encountered by SMC inductor devices and their influence on the temperatures of the iron-based core and copper-based coil. This analysis confirms the conservative assumption that the magnetic and electrical losses can be uniformly applied to the core and coil volumes. The approach proposed in 2013, for the generation of a relevant Compact Thermal Model dedicated to SMC inductor devices, according with DELPHI methodology, remains valid.

Electronic components are continuously getting smaller. They embed more and more powered functions which exacerbate the temperature rise in component/board interconnect areas. Their design optimization is henceforth mandatory to control the temperature excess and to preserve component reliability. To allow the electronic designer to early analyze the limits of their power dissipation, an analytical model of a multi-layered electronic board was established with the purpose to assess the validity of conventional board modeling approaches. For decades, a vast majority of authors have been promoting a homogenous single layer model that lumped the layers of the board using effective orthotropic thermal properties. The work presents the thermal behavior comparison between a detailed multi-layer representation and its deducted equivalent lumped model for an extensive set of variable parameters, such as effective thermal conductivities calculation models or source size. The results highlight the fact that the conventional practices for Printed Circuit Board modeling can dramatically underestimate source temperatures when their size is very small.

Nowadays, thermal designers have to deal with sophisticated 3D component packaging, enclosing several chips or conventional individually-packaged Integrated circuits with various power densities, embedded in small volumes that will drive up the complexity of their thermal management. Previous analyses were made on system-in-package (SIP) modules to better know the thermal behavior of its encapsulated chips as well as the ability to create a Compact Thermal Model with numerous power sources. These works demonstrated that the creation of thermal resistance networks with n sources, compliant with a large set of realistic boundary conditions, can be achieved with success using superposition principle and Genetic Algorithm (GA) fitting technique. To pursue the development of effective thermal models for DC-DC converter devices, a set of experiments was performed to assess the pertinence of numerical simulations. Thus the upper surface of the asymmetric side-by-sidechips package was subdivided to characterize a set of local maximal and average temperatures. The temperature predictions of the numerical models were compared with the experimental infrared results. The present work describes the process flow that has to be led to generate a detailed numerical model having a low divergence with experimental results. It also declines the creation of DELPHI style models of the discrete sensitive parts of the package, such as inductor device. Each deducted network predicts the monitored key temperatures of the detailed thermal model with a discrepancy lower than 10%. Further a reduction methodology which nests these SubCompact Thermal Models promotes an alternative solution to realize more quickly the generation of a multiple sources thermal resistance networks, according to the boundary condition independent concept [3]. Therefore, the paper summarizes the comparison of a "state-of-the-art" numerical detailed model and its deducted compact model with the help of infrared experimental results in order to establish a modeling guideline.

The trend at the level of electronic component is to gather several active chips inside the same enclosing package. The thriving development of this technology allows reducing the volume in space as well as shortening the interconnection between the elements of the device. In this article, we analyze two methods of reduction of a detailed representation of a component, embedding three chips. The first approach is based upon the sub-compact vision, which consists in generating thermal compact models of different pseudo parts and plugged them within the over-molding resin of the package. This one gives good results but the size of the deducted model remains large. The second way uses a global reduction process by generating a whole network at once by means of genetic algorithm and superposition principle. The predictions of the behavioral models are relevant, poorly dependant of boundary conditions but the number of mandatory fitting scenarios becomes quite significant as well as the parameters to be optimized.

Recent works on System-In-Package component pointed out that its in-package inductor is the hottest part. It occurs that thermal stresses due to joule heating and magnetic losses can be damaging. The present study focuses on low profile, surface-mounted, Soft Magnetic Composite inductors to define their thermal behaviour and then to propose a guideline to create pertinent models.Results highlight the impact of thermal conductivity of composite core on temperatures and the lack of properties data of iron-resin mixtures. Using mixture model, a calculation of effective thermal conductivity is proposed.To minimize the expensive meshing of the fine detailed simulations and the computation time, a novel Compact Thermal Model for inductor, based on DELPHI methodology, was established. The predictions of CTM model show good agreement, less than 10% of divergence. Further works must be done to really master the coupled interaction of magnetic, joule effect, thermal phenomenon as well as material properties.

Printed Wiring Board die embedding technology is an innovative packaging alternative to address a very high degree of integration by stacking multiple core layers housing active chips. Nevertheless this increases the thermal management challenges by concentrating heat dissipation at the heart of the substrate and exacerbates the need of adequate cooling. In order to allow the electronic designers to early analyse the limits of the in-layer power dissipation, depending on the chip location inside the board, various analytical thermal modelling approaches were investigated. Therefore the buried active chips can be represented using surface or volumetric heating sources according with the expected accuracy. Moreover the current work describes the comparison of the volumetric heating source analytical model with the state-of-art numerical detailed models of several embedded chips configurations, and debates about the need or not to simulate in full details the embedded chips as well as the surrounding layers and micro-via structures of the substrate. The results highlight that the thermal behaviour predictions of the analytical model are found to be within ±5% of relative error and so demonstrate their relevance to model an embedded chip and its neighbouring heating chips or components. Further this predictive model proves to be in good agreement with an experimental characterization performed on a thermal test vehicle. To summarize, the developed analytical approach promotes several practical solutions to achieve a more efficient design and to early identify the potential issues of board cooling.

Nowadays a high-level integration with unprecedented functionality and efficient performances is achieved through 3D packaging techniques known as System-In-Package (SIP). The paper describes the reduction process conducted on a realistic SIP module case in order to establish a behavioral thermal network having a large number of power sources. Besides this device has been slightly modified to focus on the recent 3D integration techniques such as the stacking of chip, multi-chips side by side architecture or the embedding of conventional individually-packaged Integrated Circuits (IC). These works compared the prediction of a DELPHI style Compact Thermal Model (CTM)[1][6] to a numerical Detailed Thermal Model with for aim to illustrate the diminution of computation delays, the expected accuracy and some efficient ways to improve it. Then it describes the performance of a novel methodology that nests a set of Sub-Compact Thermal Models (SCTM) within the detailed numerical model, far less grid-intensive, and its ability to preserve the final SIP CTM quality.

The recent PWB embedding technology is an attractive packaging alternative that allows a very high degree of miniaturization by stacking multiple core layers of embedded chips, using copper filled micro-vias as interconnections to improve electrical performances.

The present work proposes an approach to generate Dynamic Compact Thermal Models or “DCTMs” dedicated to electronic components. This one is based on the European project DELPHI, which defined the first comprehensive methodology concerning the generation of thermal behavioral model, Boundary Condition Independent, called Compact Thermal Models or “CTMs”. Unfortunately, the scope of “CTMs” was limited to the steady state as well as for single chip packages [1][2][3][4].

Emerging packages offer diverse options for mounting active and passive devices in a single package, such as side by side, embedded or stacked die placements.

The thermal dissipation challenges that are seen today with single-chip components will only be magnified with the introduction of System in Package devices.

This paper establish a solution for detecting these components, establishing their model, that of the board which receives them. The checking analysis was conducted on a test board to create an adjusted thermal model by using a set of infrared measurements and an electrical measurement. Its response was then verified for conventional conditions of cooling. It is this validation presented as a comparison between simulation and experimentation that forms the subject of this document.

Component power density is increasing rapidly today and requires more sophisticated cooling equipment, which must be rationalised in order to prevent degraded component performances or poor reliability. One challenge of component package/board design is to identify strong thermal constraints and propose pre-optimisation early in the upstream phase. To increase the productivity and the reliability of the design task, companies need to develop a common methodology and approach for their design teams. This one requires a redefinition of the roles and involves a close partnership between the various actors of board design, such as Librarian, Electronics Engineer, Electronics Designer and Thermal Expert. The expected benefits of "using an a shared thermal "brick" model methodology is that designer and expert activities are linked from preliminary design to final thermal simulation. This allows us, considering a predictive accuracy of 15%, to eliminate bad component candidates and to identify the weakest ones at an early stage, while accelerating the design cycle by quick EDA iterations and so reducing design cost.

International audience; The computation time needed to compute modes remains the main drawback of modal methods. This computation time can be reduced by using the sub structuring modal method. First of all, the model is divided into elementary entities, and modes of each entity are independently computed. In order to solve the original problem, only specific modes are chosen to couple sub-structures together: the Steklov modes. This method is applied to an electronic card witch supports eighteen components. The Printed Circuit Board is accurately modeled considering local thermal properties (like local copper tracks). The reduced model recovers the maximum temperature of critical component for a dynamic scenario and various boundary conditions reducing the solver time by 500.