33 results on '"Eren Kursun"'
Search Results
2. Editorial
- Author
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Wei Zhang, Poki Chen, Naehyuck Chang, Eren Kursun, Makoto Nagata, M. Elfadel, Huawei Li, Partha Pratim Pande, Tae-Hyoung Kim, Ioannis Savidis, Houman Homayoun, Krishnendu Chakrabarty, Yuh-Shyan Hwang, Chirn Chye Boon, Patrick Mercier, Shih-Chieh Chang, Arun Natarajan, Chip-Hong Ho, Maxime Baas, Sheldon X.-D. Tan, Said Hamdioui, Mingoo Seok, Mehran Mozaffari Kermani, Aida Todri-Sanial, Koji Nii, Jaydeep P. Kulkarni, Masanori Hashimoto, Tsung-Yi Ho, Pasquale Corsonello, Massimo Alioto, Masud H. Chowdhury, Chulwoo Kim, Meng-Fan Chang, Hai Helen Li, Tanay Tan, Yao-Wen Chang, M. Tehranipoor, Prabhat Mishra, Stacey Weber Jackson, Zhengya Zhang, Rajiv L Joshi, Erik G. Larsson, Jiang Xu, and Miroslav N. Velev
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Very-large-scale integration ,Vlsi system design ,business.industry ,Computer science ,media_common.quotation_subject ,02 engineering and technology ,GeneralLiterature_MISCELLANEOUS ,020202 computer hardware & architecture ,Term (time) ,Audience measurement ,Pleasure ,Hardware and Architecture ,Vlsi systems ,0202 electrical engineering, electronic engineering, information engineering ,State (computer science) ,Electrical and Electronic Engineering ,Telecommunications ,business ,Very Happy ,Software ,media_common - Abstract
As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.
- Published
- 2017
3. Compact and voltage-scalable sensor for accurate thermal sensing in dynamic thermal management
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Eren Kursun, Pavan Kumar Chundi, Martha A. Kim, Seongjong Kim, Teng Yang, Mingoo Seok, and Peter R. Kinget
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Engineering ,business.industry ,020208 electrical & electronic engineering ,Overhead (engineering) ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Bandwidth throttling ,Dynamic voltage scaling ,Reliability (semiconductor) ,020204 information systems ,Scalability ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Calibration ,business ,Electronic circuit ,Voltage - Abstract
Today's microprocessors and Systems-on-Chip are thermally limited. Many, therefore, employ dynamic thermal management (DTM) to maximize performance under a reliability constraint. Accurate thermal monitoring is critical as temperature underestimation can hurt reliability by excessively aging devices and overestimation can hurt performance by unnecessarily throttling computing components. Placing temperature sensors close to potential hotspots can help accuracy, but it is non-trivial as hotspots often form inside digital blocks consisting of densely placed digital cells. Large sensors can disrupt cell placement thereby increasing wire lengths and circuit delays. Furthermore, the sensor needs to operate from the same digital power grid as the circuit, one that can be scaled down to near-threshold regime via dynamic voltage scaling. Absent this ability, a separate power grid and dedicated supply voltage for the sensors further increases area overhead. In this paper, we present a sensor circuit that is compact and deeply voltage-scalable and can be embedded among digital cells with little disruption. Simulation results show that it achieves a comparable accuracy to other compact sensor circuits for DTM.
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- 2017
4. Hotspot monitoring and Temperature Estimation with miniature on-chip temperature sensors
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Pavan Kumar Chundi, Martha A. Kim, Yini Zhou, Eren Kursun, and Mingoo Seok
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Engineering ,business.industry ,020208 electrical & electronic engineering ,Real-time computing ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Thermal management of electronic devices and systems ,Limiting ,Temperature measurement ,020202 computer hardware & architecture ,Microarchitecture ,Hotspot (geology) ,Scalability ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,System level ,Electronic engineering ,business ,Voltage - Abstract
This paper presents analysis and evaluation of the impact of size and voltage scalability of on-chip temperature sensor on the accuracy of hotspot monitoring and temperature estimation in dynamic thermal management of high performance microprocessors. The analysis is based on both the layout level and the system level across state-of-the-art sensors in terms of accuracy, voltage-scalability, and silicon footprint. Our analysis shows that a sensor having compact footprint and good voltage scalability can be placed on exact hotspot locations, typically among digital cells, significantly improving accuracy in tracking hotspots and estimating temperature of microarchitecture blocks, as compared to two other sensors that have higher sensor-circuit accuracy, large footprint and little voltage scalability limiting flexible placement.
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- 2017
5. Security Threats and Countermeasures in Three-Dimensional Integrated Circuits
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Jaya Dofe, Qiaoyan Yu, Peng Gu, Yuan Xie, Eren Kursun, and Dylan Stow
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medicine.medical_specialty ,Engineering ,Hardware security module ,business.industry ,Supply chain ,020208 electrical & electronic engineering ,SIGNAL (programming language) ,Computer security compromised by hardware failure ,02 engineering and technology ,Integrated circuit ,Computer security ,computer.software_genre ,020202 computer hardware & architecture ,law.invention ,Attack model ,law ,Hardware Trojan ,Embedded system ,0202 electrical engineering, electronic engineering, information engineering ,medicine ,Side channel attack ,business ,computer - Abstract
Existing works on Three-dimensional (3D) hardware security focus on leveraging the unique 3D characteristics to address the supply chain attacks that exist in 2D design. However, 3D ICs introduce specific and unexplored challenges as well as new opportunities for managing hardware security. In this paper, we analyze new security threats unique to 3D ICs. The corresponding attack models are summarized for future research. Furthermore, existing representative countermeasures, including split manufacturing, camouflaging, transistor locking, techniques against thermal signal based side-channel attacks, and network-on-chip based shielding plane (NoCSIP) for different hardware threats are reviewed and categorized. Moreover, preliminary countermeasures are proposed to thwart TSV-based hardware Trojan insertion attacks.
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- 2017
6. Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory
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Guangyu Sun, Yuan Xie, Jude A. Rivers, and Eren Kursun
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Engineering ,Hardware_MEMORYSTRUCTURES ,business.industry ,CPU cache ,Processor design ,Pipeline (computing) ,Register file ,Modular design ,Non-volatile memory ,Soft error ,Hardware and Architecture ,Embedded system ,Electrical and Electronic Engineering ,business ,Software ,Computer hardware ,Vulnerability (computing) - Abstract
Improving the vulnerability to soft errors is one of the important design goals for future architecture design of Chip-MultiProcessors (CMPs). In this study, we explore the soft error characteristics of CMPs with 3D stacked NonVolatile Memory (NVM), in particular, the Spin-Transfer Torque Random Access Memory (STT-RAM), whose cells are immune to radiation-induced soft errors and do not have endurance problems. We use 3D stacking as an enabler for modular integration of STT-RAM memories with minimum disruption in the baseline processor design flow, while providing further interconnection and capacity advantages. We take an in-depth look at alternative replacement schemes to explore the soft error resilience benefits and design trade-offs of 3D stacked STT-RAM and capture the multivariable optimization challenges microprocessor architectures face. We propose a vulnerability metric, with respect to the instruction and data in the core pipeline and through the cache hierarchy, to present a comprehensive system evaluation with respect to reliability, performance, and power consumption for our CMP architectures. Our experimental results show that, for the average workload, replacing memories with an STT-RAM alternative significantly mitigates soft errors on-chip, improves the performance by 14.15%, and reduces power consumption by 13.44%.
- Published
- 2013
7. Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits
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Yuan Xie, Yibo Chen, Charles Luther Johnson, Dave Motschman, and Eren Kursun
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Materials science ,Through-silicon via ,business.industry ,Bandwidth (signal processing) ,Design flow ,Electrical engineering ,Insulator (electricity) ,Integrated circuit design ,Integrated circuit ,Computer Graphics and Computer-Aided Design ,law.invention ,Thermal conductivity ,law ,Vertical direction ,Electronic engineering ,Electrical and Electronic Engineering ,business ,Software - Abstract
3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers) because the TSV size and pitch continue to scale in μm range and the metal to insulator ratio becomes smaller. Consequently, dense TSV farms can create lateral thermal blockages in thinned silicon substrate and exacerbate the local hotspots. In this paper, we propose a thermal-aware via farm placement technique for 3-D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. By incorporating thermal conductivity profile of via farm blocks in the design flow and enabling placement/aspect ratio optimization, the corresponding hotspots can be minimized within the wire-length and area constraints.
- Published
- 2013
8. Thermal-aware 3D design for side-channel information leakage
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Russell Barnes, Peng Gu, Dylan Stow, Yuan Xie, and Eren Kursun
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010302 applied physics ,Engineering ,business.industry ,Distributed computing ,02 engineering and technology ,Integrated circuit ,Computer security ,computer.software_genre ,Encryption ,01 natural sciences ,020202 computer hardware & architecture ,law.invention ,Information sensitivity ,Thermal aware ,law ,Factor (programming language) ,0103 physical sciences ,Information leakage ,0202 electrical engineering, electronic engineering, information engineering ,Side channel attack ,business ,computer ,3d design ,computer.programming_language - Abstract
Side-channel attacks are important security challenges as they reveal sensitive information about on-chip activities. Among such attacks, the thermal side-channel has been shown to disclose the activities of key functional blocks and even encryption keys. This paper proposes a novel approach to proactively conceal critical activities in the functional layers while minimizing the power dissipation by (i) leveraging inherent characteristics of 3D integration to protect from side-channel attacks and (ii) dynamically generating custom activity patterns to match the activity to be concealed in the functional layers. Experimental analysis shows that 3D technology combined with the proposed run-time algorithm effectively reduces the Side-channel Vulnerability Factor (SVF) below 0.05 and the Spatial Thermal Side-channel Factor (STSF) below 0.59.
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- 2016
9. Leveraging 3D Technologies for Hardware Security
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Russell Barnes, Yuan Xie, Eren Kursun, Peng Gu, Dylan Stow, Shuangchen Li, and Liu Liu
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010302 applied physics ,Hardware security module ,Engineering ,business.industry ,Three-dimensional integrated circuit ,02 engineering and technology ,Ip piracy ,01 natural sciences ,020202 computer hardware & architecture ,Ic manufacturing ,Embedded system ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Interposer ,Side channel attack ,Architecture ,business - Abstract
3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans, secure IC manufacturing and IP piracy. By utilizing intrinsic characteristics of 2.5D and 3D technologies, we propose novel opportunities in designing secure systems. We present: (i) a 3D architecture for shielding side-channel information; (ii) split fabrication using active interposers; (iii) circuit camouflage on monolithic 3D IC, and (iv) 3D IC-based security processing-in-memory (PIM). Advantages and challenges of these designs are discussed, showing that the new designs can improve existing counter-measures against security threats and further provide new security features.
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- 2016
10. Spatial and temporal thermal characterization of stacked multicore architectures
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Jamil A. Wakil, Mukta G. Farooq, Robert Hannon, and Eren Kursun
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Multi-core processor ,Engineering ,business.industry ,Design flow ,Stacking ,Response time ,law.invention ,Microprocessor ,Thermal conductivity ,Stack (abstract data type) ,Hardware and Architecture ,law ,Electronic engineering ,Electrical and Electronic Engineering ,Performance improvement ,business ,Software - Abstract
Three-dimensional integration provides a new way of performance growth for microprocessor architectures. While a recent studies report promising performance improvement numbers, majority of the processor stacking options are thermally-limited. Elevated stack temperatures have significant effect on the overall energy efficiency and reliability of the processor; they also limit the potential peak performance improvement from the 3D implementation. Thermal characteristics of 3D stacks differ from 2D processors in various ways including: the nature of heat dissipation throughout the stack, thermal conductivity of the 3D structures such as micro-C4 layers, and hotspot interactions among layers. The intensity of the corresponding thermal problems is highly dependent on the 3D technology, processor and stack parameters. In this study we focus on spatial and temporal thermal characteristics of 3D multicore architectures using high-fidelity technology and processor models. Our experimental results highlight the need for integrating detailed thermal models in the design flow, starting with the early design stages. In addition, the reduced time constants and elevated on-chip temperatures indicate faster response time requirements for dynamic thermal management in processor stacking options.
- Published
- 2012
11. Fast poisson solvers for thermal analysis
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Haifeng Qian, Sachin S. Sapatnekar, and Eren Kursun
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Speedup ,Computer science ,Finite difference ,Solver ,Poisson distribution ,Computer Graphics and Computer-Aided Design ,Computer Science Applications ,symbols.namesake ,Matrix (mathematics) ,Dimension (vector space) ,Conjugate gradient method ,symbols ,Electrical and Electronic Engineering ,Algorithm ,Eigendecomposition of a matrix - Abstract
Accurate and efficient thermal analysis for a VLSI chip is crucial, both for sign-off reliability verification and for design-time circuit optimization. To determine an accurate temperature profile, it is important to simulate a die together with its thermal mounts: this requires solving Poisson's equation on a nonrectangular 3D domain. This article presents a class of eigendecomposition-based Fast Poisson Solvers (FPS) for chip-level thermal analysis. We start with a solver that solves a rectangular 3D domain with mixed boundary conditions in O( N ⋅ log N ) time, where N is the dimension of the finite difference matrix. Then we reveal, for the first time in the literature, a strong relation between fast Poisson solvers and Green-function-based methods. Finally, we propose an FPS method that leverages the preconditioned conjugate gradient method to solve nonrectangular 3D domains efficiently. We demonstrate this approach on thermal analysis of an industrial microprocessor, showing accurate results verified by a commercial tool, and that it solves a system of dimension 4.54e6 in only 13 conjugate gradient iterations, with a runtime of 65 seconds, a 15X speedup over the popular ICCG solver.
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- 2012
12. Exploring the effects of on-chip thermal variation on high-performance multicore architectures
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Chen-Yong Cher and Eren Kursun
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Multi-core processor ,Thermal efficiency ,business.industry ,Computer science ,Hardware_PERFORMANCEANDRELIABILITY ,Chip ,Power (physics) ,Reduction (complexity) ,Process variation ,Hardware and Architecture ,Embedded system ,Dynamic demand ,Hardware_INTEGRATEDCIRCUITS ,business ,Software ,Information Systems ,Efficient energy use - Abstract
Inherent temperature variation among cores in a multicore architecture can be caused by a number of factors including process variation, cooling and packaging imperfections, and even placement of the chip in the module. Current dynamic thermal management techniques assume identical heating profiles for homogeneous multicore architectures. Our experimental results indicate that inherent thermal variation is very common in existing multicores. While most multicore chips accommodate multiple thermal sensors, the dynamic power/thermal management schemes are oblivious of the inherent heating tendencies. Hence, in the case of variation, the chip faces repetitive hotspots running on such cores. In this article, we propose a technique that leverages the on-chip sensor infrastructure as well as the capabilities of power/thermal management to effectively reduce the heating and minimize local hotspots. This technique can be used in existing multicore chips as long as the thermal sensor data can be made transparent to the power/thermal management at the software layer. According to our experimental analysis on test-chips, 5°C peak temperature reduction can be achieved with no performance degradation, hence the inherent energy efficiency of the chip can be improved without any performance or cost penalty.
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- 2011
13. Temperature Variation Characterization and Thermal Management of Multicore Architectures
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Chen-Yong Cher and Eren Kursun
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Multi-core processor ,Computer science ,business.industry ,Hardware_PERFORMANCEANDRELIABILITY ,Thermal management of electronic devices and systems ,Temperature measurement ,Characterization (materials science) ,Logic synthesis ,Hardware and Architecture ,Embedded system ,Dynamic demand ,Thermal ,Hardware_INTEGRATEDCIRCUITS ,System on a chip ,Electrical and Electronic Engineering ,business ,Software - Abstract
Increased variability affects the efficiency of dynamic power and thermal management. Existing on-chip sensor infrastructure can be used to improve the inherent thermal imbalances among cores in a multicore architecture. Experimental analysis based on live measurements on a special test chip shows reduced on-chip heating with no performance loss.
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- 2009
14. Early Quality Assessment for Low Power Behavioral Synthesis
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Rajarshi Mukherjee, Eren Kursun, and Seda Ogrenci Memik
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Data flow diagram ,Schedule ,Engineering ,Test case ,business.industry ,Design flow ,Weight distribution ,Comparability graph ,Electrical and Electronic Engineering ,business ,Floorplan ,Reliability engineering ,Scheduling (computing) - Abstract
Fast and effective exploration at the early stages of the design flow can yield significant improvement in the quality of the design and substantial reduction in design time. In this paper, we present an efficient technique to evaluate the power dissipation of scheduled Data Flow Graphs (DFGs). Scheduling dictates the compatibility of operations with respect to their assignments to functional units. Generally for scheduled DFGs, this relation is captured in the form of a comparability graph. As a consequence, the topology of the comparability graph determines the solution space available to the subsequent binding stage. In this work, our main contribution is a technique to assess the inherent flexibility of the schedules we start with. We developed early evaluation metrics in order to assess the degree of flexibility inherent in an initial schedule that will eventually affect the quality of the binding solution. Every schedule is associated with a compatibility graph that represents the conflicts and compatibilities among operations with respect to possible binding decisions. Our metric based evaluation technique is based on several properties (such as edge connectivity, edge weight distribution, etc.) of these compatibility graphs. These metrics essentially reflect the amount of freedom that is provided to the binding stage, which enables early assessment and relative comparison of different possible schedules without actually performing the resource-binding step. Our experimental framework integrates scheduling, early metric-based power evaluation, low power binding and power driven iterative rescheduling stages. The correlation between early evaluation and the power measurements after binding is as high as 0.95 and greater than 0.75 for majority of test cases. Experimental results on DFGs from MediaBench suite demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement. Our results show that low power schedule selection is fast and effective. On average, the schedules selected by metric evaluation have 43% less power dissipation than schedules with iterative power improvement, based on a study set of 320 schedules. We also examined the thermal profile of the corresponding solutions. We observed that schedules selected with our metric evaluation technique have on average 12 C lower temperature, and the maximum on-chip temperatures are lower by 18 C compared to the overall average of all schedules. These thermal profiles are obtained using a functional unit-level thermal simulator after block-level floorplanning.
- Published
- 2005
15. PREDICTABILITY IN RT-LEVEL DESIGNS
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Ankur Srivastava, Eren Kursun, and Majid Sarrafzadeh
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Mathematical optimization ,Resource (project management) ,Hardware and Architecture ,Knapsack problem ,Computer science ,High-level synthesis ,Design flow ,General Medicine ,Function (mathematics) ,Electrical and Electronic Engineering ,Predictability ,Time complexity ,Power (physics) - Abstract
The primary objective of this paper is to provide an initial impetus to predictability driven design flow. Predictability is the quantified form of accuracy. The novelty lies in defining and using the idea of predictability. In order to illustrate the basic concepts we focus on the power estimation problem in RT-Level designs. Our experiments showed that predictability at RT-Level could be improved by making the resource delay constraints more stringent. This procedure may come with increased power dissipation. We present an optimal pseudo-polynomial time algorithm to optimize predictability while keeping the increase in power dissipation within a budget. We further extend this algorithm to generate an ∊-approximate solution in polynomial time where ∊ is a user defined parameter. The algorithm probably generates solutions that differ at-most ∊C max from the optimal. The future work would include extending the concept of predictability to other levels of design flow and other cost function. We envision a design automation system which does effective tradeoff between predictability and cost hence enabling efficient design exploration.
- Published
- 2002
16. An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring
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Chen-Yong Cher, Huapeng Zhou, Shi-Chune Yao, Xin Li, Eren Kursun, and Haifeng Qian
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Mathematical optimization ,Computer science ,Entropy (statistical thermodynamics) ,Numerical analysis ,Hardware_PERFORMANCEANDRELIABILITY ,Chip ,Differential entropy ,Computer Science::Hardware Architecture ,Entropy (classical thermodynamics) ,Hardware_INTEGRATEDCIRCUITS ,Entropy (information theory) ,Entropy (energy dispersal) ,Random variable ,Entropy (arrow of time) ,Entropy (order and disorder) - Abstract
Full-chip thermal monitoring is an important and challenging issue in today's microprocessor design. In this paper, we propose a new information-theoretic framework to quantitatively model the uncertainty of on-chip temperature variation by differential entropy. Based on this framework, an efficient optimization scheme is developed to find the optimal spatial locations for temperature sensors such that the full-chip thermal map can be accurately captured with a minimum number of on-chip sensors. In addition, several efficient numerical algorithms are proposed to minimize the computational cost of the proposed entropy calculation and optimization. As will be demonstrated by our experimental examples, the proposed entropy-based method achieves superior accuracy (1.4× error reduction) for full-chip thermal monitoring over prior art.
- Published
- 2012
17. Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory
- Author
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Eren Kursun, Jude A. Rivers, Yuan Xie, and Guangyu Sun
- Subjects
Random access memory ,Hardware_MEMORYSTRUCTURES ,Computer science ,business.industry ,Processor design ,law.invention ,Non-volatile memory ,Microprocessor ,Soft error ,law ,Embedded system ,Computer data storage ,Static random-access memory ,Cache hierarchy ,business ,Dram - Abstract
Spin-transfer Torque Random Access Memory (STT-RAM) emerges for on-chip memory in microprocessor architectures. Thanks to the magnetic field based storage STT-RAM cells have immunity to radiation induced soft errors that affect electrical charge based data storage, which is a major challenge in SRAM based caches in current microprocessors. In this study we explore the soft error resilience benefits and design trade offs of 3D-stacked STT-RAM for multi-core architectures. We use 3D stacking as an enabler for modular integration of STT-RAM caches with minimum disruption in the baseline processor design flow, while providing further interconnectivity and capacity advantages. We take an in-depth look at alternative replacement schemes in terms of performance, power, temperature, and reliability trade-offs to capture the multi-variable optimization challenges microprocessor architectures face. We analyze and compare the characteristics of STT-RAM, SRAM, and DRAM alternatives for various levels of the cache hierarchy in terms of reliability.
- Published
- 2011
18. A Systems Perspective on 3D Integration
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Eren Kursun and Phil Emma
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Computer science ,Management science ,Perspective (graphical) ,Modeling perspective - Published
- 2011
19. Characterizing power and temperature behavior of POWER6-based system
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Carlos Boneti, Mateo Valero, Canturk Isci, Alper Buyuktosunoglu, Eren Kursun, Pradip Bose, Francisco J. Cazorla, Roberto Gioiosa, Victor Jimenez, and Chen-Yong Cher
- Subjects
Surface-mount technology ,Engineering ,Measurement ,Design ,business.industry ,POWER6 ,Performance ,Total system power ,Thread (computing) ,law.invention ,Idle ,Microprocessor ,law ,Electronic engineering ,Power-flow study ,Electrical and Electronic Engineering ,business ,Electrical efficiency ,Experimentation - Abstract
Microprocessor architectures have become increasingly power limited in recent years. Currently power and thermal envelopes dictate peak performance limits more than any other design constraint. In this work, we characterize thermal behavior and power consumption of an IBM POWER6-based system. We perform the characterization at several levels: application, operating system, and hardware level, both when the system is idle, and under load. At hardware level, we report a 25% reduction in total system power consumption by using the processor low power mode. We also study the effect of the hardware thread prioritization mechanism provided by POWER6 on different workloads and how this mechanism can be used to limit power consumption. From this static characterization study we derive a model based on performance counters that allows us to predict the total power consumption of the POWER6 system with an average error under 3% for CMP and 5% for SMT. To the best of our knowledge, this is the first power model of a system including CMP+SMT processors. The work reported in this paper can be generalized to model power consumption for a broader class of systems. Such power modeling is required for studying promising power reduction techniques. In terms of dynamic methods, intelligent thread placement can result in a boost in power efficiency. Our results show that such a power-aware thread placement results in up to 5× improvement in energy-delay squared product for our POWER6 system. © 2011 IEEE.
- Published
- 2011
20. Energy-aware accounting and billing in large-scale computing facilities
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Francisco J. Cazorla, Canturk Isci, Mateo Valero, Alper Buyuktosunoglu, Eren Kursun, Roberto Gioiosa, Victor Jimenez, Pradip Bose, and Ministerio de Ciencia y Tecnología (España)
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Computer systems organization ,Computer science ,business.industry ,Energy management ,Power management ,Cost accounting ,Accounting ,Energy consumption ,Energy conservation ,Throughput accounting ,Hardware ,Environmental full-cost accounting ,Emerging technologies ,Hardware and Architecture ,Energy-aware systems ,Server ,Accounting information system ,Management accounting ,Resource management ,Electrical and Electronic Engineering ,business ,Software - Abstract
Proposals have focused on reducing energy requirements for large-scale computing facilities (LSCFs), but little research has addressed the need for energy-usage-based accounting. Energy-aware accounting and billing benefits LSCF owners and users. This article makes a case for accurate cost accounting and billing, which accounts for user-specific energy usage, and identifies the hardware- and software-level changes necessary to support energy-aware accounting. © 2011 IEEE., This work was supported by a collaboration agreement between IBM and BSC with funds from IBM Research and IBM Deep Computing. It was also supported by the Ministry of Science and Technology of Spain under contracts TIN-2007-60625 and JCI-2008-3688, as well as the HiPEAC Network of Excellence (ICT-217068).
- Published
- 2011
21. Trends and techniques for energy efficient architectures
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Chen-Yong Cher, Roberto Gioiosa, Alper Buyuktosunoglu, Victor Jimenez, Pradip Bose, Eren Kursun, Francisco J. Cazorla, and Mateo Valero
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Instruction set ,Microprocessor ,Power demand ,law ,Computer science ,Systems engineering ,Electronic engineering ,Constraint (mathematics) ,Electrical efficiency ,Efficient energy use ,law.invention - Abstract
Microprocessor architectures have become increasingly power limited in recent years. Currently power and thermal envelopes dictate peak performance limits more than any other design constraint. As voltage scaling has slowed down, innovative techniques have been pursued to improve the power efficiency of the increasingly demanding multi-core architectures. In this paper we look at recent trends in multi-cores with a special focus on trends and techniques to address these challenges.
- Published
- 2010
22. Session details: Microarchitectures and scheduling
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Eren Kursun and Amy Novak
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business.industry ,Computer science ,Scheduling (production processes) ,Session (computer science) ,business ,Computer network - Published
- 2010
23. 3D system design: A case for building customized modular systems in 3D
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Philip G. Emma and Eren Kursun
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Focus (computing) ,Engineering ,Market segmentation ,Packaging engineering ,business.industry ,Distributed computing ,Server ,Reliability (computer networking) ,Electronic engineering ,Systems design ,Dimension (data warehouse) ,Modular design ,business - Abstract
3D promises a new dimension in composing systems by aggregating chips. Literally. While the most common uses are still tightly connected with its early forms as a packaging technology, new application domains have been emerging. As the underlying technology continues to evolve, the unique leverages of 3D have become increasingly appealing to a larger range of applications: from embedded/mobile applications to servers and memory systems. In this paper we focus on the system-level implications of 3D technology, trying to differentiate the unique advantages that it provides to different market segments and applications.
- Published
- 2010
24. Analysis of spatial and temporal behavior of threedimensional multi-core architectures towards run-time thermal management
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Eren Kursun, J. Wakil, and M. Iyengar
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Engineering ,Multi-core processor ,business.industry ,Interconnectivity ,law.invention ,Power (physics) ,Technology management ,Microprocessor ,law ,Limit (music) ,Heat transfer ,Electronic engineering ,Performance improvement ,business - Abstract
3D integration provides number of advantages such as improved interconnectivity and packaging density, which can provide higher performance microprocessors as well as better memory hierarchies. Yet thermal characteristics limit the potential performance improvement in many cases. In this study we investigate the thermal behavior of high performance and high power microprocessor stacks, focusing on 3D-specific challenges. We investigate both the static/spatial and temporal behavior of microprocessor stacks towards assessing feasibility of stacking alternatives and effective management of on-chip temperatures.
- Published
- 2010
25. Power-efficient, reliable microprocessor architectures
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Prabhakar Kudva, Chen-Yong Cher, Victor Zyuban, Hans M. Jacobson, Jude A. Rivers, Indira Nair, Hendrik F. Hamann, Alan J. Weger, John A. Darringer, Meeta S. Gupta, Pradip Bose, Jeonghee Shin, Alper Buyuktosunoglu, Eren Kursun, and Niti Madan
- Subjects
Engineering ,Focus (computing) ,business.industry ,Reliability (computer networking) ,Chip ,Power (physics) ,Reliability engineering ,law.invention ,Microprocessor ,Work (electrical) ,law ,Embedded system ,Systems design ,Modeling and design ,business - Abstract
Next generation system designs are challenged by multiple "walls": among them, the inter-related impediments offered by power dissipation limits and reliability are particularly difficult ones that all current chip/system design teams are grappling with. In this paper, we first describe the attendant challenges in integrated (multi-dimensional) pre-silicon modeling and the solution approaches being pursued. Later, we focus on leading edge solutions for power, thermal and failure-rate mitigation that have been proposed in our R&D work over the past decade.
- Published
- 2010
26. Variation-aware thermal characterization and management of multi-core architectures
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Eren Kursun and Chen-Yong Cher
- Subjects
Thermal efficiency ,Engineering ,Multi-core processor ,business.industry ,Hardware_PERFORMANCEANDRELIABILITY ,Chip ,Power (physics) ,Thermal ,Dynamic demand ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,System on a chip ,business ,Electrical efficiency - Abstract
The accuracy and efficiency of dynamic power and thermal management are both affected by the increased levels of on-chip variation, mainly because dynamic thermal management schemes are oblivious to the variation characteristics of the underlying hardware. We propose a technique that utilizes the existing on-chip sensor infrastructure to improve the inherent thermal imbalances among different cores in a multi-core architecture. Thermal sensor readings are compiled to generate an on-chip variation map, which is provided to the system power/thermal management to effectively manage the existing on-chip variation. Experimental analysis based on live measurements on a special test-chip shows reduced on-chip heating with no performance loss, which improves the power/thermal efficiency of the chip at no cost.
- Published
- 2008
27. Fine grain 3D integration for microarchitecture design through cube packing exploration
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Yuchun Ma, Glenn Reinman, Yongxiang Liu, Jason Cong, and Eren Kursun
- Subjects
Interconnection ,Engineering ,business.industry ,Three-dimensional integrated circuit ,Hardware_PERFORMANCEANDRELIABILITY ,Integrated circuit design ,Floorplan ,Microarchitecture ,Computational science ,Reduction (complexity) ,Electronic engineering ,Performance improvement ,business ,Block (data storage) - Abstract
Most previous 3D IC research focused on "stacking" traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose techniques that enable efficient exploration of the 3D design space where each logical block can span more than one silicon layers. Although further power and performance improvement is achievable through fine grain 3D integration, the necessary modeling and tool infrastructure has been mostly missing. We develop a cube packing engine which can simultaneously optimize physical and architectural design for effective utilization of 3D in terms of performance, area and temperature. Our experimental results using a design driver show 36% performance improvement (in BIPS) over 2D and 14% over 3D with single layer blocks. Additionally multi-layer blocks can provide up to 30% reduction in power dissipation compared to the single-layer alternatives. Peak temperature of the design is kept within limits as a result of thermal-aware floorplanning and thermal via insertion techniques.
- Published
- 2007
28. Reducing the latency and area cost of core swapping through shared helper engines
- Author
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Anahita Shayesteh, Suleyman Sair, Eren Kursun, Glenn Reinman, and Timothy Sherwood
- Subjects
Engineering ,Multi-core processor ,Logic synthesis ,business.industry ,Embedded system ,Integrated circuit design ,Thermal management of electronic devices and systems ,Latency (engineering) ,business - Abstract
Technologies scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature management techniques. To combat these trends, we explore the use of core swapping on microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines. The microcore architecture presents an ideal platform for core swapping thanks to helper engines that maintain the state of each process in a shared fabric surrounding the cores, reducing the impact of core swapping 43% on average while showing promising thermal reduction. It also has favorable performance when compared to other thermal management techniques. Furthermore, we evaluate alternative approaches to spending the area overhead of the additional microcore, including larger microcores, CMP cores, and SMT cores with different thermal management techniques.
- Published
- 2006
29. Low-Overhead Core Swapping for Thermal Management
- Author
-
Timothy Sherwood, Eren Kursun, Anahita Shayesteh, Glenn Reinman, and Suleyman Sair
- Subjects
Thermal efficiency ,Multi-core processor ,Engineering ,business.industry ,Embedded system ,Thermal ,Process (computing) ,Overhead (computing) ,State (computer science) ,Dissipation ,business ,Chip - Abstract
Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature management techniques. To combat these trends, we evaluate the thermal efficiency of the microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines. We further investigate activity migration (core swapping) as a means of controlling the thermal profile of the chip in this study. Specifically, the microcore architecture presents an ideal platform for core swapping thanks to helper engines that maintain the state of each process in a shared fabric surrounding the cores. This results in significantly reduced migration overhead, enabling seamless swapping of cores. Our results show that our thermal mechanisms outperform traditional Dynamic Thermal Management (DTM) techniques by reducing the performance hit caused by slowing/swapping of cores. Our experimental results show that the microcore architecture has 86% fewer thermally critical cycles compared to a conventional monolithic core.
- Published
- 2005
30. Transistor level budgeting for power optimization
- Author
-
Majid Sarrafzadeh, Eren Kursun, and Soheil Ghiasi
- Subjects
Mathematical optimization ,Maximum power principle ,Computer science ,Low-power electronics ,Circuit design ,Design flow ,Electronic engineering ,Integrated circuit design ,Circuit complexity ,Power optimization ,Electronic circuit - Abstract
We present an optimal budget distribution method for low power circuit design using transistor sizing. The algorithm distributes the available budget inside the functional unit by efficient traversal of the Series Parallel Graph representation. The technique can be efficiently applied at different abstraction levels of the design as well as toward other optimization goals (such as area optimization). The complexity is O(n) in terms of the number of transistors in the circuit. Incorporating our method in the design flow yields significant improvements in power consumption. Experiments on circuits extracted from MCNC91 benchmark suite have revealed improvements up to 59% in average power and 65% in maximum power dissipation compared to an alternative budget distribution algorithm.
- Published
- 2004
31. Global resource sharing for synthesis of control data flow graphs on FPGAs
- Author
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Seda Ogrenci Memik, Eren Kursun, Roozbeh Jafari, and Gokhan Memik
- Subjects
Resource (project management) ,Theoretical computer science ,Computer science ,Distributed computing ,Resource allocation ,Heuristics ,Field-programmable gate array ,Measure (mathematics) ,Shared resource - Abstract
In this paper we discuss the global resource sharing problem during synthesis of control data flow graphs for FPGAs. We first define the Global Resource Sharing (GRS) problem. Then, we introduce the Global Inter Basic Block Resource Sharing (GIBBS) technique to solve the GRS problem. We developed five heuristics to solve the GRS problem. The first tries to minimize the number of connections between modules, the second considers the area gain, the third uses the criticality of operations assigned to resources as a measure for deciding on merging any given pair of resources, the fourth tries to capture common resource chains and overlap those to minimize both area and delay, and the fifth is the combination of these heuristics. While applying resource sharing, we also consider the execution frequency of the basic blocks. Using our techniques we synthesized several CDFGs representing applications from MediaBench suite. Our results show that, we can reduce the total area requirement by 44% on average (up to 59%) while increasing the execution time by 6% on average.
- Published
- 2003
32. Early evaluation techniques for low power binding
- Author
-
Majid Sarrafzadeh, Eren Kursun, Ankur Srivastava, and Seda Ogrenci Memik
- Subjects
Data flow diagram ,Test case ,Job shop scheduling ,Computer science ,High-level synthesis ,Low-power electronics ,Parallel computing ,Energy consumption ,Scheduling (computing) ,Power optimization - Abstract
This paper presents effective metrics to evaluate the power dissipation of scheduled data flow graphs (DFGs). This enables early evaluation of schedules without performing the computationally expensive resource-binding step. Our metrics correlate heavily (as high as 0.95 and > 0.75 for most test cases) with power dissipation values obtained after resource binding and rescheduling for power optimization steps. An experimental flow that integrates path-based scheduling, power optimal binding and power driven iterative rescheduling stages is constructed. The flow integrates commercial tools; like Synopsys, VSS and academic compilers like SUIF in a common optimization framework. Experimental results on DFGs from MediaBench suit also demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement. Hence metric based evaluation enables fast design exploration at early stages.
- Published
- 2002
33. Algorithmic aspects of uncertainty driven scheduling
- Author
-
Seda Ogrenci Memik, Majid Sarrafzadeh, Ankur Srivastava, and Eren Kursun
- Subjects
Theoretical computer science ,Computational complexity theory ,Job shop scheduling ,Computer science ,Robustness (computer science) ,High-level synthesis ,Design flow ,Processor scheduling ,Graph theory ,Dynamic priority scheduling ,Computer Science::Operating Systems ,Scheduling (computing) - Abstract
In this paper we discuss the algorithmic aspects of uncertainty driven scheduling which is a new design paradigm. Slack oriented design flow could be used to address the uncertainty problem in high level synthesis. We formalize the concept of slack and discuss different variations of the slack driven scheduling problem. The complexity issues are studied in detail and algorithms are proposed to solve the problem. These algorithms and proofs heavily exploit the concepts and techniques of graph theory and combinatorial optimization problems.
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