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The formation of a copper silicide interfacial layer by surface reaction in a plasma enhanced chemical vapour deposition (PECVD) system has been studied. Tri-methyl silane (TMS, SiH(CH"3)"3) has been employed as the Si source as an alternative to more conventional silane (SiH"4) approach. TMS precursor has been chosen due to improved control of Si penetration into the copper [S. Chhun, L.G. Gosset, N. Casanova, J.F. Guillaumond, P. Dumont-Girard, X. Fedespiel, R. Pantel, V. Arnal, L. Arnaud, J. Torres, Microelectronic Engineering 76 (2004) 106-112]. AFM, SIMS, light scattering, FT-IR spectroscopy and dielectric constant measurements were performed on various stacks to evaluate CuSiN formation. Resistance, leakage, and electromigration (EM) reliability characterization were performed on test structures based on 65nm design rules. Nitridation step in silicidation process was shown to have positive impact on EM reliability, minimizing the line resistance increase.

The FSG (fluorine-doped silicon glass) was introduced as dielectric for copper interconnects in order to take advantage of its lower dielectric constant. With a gain of 18% in the constant value, it makes the shrink of metal dimension possible for 0.12- µm technology devices with limited cross-talks or delays in the information transmission. In spite of its strong sensitivity to water and moisture absorption, we could integrate this material in the dual damascene structure for copper application for 0.12- µm technology. The use of appropriate capping layer and optimisation of fluorine content made the integration possible with optimal dielectric properties.

The increasing use of closely spaced narrow interconnections and generally reduced feature sizes in modern IC technology has led to a requirement for anisotropic etching of high performance metallizations. Etching processes addressing this requirement should exhibit good uniformity and reproducibility, a good selectivity over underlying materials and the mask to ensure a good pattern fidelity. WGe based barriers have good prospects in sub-micron contact barrier technology. The purpose of the present paper is to investigate the reactive ion etching (RIE) of blanket deposited AlCu/WGe/sub x//Ti films on SiO/sub 2/ in a chlorine based plasma chemistry employing a Cl/sub 2/, SiCl/sub 4/, He mixture. Various aspects of the metal stack etching including profile control, etch rate and selectivity to oxide are discussed in detail.

An enhanced trench first hard mask (TFHM) backend integration architecture has been developed to facilitate straightforward ultra low-k (ULK) material insertion and to enable rapid yield learning at the 65nm technology node. Parametric, yield, reliability, and RC performance data are presented for the fully-integrated, improved TFHM 300mm ULK backend

Mechanical reliability is widely recognized as the primary obstacle to productionization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SOI substrates.

Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An alternate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k" and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.

This study is on oxide etch selective to nitride using a C/sub 4/F/sub 8/-CO-Ar-O/sub 2/ chemistry in a RIE chamber. It has been tested in a manufacturing environment on several applications for 16 and 64 megabit DRAM chips. Film stacks tested included a BPSG/nitride self-aligned contact type of application and a BPSG/nitride/oxide application. Aspect ratios ranged from 4:1 to 8:1. Critical dimensions were typically 0.4 /spl mu/m and 0.3 /spl mu/m, but for one application, oxide etch had to finally occur in a 0.09 /spl mu/m wide space. Process development started with a design of experiments on patterned wafers in order to understand the major trends of the chemistry. The wafers were analysed by SEM. Fine tuning of processes for each application involved optical emission spectroscopy (OES) and electrical test yield analysis.

This paper compares three different schemes to pattern dual damascene (DD) structures. The Self Aligned (SA), Via First (VF), and Trench First (TF) architectures are compared in terms of complexity, process latitude, and sensitivity to lithography misalignment using 0.18-/spl mu/m copper/oxide two metal level structures. The integration of thick metal lines is also discussed, for the upper levels of interconnects. This study shows that the VF architecture has the best via chain yield, regardless of the test configuration, and allows to pattern thick metal DD structures with high yield. The VF technique was used to manufacture a six copper level device, with functional yield similar to that obtained with an AlCu/HSQ Back End Of Line (BEOL).