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Spintronics attracts much attention because of the potential to build novel spin-based devices which are superior to nowadays charge-based microelectronic devices. Silicon, the main element of microelectronics, is promising for spin-driven applications. Understanding the details of the spin propagation in silicon structures is a key for building novel spin-based nanoelectronic devices. We investigate the surface roughness- and phonon-limited electron mobility and spin relaxation in ultra-thin silicon films. We show that the spin relaxation rate due to surface roughness and phonon scattering is efficiently suppressed by an order of magnitude by applying tensile stress. We also demonstrate an almost twofold mobility increase in ultra-thin (0 0 1) SOI films under tensile [1 1 0] stress, which is due to the usually neglected strain dependence of the scattering matrix elements.

Properties of semiconductors provided by the electron spin are of broad interest because of their potential for future spin-driven microelectronic devices. Silicon is the main element of modern charge-based electronics, thus, understanding the details of the spin propagation in silicon structures is key for novel ��

Display Omitted Electron spin lifetime increases in (001) thin silicon film under shear strain.Intervalley scattering is suppressed with applied shear strain in 110].Spin lifetime is enhanced for in-plane spin injection orientation. Electron spin attracts much attention as an alternative to the electron charge degree of freedom for low-power reprogrammable logic and non-volatile memory applications. Silicon appears to be the perfect material for spin-driven applications. An order of magnitude enhancement of the electron spin lifetime in (001) silicon thin films by shear strain is shown. It is demonstrated that spin-flip scattering processes between the two 001] valleys are responsible for spin relaxation in thin (001) silicon films. The enhancement of the spin lifetime is the result of the suppression of inter-valley scattering caused by the shear strain induced equivalent 001] valley splitting.

With complementary metal-oxide semiconductor feature size rapidly approaching ultimate scaling limits, the electron spin attracts much attention as an alternative to the electron charge degree of freedom for low-power reprogrammable logic and nonvolatile memory applications. Silicon, the main element of microelectronics, appears to be the perfect material for spin-driven applications. Despite an impressive progress in understanding spin properties in metal-oxide-semiconductor field-effect transistors (MOSFETs), spin manipulation in a silicon channel by means of the electric field–dependent Rashba-like spin–orbit interaction requires channels much longer than 20 nm channel length of modern MOSFETs. Although a successful realization of the spin field-effect transistor seems to be unlikely without a new concept for an efficient way of spin manipulation in silicon by purely electrical means, it is demonstrated that shear strain dramatically reduces the spin relaxation, thus boosting the spin lifetime by an order of magnitude. Spin lifetime enhancement is achieved by lifting the degeneracy between the otherwise equivalent unprimedsubbands by [110] uniaxial stress. The spin lifetime in stressed ultra-thin body silicon-on-insulator structures can reach values close to those in bulk silicon. Therefore, stressed silicon-on-insulator structures have a potential for spin interconnects.

Semiconductor spintronics is promising, because it allows creating microelectronic elements which are smaller and consume less energy than present charge-based devices. Silicon is the main element of modern charge-based electronics, thus, understanding the peculiarities of spin propagation in silicon is the key for designing novel devices. We investigate the electron momentum and the spin relaxation in thin (001) oriented SOI films using a k ⋅ p-based approach with spin degree of freedom properly included. We demonstrate that shear strain routinely used to enhance the electron mobility can boost the spin lifetime by an order of magnitude.

We study the transport properties of the Datta–Das spin field-effect transistor built on InAs and Si. First, we demonstrate that the amplitude of the magnetoresistance oscillations as a function of the band mismatch between the ferromagnetic contacts and the semiconductor channel made of InAs decreases dramatically with increasing temperature. A shorter InAs channel is needed to create an InAs-based SpinFET which will operate at higher temperatures. Second, we show that the [1 0 0] orientation of the fin is preferable for silicon SpinFETs due to stronger modulation of the conductance as a function of spin–orbit interaction and magnetic field. Short silicon fins can be used for current modulation as a function of the conduction band mismatch between the channel and the ferromagnetic contacts only at relatively low temperatures. In contrast, longer silicon channels allow a TMR modulation at room temperature by changing the strength of the spin–orbit interaction through the gate bias.

We investigate the transport properties of ballistic spin field-effect transistors (SpinFET). We show that temperature exerts a significant influence on the device characteristics. For the InAs-based SpinFET an ambient temperature higher than T=150K leads to the absence of the ability to modulate the value of the tunneling magnetoresistance through changing the bandgap mismatch between the channel and the contacts. The length of the semiconductor channel impacts significantly the device characteristics. A shorter channel is preferred for potential operations at room temperature. For the silicon-based SpinFET the spin-orbit interaction has to be taken in the Dresselhaus form. We demonstrate that silicon fins with [100] orientation exhibit a stronger dependence on the value of the spin-orbit interaction and are thus preferable for practical realization of SpinFETs.

We investigate the properties of ballistic fin-structured silicon spin field-effect transistors. The spin transistor suggested first by Datta and Das employs spin-orbit coupling to introduce the current modulation. The major contribution to the spin-orbit interaction in silicon films is of the Dresselhaus type due to the interface-induced inversion symmetry breaking. The subband structure in silicon confined systems is obtained with help of a two-band k·p model and is in good agreement with recent density functional calculations. It is demonstrated that fins with [100] orientation display a stronger modulation of the conductance as function of spin-orbit interaction and magnetic field and are thus preferred for practical realizations of silicon SpinFETs.

The electron spin properties of semiconductors are of huge interest because of their potential for future spin-driven microelectronic devices. Modern charge-based electronics is dominated by silicon, and understanding the details of spin propagation in silicon structures is key for novel spin-based device applications. The peculiarities of the subband structure and details of the spin propagation in surface layers and thin silicon films in the presence of the spin-orbit interaction is under research. We investigate the influence of the spin injection direction on the spin relaxation. Beginning with the four-component wave functions, we show that the surface roughness induced spin intersubband relaxation matrix elements get reduced for an in-plane spin injection compared to perpendicular-plane spin injection, henceforth the corresponding spin relaxation rate (time) is diminished (enhanced). In order to explain this observation we point out that at the spin relaxation hot spots the perpendicular-plane spin injection results in a maximal spin randomization at any in-plane momentum, which increases the spin relaxation rate and decreases the spin lifetime as compared to an in-plane spin injection.

We present and validate a novel physics-based model for hot-carrier degradation. The model incorporates such essential ingredients as a superposition of the multivibrational bond dissociation process and single-carrier mechanism, dispersion of the bond-breakage energy, interaction of the electric field and the dipole moment of the bond, and electron-electron scattering. The main requirement is that the model has to be able to cover HCD observed in a family of MOSFETs of identical architecture but with different gate lengths under diverse stress conditions using a unique set of parameters.

Oscillators belong to the group of fundamental building blocks and are ubiquitous in modern electronics. Especially spin torque nano oscillators are very attractive as cost effective on-chip integrated microwave oscillators, due to their nano-scale size, frequency tunability, broad temperature operation range, and CMOS technology compatibility. Recently, we proposed a micromagnetic structure capable of operating as non-volatile flip flop as well as a spin torque nano oscillator. The structure consists of three anti-ferromagnetically coupled stacks (two for excitation A, B and one for readout Q) and a shared free magnetic layer. Micromagnetic simulations show a current regime, where the structure exhibits large, stable, and tunable in-plane oscillations in the GHz range without the need of an external magnetic field or an oscillating current. In this work the dependence of these oscillations on the shared free layer geometry at a fixed input current is studied. It is shown that the precessional frequency can be controlled by the dimensions of the shared free layer. Most efficient is to utilize the layer thickness to control the precessional frequency, but also changing the layer length can be exploited.

Spintronics attracts much attention because of the potential to build novel spin-based devices which are superior to nowadays charge-based microelectronic devices. Silicon, the main element of microelectronics, is promising for spin-driven applications. We investigate the surface roughness and electron-phonon limited spin relaxation in silicon films taking into account the coupling between the relevant valleys through the Γ-point. We demonstrate that applying uniaxial stress along the [110] direction considerably suppresses the spin relaxation.

We present the first physics-based model for hot-carrier degradation which is able to capture degradation in both short- and long-channel SiON nMOSFETs. Degradation is considered to be due to the breaking of Si-H bonds at the SiON/Si interface. Contrary to previous modeling attempts, our approach now correctly considers the intricate superposition of multivibrational bond excitation and bond rupture induced by a solitary hot carrier based on experimentally confirmed distributed activation energies. All processes are treated as competing pathways, leading to bond dissociation from all vibrational levels. These rates are determined by the carrier acceleration integral and by the bond energetics. The acceleration integral is calculated using the carrier energy distribution. Corresponding distribution functions are found by a thorough solution of the Boltzmann transport equation. We demonstrate that electron-electron scattering plays the dominant role. As for the bond energetics, we consider the dispersion of the activation energy as well as its reduction induced by the interaction of the bond dipole moment with the electric field. All the model ingredients are incorporated into the same simulation framework based on the deterministic solver of the Boltzmann transport equation, ViennaSHE.

The breathtaking increase in performance of integrated circuits is supported by the continuous miniaturization of CMOS devices. However, growing technological challenges and soaring costs are gradually bringing scaling to an end, and research on alternative technologies and computational principles becomes important. Spin attracts attention as alternative to the charge degree of freedom for computations and non-volatile memory applications. Recent progress and challenges in simulating spin-based devices are briefly reviewed. Special attention is paid to methods for enhancing the electron spin lifetime in silicon inversion layers and thin films necessary for realizing spin-based field-effect transistors. A new rapidly switching structure for spin-based non-volatile memory cell, MRAM, was optimized by means of micromagnetic simulations. Several memory cells can be assembled in logic gates capable to perform logic operations. We demonstrate that an implication gate is promising for realizing intrinsic non-volatile logic-in-memory architectures.

Electron spin attracts much attention as an alternative degree of freedom for low-power reprogrammable logic and non-volatile memory applications. Silicon appears to be the perfect material for spin-driven applications. Recent progress and challenges in simulating spin-based devices are briefly reviewed. Strain-induced enhancement of the electron spin lifetime in silicon thin films is predicted and its impact on spin transport in SpinFETs is discussed. A new design of the spin-based nonvolatile memory cell, MRAM, is presented. By means of micromagnetic simulations it is demonstrated that the new design leads to a reduction of the switching time of the cell. Any two memory cells from a MRAM array can form an implication logic gate. It is shown how by using these gates an intrinsic non-volatile logic-in-memory architecture is realized.

In this chapter we investigate spin relaxation in thin silicon films. We employ a k·p based approach to investigate surface roughness and phonon induced momentum and spin relaxation matrix elements. We show that the spin relaxation matrix elements strongly decrease with shear strain increased. In order to meet computational requirements with actual resources needed for relaxation time calculations, we demonstrate a way to find the subband wave function from the k·p model analytically. We consider the impact of the surface roughness and phonons on transport and spin characteristics in ultra-thin SOI MOSFET devices. We show that the regions in the momentum space responsible for strong spin relaxation can be efficiently removed by applying uniaxial shear strain. The spin lifetime in strained films can be improved by orders of magnitude.

We present a novel approach to hot-carrier degradation (HCD) simulation, which for the first time considers and incorporates mechanisms crucial for HCD. First, two main pathways of Si-H bond dissociation, namely bond-breakage triggered by a single hot carrier and induced by multivibrational bond excitation, are combined and considered consistently. Second, we show how drastically electron-electron scattering affects the whole HCD picture. Furthermore, dispersion of the activation energy of bond dissociation substantially changes defect generation rates. Finally, the interaction between the electric field and the dipole moment of the bond leads to interface states created near the source end of the channel. To demonstrate the importance of all these peculiarities we use ultra-scaled n-MOSFETs with a channel gate of 65 nm.

We investigate the surface roughness induced spin relaxation in scaled spin MOSFETs. We show that the regions in the momentum space, responsible for strong spin relaxation, can be efficiently removed by applying uniaxial strain. The spin lifetime in strained films can be improved by orders of magnitude, while the momentum relaxation time determining the electron mobility can only be increased by a factor of two.

We investigate the surface roughness and phonon induced spin and momentum relaxation in ultra-scaled SOI MOSFETs. We show that the spin-flip hot spots characterized by strong spin relaxation can be efficiently removed by applying shear strain resulting in an increase of spin lifetime by orders of magnitude. In contrast, the momentum relaxation time in ultrathin films, which is mostly determined by surface roughness scattering can be only increased by a factor of two, in agreement with strain-induced mobility enhancement data.

We investigate the surface roughness induced spin relaxation in scaled spin MOSFETs. We show that the spin-flip hot spots characterized by strong spin relaxation appear in thin MOSFET channel. Strain can efficiently move these hot spots outside of the states occupied by carriers, resulting in a substantial increase of the spin lifetime.

Semiconductor spintronics is a rapidly developing field with a potentially large impact on microelectronics. Using electron spin may help to reduce power consumption and increase computational speed of modern electronic circuits. Silicon is perfectly suited for spin-based applications: it is characterized by a weak spin-orbit interaction which should result in a long spin lifetime. However, recent experiments indicate the lifetime may get significantly reduced in gated structures. Thus, understanding the peculiarities of the subband structure and details of the spin propagation in surface layers and thin silicon films in presence of the spin-orbit interaction is urgently needed. We investigate the contribution of the spin-orbit interaction to the equivalent valley splitting and calculate the spin relaxation matrix elements by using a perturbative k·p approach. We demonstrate that the valley degeneracy strongly influences the spin relaxation matrix elements. Shear strain is an efficient concept to lift the valley degeneracy, which can considerably suppress the electron spin relaxation in silicon surface layers and thin films.

Semiconductor spintronics is a rapidly developing field with large impact on microelectronics. Using spin may help to reduce power consumption and increase computational speed. Silicon is perfectly suited for spin-based applications. It is characterized by a weak spin-orbit interaction which should result in a long spin lifetime. However, recent experiments indicate the lifetime is greatly reduced in gated structures. Thus, understanding the peculiarities of the spin-orbit effects on the subband structure and details of the spin propagation in surface layers and thin silicon films is urgently needed. We investigate the contribution of the spin-orbit interaction to the equivalent valley splitting and calculate the spin relaxation matrix elements by using a perturbative k ⋅p approach. We demonstrate that applying uniaxial stress along the [110] direction may considerably suppress electron spin relaxation in silicon surface layers and thin films.

Silicon is the main element of modern charge-based electronics. Understanding the details of the spin propagation in silicon structures is elementary for novel spin-based device applications. We investigate valley splitting, surface roughness scattering, and spin relaxation matrix elements in thin silicon films by using a perturbative k·p approach. We demonstrated that applying uniaxial stress along the [110] direction considerably suppresses the intersubband spin relaxation elements.

Significant progress in integrated circuits performance has been supported by the miniaturization of the transistor feature size. With transistor scalability gradually slowing down new concepts have to be introduced in order to maintain the computational speed increase at reduced power consumption for future micro- and nanoelectronic devices. A promising alternative to the charge degree of freedom currently used in MOSFET switches is to take into account the spin degree of freedom. We computationally investigate transport properties of ballistic spin field-effect transistors (SpinFETs). These simulations require a significant amount of computational resources. To achieve the best performance of calculations we parallelize the code for a shared-memory multi-CPU system. As the result of the optimization of the whole model a significant speed-up in calculations is achieved. We demonstrate that the [100] oriented silicon fins are best suited for practical realizations of a SpinFET.

The theoretical predictions [1] and the experiments [2] of spin transfer switching demonstrated that the spin transfer torque random access memory (STTRAM) is one of the promising candidates for future universal memory. The basic element of the STTRAM is a magnetic tunnel junction (MTJ), a sandwich of two magnetic layers separated by a thin non-magnetic spacer (Fig.1a). The reduction of the current density required for switching and the increase of the switching speed are the most important challenges in STTRAM research [3]. It has been demonstrated [4] that the critical current density is decreased in a penta-layer magnetic tunnel junction as shown in Fig.1b.

A spin field-effect transistor (SpinFET) is composed of source and drain contacts which sandwich a semiconductor region [1]. Current modulation is achieved by electrically tuning the gate voltage dependent strength of the spin-orbit interaction in the semiconductor region.

We investigate the transport properties of ballistic spin field-effect transistors. The transistor characteristics are examined for a broad range of parameters including the semiconductor channel length, the conduction band mismatch between the channel and the contacts, the strength of the spin-orbit interaction, and the magnetic field. We show that temperature exerts a significant influence on the device characteristics. For the InAs-based transistors a shorter channel is preferred for potential operations at room temperature. For the silicon-based transistors we demonstrate that the [100] fin orientation displays a stronger dependence of the magnetoresistanse on the strength of the spin-orbit interaction and is therefore best suited for practical realization of the silicon spin transistor.

We investigate the properties of ballistic spin field-effect transistors (SpinFETs). First we show that the amplitude of the tunneling magnetoresistance oscillations decreases dramatically with increasing temperature in SpinFETs with the semiconductor channel made of InAs. We also demonstrate that the [100] orientation of the silicon fin is preferred for practical realizations of silicon SpinFETs due to stronger modulation of the conductance as a function of spin-orbit interaction and magnetic field.

Spintronics attracts at present much interest because of the potential to build novel spin-based devices which are superior to nowadays charge-based microelectronic elements. Utilizing spin properties of electrons opens great opportunities to reduce device power consumption in future electronic circuits. Silicon, the main element of microelectronics, is promising for spin-driven applications. Understanding the details of the spin propagation in silicon structures is a key for building novel spin-based nanoelectronic devices. We investigate the influence of shear strain on surface roughness induced spin relaxation in a thin silicon-on-insulator-based transistor. Shear strain dramatically influences the spin, which opens a new opportunity to boost spin lifetime in a silicon spin field-effect transistor.