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This paper review the FinFET structure as a future transistor for analog and digital electronic circuits, and present its electrical characteristics depending on the important parameters for evaluating the MOSFETs structures like DIBL and Ion/Ioff.

The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the “knowledge’’ from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design.

International audience; In this paper, we report on an enhancement of mm-wave power performances with a vertically scaled AlN/GaN heterostructure. An AlGaN back barrier is introduced underneath a nonintentionally doped GaN channel layer, enabling the prevention of punch-through effects and related drain leakage current under a high electric field while using a moderate carbon concentration into the buffer. By carefully tuning the Al concentration into the back barrier layer, the optimized heterostructure offers a unique combination of electron confinement and low trapping effects up to high drain bias for a gate length as short as 100 nm. Consequently, pulsed (CW) Load-Pull measurements at 40 GHz revealed outstanding performances with a record power-added efficiency of 70% (66%) under high output power density at VDS = 20 V. These results demonstrate the interest of this approach for future millimeter-wave applications.

FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of device Vtsat flavors is enabled in this experiment, presenting excellent device performances at different operating voltages of 0.55V, 0.8V and 1.2V. All results indicates that devices with no LDD and one less mask in FinFET architecture achieve lower cost, compelling performance and area scaling compared to devices with LDD, for high performance and low power applications.

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L)×10 -7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL=25.15𝜂𝐿 𝑔 −3 𝑡 𝑠𝑖 2 , where 𝜂 is a static feedback coefficients between 0 and 1. The 𝜂 is found to be between 0.5 and 1.0 in this model. √ 𝑡 𝑜𝑥1 ∙ 𝑡 𝑜𝑥2 The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.

We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub-10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length Lg and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/Lg)10-7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET.

Технологія CMOS досить довго панує в світі кремнієвих матеріалів і вже наближається до своїх обмежень. Зі зменшенням товщини оксидного шару затвора зростає струм витоку, що різко знижує надійність пристрою. Впровадження high-k матеріалів значно зменшило вплив короткоканальних ефектів (SCEs) в нанопристроях. Ці матеріали також забезпечують електричну стабільність і зарекомендували себе як масштабовані. Різні пристрої було розроблено для різних оксидів затвора, таких як SiO2, і high-k матеріалів, таких як Si3N4, Al2O3, ZrO2 та HfO2. Параметри цих high-k діелектричних матеріалів порівнюються з характеристиками SiO2 в тризатворному (TG) пристрої SOI FinFET. TG SOI FinFETs з довжинами затвора 14, 10 і 8 нм реалізовані для всіх діелектричних матеріалів з урахуванням еквівалентної товщини оксиду в 1 нм для SiO2. Для всіх TG SOI FinFETs досліджено і проаналізовано параметри, які стосуються SCEs, такі як спад граничної напруги, відношення струмів включення та виключення і DIBL. Спостереження за електричними характеристиками пристроїв привело до висновку, що струм Ion знаходиться на одному рівні для всіх геометричних довжин затвора. Але струми витоку різко знижуються з використанням HfO2 як діелектричного матеріалу затвора, що забезпечує найвищу швидкість перемикання пристрою поряд з відмінним контролем короткокальних параметрів. Результати показують, що пристрої на основі high-k діелектричних матеріалів забезпечують покращені характеристики за рахунок зниження струму витоку, тим самим досягаючи зменшення впливу SCEs. Було також встановлено, що TG SOI FinFET на основі HfO2 є найбільш ефективним серед усіх інших транзисторів навіть при довжині каналу 8 нм. The CMOS technology has been dominated long enough by the silicon material world and it has been approaching to its limitations. With contracting magnitudes of thicknesses of the gate oxide layer, leakage current worsens which drastically reduces the device reliability. In the nano regime device, the introduction of high-k materials has brought down the Short Channel Effects (SCEs) significantly. They also provide electrical stability and have proven to be scalable. Different devices are evolved for different gate oxides such as SiO2 and high-k materials like Si3N4, Al2O3, ZrO2 and HfO2. These high-k dielectric materials are compared with the performance of SiO2 in a Tri-Gate (TG) SOI FinFET device. TG SOI FinFETs with 14, 10 and 8 nm gate lengths are implemented for all the dielectric materials considering an equivalent oxide thickness of 1 nm for SiO2. Since the devices are developed in the nano regime, the parameters relating to SCEs such as the roll-off of threshold voltage, on-to-off current ratio and DIBL are investigated and analyzed for all the TG SOI FinFETs. Observation of the electrical characteristics of the devices led to the culmination that the Ion current is at the same level for all geometrical gate lengths. But the leakage currents reduced drastically with HfO2 as the gate dielectric material rendering the highest switching speed of the device along with excellent control over the short channel parameters. The results inevitably show that high-k dielectric material based devices provide enhanced performance by reducing the leakage current, thereby attaining degradation in the SCEs. It has also been perceived that the HfO2 based TG SOI FinFET is found to be the most superior among all others even at 8 nm channel length.

Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 104, while our four channels GAA MOSFET showed a value of 103. In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.

Drain Induced Barrier Lowering(DIBL) effect is prominent as the feature size of MOS device keep diminishing. In this paper, a threshold voltage model for small-scaled strained Si nMOSFET is proposed to illustrate the DIBL effect, which is based on solving 2-D Poisson equation. By simulation, the relationship between DIBL and channel length, gate oxide thickness, Ge content, and channel doping concentration has been analyzed and the way to restrain the DIBL effect has been acquired. By using ISETCAD device simulator, the validity of the model has also been proved.

A physics-based compact model including short-channel effects (SCEs) is presented for undoped (or lightly doped) symmetric double-gate (DG) MOSFETs. Our approach allows an accurate description of the device behavior down to 60 nm with a simple set of equations. It is shown that the subthreshold current, the threshold voltage roll-off and the DIBL predicted by the analytical solution are in close agreement with 2-D numerical simulations performed with Atlas. The mobility degradation due to both transverse and longitudinal fields is taken into account but the channel length modulation (saturation regime) is not addressed in this paper. In order to demonstrate that the model is well-suited for circuit simulation, the results of the dynamic model based on an explicit formulation of the mobile charge density are also presented. (C) 2007 Elsevier Ltd. All rights reserved.

This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with gate oxide HfO2 are simulated and compared with conventional gate oxide SiO2 for the same structure. As a result, it was observed that the GAA with high K dielectric gate oxide has more possibility to optimize the Fin width with improved performance. All the simulations are performed on 3-D TCAD device simulator.

Semiconductor technology has reached an end in the manufacture of conventional Metal Oxide semiconductor Field Effect Transistor (MOSFET). The continuous scaling of semiconductor devices has kept pace with Moore’s law and transistors below 1µm are grouped under deep sub-micron (DSM) technology node. But this trend seem to end beyond deep sub micron levels due to main design constraints such as short channel effects (SCE) , and variations in process design parameters leading to high leakage currents. Silicon material processes technology has undergone a change in process material and technology beyond 180nm node. For DSM technology nodes leakage current dominates the devices. Circuit designing using MOSFETs at deep sub micron levels, needs a careful study of the behaviour of short channel devices for the parameter variations such as threshold voltage, channel length leading to high leakage currents and poor performance of devices. In this paper we have presented the behaviour of NMOS metal oxide semiconductor field effect transistor (MOSFETs) for 90nm technology node in detail and finally compared with 180nm and 45nm nodes. The simulations have been carried out using libraries from TSMC foundry and the device has been simulated using Virtuoso Cadence Spectre Simulator version 6.1.5 with HSPICE.

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.

In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL). To assess the performance of the proposed structure, some device characteristics of the structure have been compared with those of silicon on insulator-FinFET (SOI-FinFET) and Bulk-FinFET structures (where the BOX layer covers all the regions except the channel region). In addition, we compare different characteristics of static random access memory (SRAM) cells based on the proposed device structure as well as SOI-FinFET and Bulk-FinFET structures. The characteristics include standby power consumption, and read static noise margin (SNM). Finally, the behavior of the proposed device in the presence of dimensional variations (channel length and thin film thickness variations) and random dopant fluctuation (RDF) are studied and compared with those of the other two structures. (C) 2012 Elsevier B.V. All rights reserved.

To manage the increasing static leakage in low power applications, solutions for leakage reduction are sought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm groovedgate nMOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS in ultralow power applications. The simulation results show that leakage contributing currents like the subthreshold current, punchthrough current and tunneling leakage current are reduced. The oxide thickness can be increased without increase in the gate induced drain leakage current, and ON-OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is reduced drastically, as well as be applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this work. &nbsp

This work focuses on the determination of the valid device domain for the use of the Top of the barrier (ToB) model to simulate quantum transport in nanowire MOSFETs in the ballistic regime. The presence of a proper Source/Drain barrier in the device is an important criterion for the applicability of the model. Long channel devices can be accurately modeled under low and high drain bias with DIBL adjustment. Keywords-component; nanowires; top of the barrier; MOSFET; ballistic transport model; DIBL; tunneling current; top-of-the- barrier; subthreshold- slope; Tight-Binding;Short channel effects .

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drain induced barrier lowering is investigated with respect to the technological parameters. This work could serve as a guideline for technology optimization and design of JL VeSFETs.

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance., {"references":["C. -H. Choi, K. Y. Nam, Z. Yu, and R. W. Dutton, \"Impact of gate\ndirect tunneling current on circuit performance: A simulation study,\"\nIEEE Trans. Electron Devices, vol. 48, pp. 2823-2829, Dec. 2001.","International Technology Roadmap for Semiconductors, http:\n//public.itrs.net/Files /2001 ITRS /Home.html.","Y. Taur, \"CMOS Design Near the Limits of Scaling,\" IBM J.R&D, vol.\n46(2/3), pp. 213-222, Mar./May 2002.","N. Sirisantana, Wei, L. and Roy, K. , \"High Performance Low-Power\nCMOS Circuits Using Multiple Channel Length and Multiple Oxide\nThickness,\" in Proc. of IEEE ICCD, pp. 227-232, Sept. 2000.","F. Hamzaoglu and M. Stan, \"Circuit-Level Techniques to Control Gate\nLeakage for sub 100nm CMOS,\" Proc. ISLPED, pp. 60-63, Aug. 2002.","K. Roy, S. Mukhopadhyay, and H. M. Meimand, \"Leakage Current\nMechanisms and Leakage Reduction Techniques in Deep-\nSubmicrometer CMOS Circuits,\" Proceedings of the IEEE, vol. 91,no. 2,\npp. 305-327, February 2003.","D. Lee, D. Blaauw, and D. Sylvester ,\"Analysis and Minimization\nTechniques for Total Leakage Considering Gate Oxide Leakage,\" in\nProc. Of ACM/IEEE DAC, pp. 175-180, Jun. 2003.","D. Lee, D. Blaauw, and D. Sylvester, \"Gate Oxide Leakage Current\nAnalysis and Reduction for VLSI Circuits,\" IEEE Transactions on VLSI\nSystems, vol. 12, no. 2, pp. 155-166, February 2004.","A. K. Sultania, D. Sylvester, and S. S. Sapatnekar, \"Tradeoffs Between\nGate Oxide Leakage and Delay for Dual Tox Circuits,\" in Proceedings of\nDesign Automation Conference, 2004, pp. 761-766.\n[10] N. Sirisantana and K. Roy;, \"Low-power Design using Multiple Channel\nLengths and Oxide Thicknesses,\" IEEE Design & Test of Computers,\nvol. 21, no. 1, pp. 56-63, Jan-Feb 2004.\n[11] S. P. Mohanty and E. Kougianos. \" Modeling and Reduction of Gate\nLeakage during Behavioral Synthesis of Nano CMOS Circuits.\" In\nProceedings of the 19th IEEE International Conference on VLSI Design\n(VLSID), 2006.\n[12] Hyunjin Lee, Jongho Lee and Hyungcheol Shin, \"DC and AC\nCharacteristics of Sub-50-nm MOSFETs with Source/Drain-to-Gate\nNon-overlapped Structure.\" IEEE Transactions on Nanotechnology, vol.\n1, No. 4, pp. 219-225, Dec 2002.\n[13] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and\nM. Bohr, \"Scaling challenges and device design requirements for high\nperformance sub-50 nm gate length planar CMOS transistors,\" in Tech.\nDig. VLSI Sym., 2000, pp. 174-175.\n[14] K. F. Schuegraf and C. Hu, \"Hole injection SiO2 breakdown model for\nvery low voltage lifetime extrapolation,\" IEEE Transactions on Electron\nDevices, Vol. 41, No. 5,pp 761-767, May 1994.\n[15] W. -C. Lee and C. Hu, \" Modeling CMOS tunneling currents through\nultrathin gate oxide due to conduction- and valence-band electron and\nhole tunneling,\" IEEE Transactions on Electron Devices, Vol. 48, No. 7,\npp 1366-1373, July 2001.\n[16] Fabien Pregaldiny, Christophe Lallement and Daniel Mathiot,\n\"Accounting for quantum mechanical effects from accumulation to\ninversion, in a fully analytical surface potential-based MOSFET model,\"\nSolid-State Electronics, Vol.48, No. 5, pp.781-787, 2004.\n[17] Taur, Y., and Ning, T.H.: ÔÇÿFundamentals of modern VLSI devices-\n(Cambridge University Press, New York, 1998).\n[18] Steve Shao-Shiun Chung and Tung-Chi Li, \"An analytical thresholdvoltage\nmodel of trench-isolated MOS devices with non-uniformly\ndoped substrates\" IEEE Transactions On Electron Devices, Vol. 39, No.\n3, pp 614-622,1992.\n[19] ISE TCAD: Synopsys Santaurus Device simulator."]}

The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters, namely, the doping level in the channel, the minimum slit width, and the effective radius of the slit. This work could serve as a guideline for technology optimization, design and scaling of JL VeSFETs.

In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along the channel, while assuming a parabolic potential across the silicon thickness, which in turn leads to some explicit relationships of the subthreshold current, subthreshold slope (SS) and drain induced barrier lowering (DIBL). This approach has been assessed with Technology Computer Aided Design (TCAD) simulations, confirming that this represents an interesting solution for further implementation in generic JL DG MOSFETs compact models.