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This letter demonstrates an on-silicon integrated thin film coupled inductor using a novel cascade matrix concept to suit multiphase integrated voltage regulator (IVR) applications. The novel cascade matrix coupled (CMC) stripline inductor facilitates all-phase-coupled configuration to reduce the phase ripple current in IVRs. It also shows excellent scalability and neat floor planning. Moreover, the proposed CMC inductor uses double layer metal scheme for windings and interconnects, which significantly reduces the ac winding resistance. A four-phase CMC inductor has been successfully fabricated on-silicon substrate and characterized, which uses conventional thin film magnetic core deposition process to achieve in-plane magnetic uniaxial anisotropy. The device occupies 3.2 × 1.7 mm2 floor area and provides 19.5 nH phase inductance with 120 mΩ dc resistance. The saturation current for each phase is up to 0.4 A when the phase inductance drops by approximately 20%. The coupling coefficient between any two phases of the proposed CMC inductor is 0.27, much higher and more controllable than that of toroid core-based coupled inductors.

This paper presents the development of an AA battery size electromagnetic vibration energy harvester with an aim to maximize the output power density. A tube shape and stacked opposing permanent magnets with magnetic spring were used to suit the shape constraint as well as to achieve high flux linkages. An initial prototype of electromagnetic vibration harvester with AA battery size was built and tested on a controllable shaker to obtain its output voltage and power level at different frequencies for fixed accelerations. A single magnet was fixed at the bottom of the harvester to provide levitation force in this development in order to lower the resonant frequency. A special time-domain based analytical model was also developed using both Finite Element Analysis and Simulink simulation. The time-domain analytical model is easier to implement than other frequency domain based analytical models which generally applied in literatures for modelling of the electromagnetic vibration energy harvesters. The analytical model was verified by the measured results obtained from the initial prototype. The validated analytical model was successfully applied to optimize the harvester. Two more generator prototypes were further built and tested after the optimization study. The optimized harvester using three stacked opposing permanent magnets could achieve a normalized power density of 12,655 μWcm−3 g−2 at 9.9 Hz frequency with 0.22 g acceleration, which is significantly higher than other reported electromagnetic vibration energy harvesters.

In this work a stacked winding thin film magnetic core microinductor is proposed to improve the ratio of inductance to dc resistance (DCR). This article also describes an improved ac winding loss model accounting for the asymmetric 2-D magnetic fields present within the device. Two six-turn single layer and stacked winding devices are fabricated, and small signal measurements are presented with dc inductance of 150 nH and DCR of $0.35~\Omega $ for the stacked winding inductor, and with DCR of $0.47~\Omega $ for the single winding inductor. In this case, the total DCR of stacked winding inductor is reduced by approximately 25% compared with the corresponding single layer structure with an equivalent inductance and device area.

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A micro-inductor has been fabricated on silicon substrate using a Micro-Electromechanical Systems (MEMS) process. The micro-inductor has a single layer copper winding sandwiched between two layers of electroplated NiFe core. It has a footprint area of 2.9 mm2, an inductance of 204 nH at 21.7 MHz, a DC resistance of 470 m Ω , and a peak quality factor of 9.23 at 9.2 MHz. The micro-inductor has been applied in a buck converter and achieved a maximum converter efficiency of 81.74% at 20 MHz. The performance of the micro-inductor has also been compared with an air-core inductor embedded in PCB. The air core inductor has a similar inductance of 220 nH, but with a large footprint area of 32 mm2. The maximum buck converter efficiency is 85.47% when the air core inductor is applied.

Coupled inductors offer significant advantages over their uncoupled counterparts; however, with these advantages come a number of additional design caveats. The factors affecting the design and optimization of coupled stripline microinductors for PwrSoC applications are outlined, which include device area, the number of coupled phases, duty cycle, paralleling of coupled inductors, switching frequency, as well as thermal and saturation constraints. Results of this analysis are presented and discussed along with guidelines for the design of coupled stripline microinductors, which show that paralleling coupled inductors is the best route toward higher output current. Analytical models predict a peak inductor efficiency of 86.8% and 86.3% for fabricated 3 and 5-phase coupled stripline microinductors with an Ni45Fe55 core, respectively. Models are verified by measurements on prototype 3 and 5-phase converters with parallel coupled stripline microinductors over a range of operating conditions.

In this paper, models that account for the duty cycle and phase shift angle of the applied phase voltages in coupled stripline microinductors are presented and are shown to have a significant impact on harmonic current amplitudes and therefore microinductor efficiency. The impact of a high coupling factor between two windings surrounded by a single core is also investigated. The models are validated using finite-element analysis and measurements. A three-phase-coupled microinductor has been fabricated with a Ni45Fe55 core and analyzed for a number of operating conditions. A prototype 1.6 W, three-phase converter utilizing this inductor has also been measured and is discussed in detail. The coupled microinductor is predicted to have a peak efficiency of 86.6% at 20 MHz in the prototype circuit.

In circuits where there is an inherent phase shift angle between coupled winding currents such as in coupled inductors, it is important to accurately calculate the ac winding loss at the correct phase shift and frequency. Phase shift between winding currents can cause the ac winding loss to vary significantly due to changes in the magnetic field distribution. This paper presents an analysis of winding loss for the general case of coupled windings with arbitrary phase-shifted currents and its effect in a number of practical devices. A detailed approach to analytically calculate ac winding loss in microfabricated-coupled stripline inductors is presented along with a derivation of the resistance matrix for the device. The analysis and methodology are then validated using finite element analysis and experimental results.

Traditionally, Dow ell's one-dimensional method is used to calculate the AC winding loss factor for transformers with reasonable accuracy in most cases. However, for thin film transformers there can be significant two-dimensional fields which, if ignored will lead to erroneous results. The problem is exacerbated for transformers used in Flyback DC-DC converters which are exposed to arbitrary current waveforms. In this paper we derive the resistance matrix for a closed core transformer accounting for the two-dimensional fields present. The derived resistance matrix can then be used to analytically calculate AC winding loss for arbitrary current waveforms such as those found in Flyback converters.

With the advent of PwrSoC/PwrSiP systems comes a wide range of process variables which the designer is required to optimize. However, as the number of parameters increases, so too does the complexity of the design. If active and passive components are not optimized in unison the advantages these highly integrated systems bring are negated. Considering this, the need for an intuitive design tool for the practicing engineer to quickly analyze a range of potential system configurations and find the Pareto optimal design with ease is clear. In this paper we present a new Electronic Design Automation (EDA) package, the Ferrochip Design Studio for the co-optimization of DC-DC converter systems, primarily for PwrSoC and PwrSiP systems using thin film integrated magnetics. We discuss its constituent parts as well as presenting the design flow used by the tool. Finally small signal measurement results are presented and compared to the analytical results generated by the design studio.

Inductor-on-silicon research to date has focused on optimizing technologies for maximum power density and efficiency, with most design procedures based on computationally intensive methods. In this paper, a simple and intuitive method for designing microinductors based on a given dc–dc converter specification, which includes accurate models for all loss components, is presented. A detailed examination of variations in designs to realise the same circuit performance is presented. Finally, finite element analysis simulations demonstrating the accuracy of the models are given, along with measured results.

The purpose of this paper is to show that distributing microinductors in parallel can reduce light-load losses, while also maintaining the same overall footprint area and the same effective inductance as a single microinductor. The performance of parallel microinductors is compared in a number of configurations to demonstrate which configuration provides the best overall performance in terms of circuit size, conversion efficiency, and power handling. Light-load saving techniques are implemented demonstrating the potential of parallel inductors to improve efficiency at light-load. Measured and modeled results of efficiency versus load are presented for the prototype DC-DC converters explored, and a peak efficiency of 74% is predicted for a 1.8 W, 20-MHz DC-DC converter including microinductors.

The application of coupled vs. non-coupled inductors in a phase-interleaved PV boost module-integrated-(MIC) converter is investigated in terms of inductor size, output voltage ripple and circuit efficiency. Reduced circuit size is the main motivation in this case whereby inductors currently dominate MIC size. Interleaved inductors provide one step towards size reduction by enabling current ripple cancellation at the converter input and output, so that the size of capacitors is significantly reduced. Further reduction in inductor size is demonstrated through the application of coupled inductors, in which two-phase inductors share the same core, to provide the same effective inductance as two larger non-coupled phase inductors.

Currently there is a great interest in inductors-on-silicon for power-supply-on-chip applications (PwrSoC), with an ultimate goal of integrating passive and active components on a single silicon die to reduce power supply size. While power levels of individual circuits are low, there is an ever-increasing trend towards ubiquitous computing; with the result that power consumption of mobile computing accumulates to a significant load demand from the grid. Inductor-on-silicon research to date has focused on optimising technologies for maximum power density and efficiency, without considering particular inductor specifications. In this paper a method for designing inductors-on-silicon based on a given DC-DC converter specification is presented.

Recently a great deal of work has been done to improve the efficiency of DC-DC converters at light-load. This has been driven by the desire to increase battery life in portable devices and to reduce standby power consumption in mains powered devices. In general, power supplies are moving towards higher switching frequencies to reduce passive component size, resulting in higher switching and gate drive power loss. Several methods to reduce power loss at light-load including Pulse Frequency Modulation and Diode Emulation are investigated in this paper. These methods however result in higher inductor current ripple as the inductor is designed for operation when output current is at its maximum. Distributing inductors in parallel is shown to provide a means for increasing the effective inductance at light-load through reducing current ripple.