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1. Sub-15 ps Charge-buffered Active-pull-down ECl/NTL Circuits

Author

Ching-Te Chuang Ching-Te Chuang, J.D. Warnock, and K. Chin

Subjects
Materials science, business.industry, Bipolar process, Electronic engineering, Optoelectronics, Charge (physics), business, Electronic circuit
Abstract

ECLINTL circuits with charge-buffered active-pull-down configuration are described. Implemented in a 0.8 pm double-poly trench-isolated self-aligned bipolar process, unloaded gate delays of 14.9-ps/2.2-mW and 12.8-psll .O-mW have been achieved for the charge-buffered active-pull-down ECL and NTL circuit, respectively.

Published
2005

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