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Due to the gapless between any two successive subbands with the same spin, the spin polarization in uniform MoS2 zigzag nanoribbon (MoS2-ZR) is weak. Here, through configuring Z-shaped structure, we realize 100% spin polarization in MoS2-ZR with only exchange field. The filtered spin electrons transmit along a specified edge of the device. This phenomenon is the result of the combined effect of the localized edge states and structure induced inversion of the Mo-edge and S-edge. In our calculation the fully spin polarization appears in several energy regions, so this Z-shaped MoS2-ZRs can be used in making spintronic devices.

Trust and distrust are common in the opinion interactions among agents in social networks, and they are described by the edges with positive and negative weights in the signed digraph, respectively. It has been shown in social psychology that although the opinions of most agents (followers) tend to prevail, sometimes one agent (leader) with a firm stand and strong influence can impact or even overthrow the preferences of followers. This paper aims to analyze how the leader influences the formation of followers' opinions in signed social networks. In addition, this paper considers an asynchronous evolution mechanism of trust/distrust level based on opinion difference, in which the trust/distrust level between neighboring agents is portrayed as a nonlinear weight function of their opinion difference, and each agent interacts with the neighbors to update the trust/distrust level and opinion at the times determined by its own will. Based on the related properties of sub-stochastic and super-stochastic matrices, the inequality conditions about positive and negative weights to achieve opinion consensus and polarization are established. Some numerical simulations based on two well-known networks called the ``12 Angry Men" network and the Karate Club network are provided to verify the correctness of the theoretical results., Comment: 12 pages, 15 figures

Fully parallel architecture at disparity-level for efficient semi-global matching (SGM) with refined rank method is presented. The improved SGM algorithm is implemented with the non-parametric unified rank model which is the combination of Rank filter/AD and Rank SAD. Rank SAD is a novel definition by introducing the constraints of local image structure into the rank method. As a result, the unified rank model with Rank SAD can make up for the defects of Rank filter/AD. Experimental results show both excellent subjective quality and objective performance of the refined SGM algorithm. The fully parallel construction for hardware implementation of SGM is architected with reasonable strategies at disparity-level. The parallelism of the data-stream allows proper throughput for specific applications with acceptable maximum frequency. The results of RTL emulation and synthesis ensure that the proposed parallel architecture is suitable for VLSI implementation., Comment: stereo matching; SGM; Rank SAD; fully parallel architecture

For 110W high power LED Street lamp, TEA1750, the third generation of green Switched Mode Power Supply (SMPS)controller ICs of Philips, is used to design a high-power LED driver circuit. The circuit has 90VAC ∼ 280VAC input and about 80V/1.37A output drive capability. At the same time, there are advantages of power factor correction (PFC), quasi-resonant and valley detection in it. It also have input low-voltage protection, over-voltage protection, over-temperature and over-current protection. Under normal working conditions, efficiency is greater than 85%; power factor is above 94%.

The principle of hybrid translinear (HTL) loop was presented, which made the principle of translinear (TL) loop be more complete. By proposing a method of decomposing an MOS transistor operated in triode region into two MOS transistors operated in saturation region, the principle of TL loop was simplified and the graphical equivalent topology was extended. In addition, the topological method to identify TL loops involved in translinear cell was successfully extended to all types of TL loops especially to HTL loop.

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer (TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.

A switched capacitor bandgap voltage reference with correlated double sampling structure embedded in a temperature sensor is implemented in a standard 0.35 μm CMOS process. Due to the smaller change of the op-amp's output voltage, this topology is very suitable for low power applications. In addition, errors caused by the finite op-amp gain, input offset voltage, and 1/f noise are eliminated with the correlated double sampling technique. Additionally, two-level process calibration techniques are designed to minimize the process spread. Finally, a method of getting a full period valid reference voltage output is discussed and experimental results are provided to verify the effectiveness of the proposed structure.