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This brief presents a phase-difference modulation signaling enhanced by decision feedback equalization for multi-drop memory interfaces. The phase-difference modulation signaling enables efficient data communication via a multi-drop channel, but only if the stub lengths are specially engineered. In this brief, the phase-difference modulation signaling is combined with decision feedback equalization to extend the applicable channel range. A test chip with a phase-difference-modulation transmitter and a decision feedback equalization receiver was fabricated in 65-nm CMOS technology. With a 2-tap decision feedback equalization, the test chip achieved the data rate of 7.8 Gb/s/pin via the both multi-drop channels with a long 10-cm stub and a short 2-cm stub, whereas the previous work without decision feedback equalization does not work with the 2-cm stub channel at 7.8Gb/s/pin.

This brief presents a channel-included filtering feed-forward equalizer (FFE) scheme suitable for data transmission through a heavily-dispersive lossy channel. The proposed scheme adjusts the tap weights so that the impulse response seen at the receiver has only a 2-unit interval (UI)-long impulse response with other parts negligible. The confinement of each bit response to a 2-UI period effectively achieves a lossless duobinary-like eye opening and enables data recovery with only a 1-tap decision-feedback equalizer (DFE). The proposed transceiver, implemented in 28-nm LP CMOS technology, achieved data recovery of 18 Gb/s up to 32-dB loss with only 3-tap FFE at the transmitter and 1-tap DFE at the receiver.

A delta-sigma modulator (DSM) is proposed for the direct connection to micro-electro-mechanical systems (MEMS) microphone. To reduce power, both the DAC reference voltage (VREF) and the DSM supply voltage (VDD) are reduced to 700 mV by limiting the maximum linear acoustic input range to 110 dB SPL (sound pressure level). For the low VDD operation, the switched capacitor (SC) integrators of DSM employ CMOS inverters as amplifiers. A unity-gain buffer compensates the pole error of the SC integrator; it reduces chip area by replacing the auto-zero capacitor of conventional inverter-based SC integrator. Compared to the conventional integrator, the integrator of this brief reduces the pole error from 0.3% to 0.06%, reduces the chip area and the power by 32.4% and 24.8%, respectively. The 3rd order DSM in a 65 nm CMOS process was measured to have Walden-figure of merit (FoMw) 89.3fJ/step, dynamic range (DR) 90.1 dB, signal-to-noise ratio (SNR) 87.2 dB, signal-to-noise and distortion ratio (SNDR) 86.4 dB, and power 122 uW at 10 MHz clock frequency (Fs).

This paper presents a phase-difference-modulation transceiver with simple clock recovery for highly-reflective interconnects. By greatly suppressing reflective intersymbol interferences with two new enabling mechanisms, phase–difference modulation enables high-speed data communication through highly-reflective multi-drop channels without utilizing decision feedback equalization. A systematic analytical approach is presented, and provides guidelines on how to determine channel and signaling parameters to exploit the two enabling mechanisms based on a newly derived formula of a single bit response of a channel. In addition, we propose a phase-difference amplifier that relieves the timing constraint of the bit decision at the receiver. By deserializing the received signals using the clock embedded in the received signals, the phase-difference amplifier can greatly reduce the design complexity of the clock recovery circuit. The proposed transceiver was fabricated in 65-nm CMOS technology. In single-ended mode, the transceiver achieved a maximum speed of 7.8 Gb/s/pin at energy cost of only 1.96 pJ/b while overcoming 10 in-band notches without decision feedback equalization. Also, the phase-difference amplifier enables clock recovery at power and area costs of only 0.12 pJ/b and 550 $\mu \text{m}^{2}$ , respectively, in single-ended 6-Gb/s/pin operation.

For the first time, we prove that 7.8-Gb/s single-ended signaling through a highly reflective channel is feasible at low energy cost by an energy-efficient many-tap decision feedback equalization (DFE) receiver (RX). The reported data rate of 7.8 Gb/s is the fastest data rate that has been achieved through a single-ended highly reflective channel that has more than five taps of postcursor reflective intersymbol interference. Compared with the prior arts, the target multidrop has the most in-band notches: ten notches. To compensate for large reflection by many notches, the RX exploits the DFE with the largest tap count of 20 that has been never used in single-ended signaling before. Low-power circuit techniques such as a current-integrating summer and double-tail sense amplifiers were adequately adopted and engineered to reduce large power dissipation by many taps. The RX was fabricated in a 65-nm CMOS technology and occupies only 0.014 mm2. The energy efficiency was measured to be only 2.9 pJ/b at 7.8 Gb/s with 0.9-V supply, proving that fast single-ended signaling through a highly reflective channel is feasible at low energy cost by many-tap DFE if low-power circuit techniques are adequately applied. The horizontal and vertical eye sizes were measured to be 0.12 UI and 34 mV, respectively, at a bit error rate of

This article presents a methodology to design a circuit to compensate for process skew by exploiting an inherent dimension-dependent effect of process skew on change in the threshold voltage. We design a voltage reference circuit with a hybrid architecture of bandgap reference (BGR) and CMOS reference, which generates a nominal voltage level of (bandgap - threshold). By compensating the process skew of the threshold term with the proposed dimension-induced effect as well as the temperature dependence, the circuit achieves the simultaneous benefits of BGR and CMOS references. For verification, the circuit was fabricated in three wafers of a 0.18- $\mu \text{m}$ CMOS including extreme slow and fast corners. With an active area of 0.0045 mm2, it consumes 192 pW at room temperature. Measurement from 45 chips (15 chips per wafer) shows untrimmed process/voltage/temperature variations of 0.53%, 0.020%/V, and 33 ppm/°C, respectively.

Internet-of-things applications that use machine-learning algorithms have increased the demand for application-specific energy-efficient hardware that can perform both learning and inference tasks to adapt to endpoint users or environmental changes. This paper presents a multilayer-learning neuromorphic system with analog-based multiplier-accumulator (MAC), which can learn training data by stochastic gradient descent algorithm. As a component of the proposed system, a current-mode MAC processor, fabricated in 28-nm CMOS technology, performs both forward and backward processing in a crossbar structure of 500 × 500 6-b transposable SRAM arrays. The proposed system is verified in a two-layer neural network by using two prototype chips and an FPGA. Without any calibration circuit for the analog-based MAC, the proposed system compensates for non-idealities from analog operations by learning training data with the analog-based MAC. With 1-b (+1, 0, -1) batch update of 6-b synaptic weights, the proposed system achieves a recognition rate of 96.6% with a peak energy efficiency of 2.99 TOPS/W (1 OP = one unsigned 8-b × signed 6-b MAC operation) in the classification of the MNIST dataset.

This paper presents a low power and low noise quadrature RC oscillator based on a frequency locked loop. Voltage swing control of each of the two sub-oscillators reduces the effect of 1/f noise on the accumulated jitter. In addition, the use of quadrature phases greatly relieves timing constraints of sampling operations and helps the reduction of power consumption. With a discrete-time modeling of the quadrature oscillator, noise analysis is also provided for quantitative estimation of the circuit-driven effects on the phase noise. The proposed oscillator is fabricated using 180-nm CMOS process in an active area of 0.058mm2. The measurement shows a period jitter of 0.047% and a standard deviation of 0.94% in untrimmed frequency (444.9kHz) in a wafer. The oscillator achieves a figure-of-merit of 155 dBc/Hz at 100 Hz offset frequency.

In this paper, we propose a code inversion encoding technique to improve the read margin of a cross-point phase change memory (PCM). The proposed technique reduces the maximum number of low resistance state cells which significantly reduce read margin by increasing sneak current. Therefore, the proposed scheme can significantly improve the read margin of the cross-point PCM. To verify the improvement of read margin by the proposed technique, we simulated and compared read margins of various arrays with and without the proposed technique. According to the simulation, our technique improves the read margin by 102% or equivalently allows to increase the array size by 91.6% without decreasing for the read margin. The results show that the proposed technique greatly improves the read margin.

In this paper, we analyze the impact of line mismatch on two-wire deembedding methods in early characterization of emerging interconnects. According to our analysis, mismatch of wires significantly reduces the accuracy of deembedding methods using two test wire structures and causes unexpectedly large error. Therefore, characterizing emerging interconnects with the deembedding methods is not reliable in an early development period when the process variation is large. To help engineers to decide whether the deembedding methods are applicable or not, we theoretically and empirically analyze how line mismatch affects the deembedding accuracy, and derive a condition under which the deembedding methods are reliable.

We present the first FFE SST TX layout generator enhanced by various software techniques including a GUI-based template engine. Seven different DRC/LVS-clean TXs were generated in multiple technologies (40nm/65nm/90nm CMOS) for the first time, and achieved adequate maximum data rates: 36Gb/s with 40nm in post-layout simulation; 14Gb/s with 65nm in measurement. Total generation time was less than 5 days, including iterative parameter tuning by a human designer and computation (30 minutes for TX core, 8 hours for power network). Fast post-layout analysis of TX’s performance-power trade-off was enabled by the presented generator for the first time.

We propose a new simple and low-cost alignment method utilizing electric contact for die stacking on an interposer or a printed circuit board. Without any expensive aligning/bonding equipment assisted by microscopy, we successfully stacked and bonded two silicon dies on a printed circuit board achieving alignment accuracy of $20~\mu \text{m}$ by utilizing only cheap equipment: manual micropositioners, a stage, a stand, a heat gun, a hot plate, and a power supply. In the proposed method, conductive alignment marks are fabricated on the bonding surfaces, and the electric contact between them are used to characterize misalignment. Therefore, the proposed method does not require any expensive complex microscopy equipment for alignment. In addition, alignment can be quickly and simply examined in situ by detecting electrical conduction during bonding. In experiment, alignment accuracy better than $20~\mu \text{m}$ and 100% bonding yield was measured in testing of 1800 bonds connecting two silicon interposer dies which were stacked on a printed circuit board by the proposed method.

A parallel branching synchronous dynamic random access memory (SDRAM) channel with write-direction impedance matching (parallel branching with write-direction impedance matching (PBIM)) is proposed for an 8-drop 6.4-Gb/s SDRAM interface. The 8-drop PBIM channel consists of two parallel branches; each branch consists of a series connection of two dual in-line memory modules for a 4-drop configuration and the data (data pin) channel uses two kinds of transmission lines with characteristic impedances of 50 and $25~\Omega $ and a resistor on the motherboard. Measurements on the test setup show that the proposed 8-drop channel works at the DDR5 target data rate of 6.4 Gb/s in both write and read directions by using the same motherboard area as that of the stub series terminated logic channel and a bit-error-rate tester for transmitter and receiver.

In this paper, we propose a search algorithm to find the worst operation scenario of a cross-point array of a phase-change random access memory to enable a precise read margin evaluation. The search algorithm utilizes a particle swarm optimization method to find the worst scenario quickly and efficiently. In an experiment, the proposed algorithm improves the search speed by $39.3\times $ compared with the previous algorithm. With the improved search speed, the proposed algorithm could find the worst operation scenarios of large arrays whose worst operation scenarios had been only guessed before. In the experiment with a large array, the proposed algorithm proved that the worst high-resistance state read current can be $36\times $ larger than the previous best guess. In the reliability test, the evaluation error of the worst read current found by the proposed algorithm is less than 0.2% with 99% probability. These results show that the proposed search algorithm can improve the precision and efficiency of the read margin evaluation in designing a cross-point phase-change memory array.

This paper presents detailed analyses on leakage-based bandgap reference (BGR) circuit for ultralow-power applications. Design considerations for power supply rejection ratio and noise characteristics are provided with pole/zero analysis. Startup settling issue is also discussed with measurements. For verification, a test BGR circuit is implemented in a 0.18- $\mu \text{m}$ CMOS technology. The standard deviation of proportional-to-absolute-temperature (PTAT) voltages measured from 20 chips is 1.15% at 30 °C. The BGR also uses two PTAT voltages to reduce the resistance for complementary-to-absolute-temperature generation, hence alleviating the tradeoff limitation between power consumption and area cost. With an active area of 0.056 mm2, the BGR consumes 19 nW at room temperature. Measurements from 20 chips show a standard deviation of 0.54% at 30 °C without any trimming, a temperature dependence of 143 ppm/°C and a line regulation of 2.4%/V.

This brief presents an intuitive, simple, and widely applicable approximate closed-form transfer function model for multiconductor transmission lines (MTLs). Rigorous closed-form transfer functions are derived from the telegrapher’s equation and approximated for a wide range of MTLs that satisfy validity conditions. Theoretical error bounds are also proposed and tightly estimate the approximation errors. The approximate formulas are simple yet accurate, and can be intuitively interpreted by a simple voltage-controlled voltage source circuit model. In demonstration, we show that the proposed model allows designers intuitively to understand and accurately to analyze complex MTLs.

This paper proposes the first feed-forward equalizing transmitter (Tx) which adaptively relaxes impedance matching. Using an on-chip time-domain reflectometer monitor, the Tx accurately detects the impedances of the channel and the receiver (Rx), and then automatically configures its termination impedance to maximize the received signal by optimally relaxing the constraint of impedance matching at the cost of a negligible penalty in signal integrity. The Tx is universally compatible with arbitrary impedances of channels and Rxs, and achieves better performance and power efficiency than the conventional Tx with impedance matching. The proposed Tx was fabricated in 65-nm CMOS technology. The Tx successfully adapted to any combination of a channel impedance of 35–75 $\Omega $ and a receiver impedance of 30–200 $\Omega $ . When the impedance matching of the Tx is adaptively and optimally relaxed, the eye size and the power efficiency are improved by up to 3.8 times and 2 times, respectively, compared with the conventional Tx. These results verify that the proposed Tx can adapt to various impedances of the channel and the receiver while achieving better performance and power efficiency than the conventional Tx with impedance matching.

This paper presents an asynchronous-clocking successive approximation register (SAR) analog-to-digital converter (ADC) suitable for ultralow-power fine-precision sensor applications whose signal bandwidth is in the kilohertz range. The performance-limiting issues of comparator noise and capacitor mismatch in SAR ADC are resolved by a residue integration scheme combined with a dynamic element matching (DEM), achieving a high resolution without imposing extra burden on the design of residue amplifier and comparator. The prototype 16-bit 2 kS/s SAR ADC is fabricated using 180-nm CMOS process in an area of 0.68 mm2. Measurements show 84.6-dB signal to noise and distortion ratio and 98.2-dB spurious-free dynamic range at the Nyquist input frequency. The ADC dissipates 7.93 $\mu \text{W}$ from supply voltage of 1.8 V and achieves a Schreier figure of merit of 165.6 dB.

A time-based (TB) receiver (RX) with a 2-tap TB decision feedback equalizer (DFE) is proposed for mobile DRAM interface. The TB RX consists of a voltage-to-time converter (VTC), a TB DFE, and a time comparator. The VTC converts the RX input voltage to a time difference between two VTC outputs by using the difference in clock-to-Q delays between two latches with different input offset voltages. The TB DFE inserts an additional delay to one of the two VTC outputs and bypasses the other VTC output to increase the time opening. The time comparator makes a decision with the first arriving edge of the two outputs of the TB DFE. While the feedback loop delay must be less than 1 UI for proper operation in the conventional voltage-based DFE, the TB DFE allows the feedback loop delay up to 1.43 UI in this paper. A transmitter (TX) transmits a single-ended signal of 200-mV swing by using an n-over-n voltage-mode driver. The transceiver in a 65-nm CMOS process achieves a 12.5 Gb/s with a 0.8-V supply through a 15-inch FR-4 channel of 14-dB loss. The TX and RX chip consume 4.3 and 3.4 mA, respectively. The energy efficiency is 0.49 pJ/b.

This paper disproves the worst read scenario of a ReRAM crossbar array. If the previously believed worst read scenario is not the worst one, the read margin evaluated based on the scenario can be incorrect. We explored for read scenario worse than the previously believed worst scenario by wisely sampling scenarios and iteratively searching for the worse one. In experiment, our algorithm successfully found the scenario worse than the previously believed one, disproving the previously believed worst read scenario. Our results show that the sensing window estimated by the incorrect previously believed worst scenario is 14 times as large as the estimation by the worst scenario found by our algorithm.

This brief presents an approximate transfer function model of two heterogeneous transmission lines connected in series. The proposed model is simple, intuitive, and can accurately describe the frequency response of various serially connected heterogeneous interconnects which satisfy a validity condition. The exact error of the proposed model is also provided. According to our analysis, the validity condition can be clearly interpreted by the propagation and the reflection waves. The accuracy of the proposed model is verified by comparing the calculated transfer function of LC-dominant off-chip and RC-dominant on-chip examples against SPICE simulation results. In these verifications, the maximum errors between calculation and simulation are, respectively, 2.58% and 3.32% for off-chip and on-chip examples. The computation time is also reduced about 29.76 and 289.07 times compared with a single-channel model and the SPICE ${w}$ -element model. With the proposed model, designers can easily understand the channel responses of diverse serially connected heterogeneous interconnects.

This paper presents a self-biased current-mode amplifier (CMAMP) suitable for a switched-capacitor circuit. The CMAMP uses a subthreshold-biased transimpedance stage as a current-sensing load, and minimizes static power dissipation by passing bias current only at the input stage. The first-order system behavior with single dominant pole gives stable phase margin without complicated frequency compensation. Self-biasing circuits automatically generate bias voltages to sustain performance over a wide range of supply voltage. The designed CMAMP is verified in a 10-bit pipeline analog-to-digital converter (ADC) fabricated in a 65-nm CMOS process. The ADC achieves a figure of merit of 14.3 fJ/c-s with a supply voltage of 0.6 V at 2.5 MS/s.

This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our model generator automatically produces SPICE models of ReRAM devices and selectors from the measured ${I}$ – ${V}$ data to reduce too much time consumption in manual model development for ReRAM devices and simulation of the target ReRAM circuits. To verify our method, SPICE models for diverse ReRAMs were automatically generated from measured data and simulated with various circuits. The results show that our model can accurately describe the original data and allows fast quantitative evaluation of ReRAM circuits. Because developing SPICE models of ReRAMs and simulating them with circuits have been the critical time-consuming procedure in ReRAM research, these results show that our method enables early ReRAM evaluation.

A phase-interpolator-based fractional counter (PIFC) is proposed to reduce power consumption by replacing TDC in a ring-oscillator-based digital fractional-N phase-locked loop. A predicted-phase-interpolation method is used to calculate the integer and fractional parts of the frequency-division-ratio and to find two interpolation clocks; the prediction method gives a significant power reduction in the proposed PIFC by enabling the use of low-frequency clocks for phase interpolation. The proposed PLL chip in a 65-nm CMOS occupies 0.173 mm2 and consumes 15.5 mW at 6 GHz and 1.2 V; the PIFC consumes less than 20% of the TDC power. The integrated rms jitter is 1.75 ps and a FoM value of −223.2 dB is achieved.

This paper presents a smart contact lens (SCL) controller IC with a high-precision current sensor interface and a dual-mode wireless telemetry, where a single power-oscillator-based circuit with an external loop antenna supports both LSK and RF data transmission. The implemented IC in $0.18 \mu m$ CMOS, achieving a dynamic conversion range of 89 dB while dissipating 143 nW, is verified in a glucose-sensing SCL system.

An all-synthesizable current-mode transmitter driver for a USB2.0 high-speed (480 Mb/s) interface was proposed to enhance the design portability. The proposed driver was implemented using tristate inverter cells. It uses the differential current-mode architecture, with variable output voltage swing, and includes a predriver. It was also successfully applied to the 480-Mb/s USB2.0 TX driver with the synthesized serializer and phase-locked loop.

This brief presents a fast-lock 2.4-GHz fractional-N phase-locked loop (PLL) for ultralow-power applications. To minimize the power consumed by all the other circuits except for the main oscillator, we propose a master-slave PLL structure in which a low-frequency master PLL is followed by a slave injection-locked oscillator operating at high frequency. A frequency-error compensation circuit is also implemented in the slave oscillator to eliminate possible drift in the free-running frequency. With a fractional-N coarse-lock unit in the master PLL and a fine frequency initialization unit in the slave oscillator, the PLL supports two fast-lock modes: 1) start-up locking from deep-power-down mode and 2) instantaneous relocking from standby mode. The implemented PLL in 65-nm complementary metal-oxide-semiconductor (CMOS) consumes 250 μW from a 0.8-V supply, demonstrating a power efficiency of 0.102 mW/GHz. The PLL performs the two fast-lock operations with lock times of less than 22 μs from deep power down and 1 μs from standby, respectively.

To enhance the signal-to-noise ratio of a mutual-capacitive touch-sensor, three methods are used to implement read-out integrated circuit (ROIC); an averaging method with three specific transmitter frequencies of ( $n+0.5$ ) times the frequency of a gate driving signal (GCLK) of LCD with an integer $n$ , a noise memory method that eliminates the dc and low frequency noise by subtracting the noise data from the measured data, and a compact delay compensation method. A digital dual-loop phase-locked-loop generates the three specific frequencies automatically from GCLK. The proposed ROIC applied to a $14\times 16$ touch-sensor panel on a 7.9-in LCD achieves the SNR of 52.9 dB with the frame rate of 367 Hz. The ROIC chip with a 0.35- $\mu \text{m}$ CMOS process takes an area of 5.64 mm $^{{\mathrm {2}}}$ and consumes power of 29.7 mW.

A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of $\sim 10$ dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s.

This paper proposes a new feed-forward equalizing (FFE) transmitter ( Tx ) for a massively parallel I/Os to reduce calibration circuits and to save power consumption. The proposed FFE Tx improves its robustness to a coefficient error and its power efficiency by utilizing a high-pass digital difference filter and a channel loss to attenuate the effects of the coefficient errors. To verify the proposed FFE architecture, we fabricated the conventional and the proposed FFEs in 65 nm CMOS technology and tested eye sensitivity and eye variation at 8 Gb/s on 25 dB, 13.2 dB, and 9.6 dB PCB traces. Compared to the conventional FFE Tx , the proposed FFE Tx improves the eye sensitivity and the eye variation by about 230% on a 25 dB lossy channel without calibration. In addition, this improvement increases as the channel loss increases. The proposed FFE Tx also improves the power efficiency by 230% at 25% utilization on a 25 dB lossy channel. These results imply that the proposed FFE Tx can reduce calibration circuits in a massively parallel I/Os and the power consumption.

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5- phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies 0.038 mm², consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

A voltage reference circuit is an essential block of a system to generate various internal voltages. Since it consumes static power in standby modes, it plays an important role in energy management of battery-limited applications. The bandgap reference (BGR) has been a widely used approach since it provides a well-defined large value ($\sim 1.15\text{V}$) with strong immunity to process, supply and temperature changes. Recently proposed BGR approaches achieved a great reduction of power consumption by taking only complementary-to-absolute-temperature (CTAT) quantity from a PN junction while they obtained proportional-to-absolute-temperature (PTAT) quantity from alternative CMOS circuits such as a CTAT divider [1]or leakage-based two diodes [2, 3]. However, these BGR schemes are formed with multiple branches fed from a supply voltage above 1.4V and require power consumption of order larger than 10nW. To further reduce power consumption, threshold-based reference approaches with CMOS-only circuits have been proposed [4, 5]. However, generation of a practical voltage level by up-scaling of a threshold-based reference also causes an amplification of the uncertainty by the same factor. I addition, though [4]has successfully achieved sub-nW power consumption, the threshold voltage eventually suffers from a large sensitivity to process variation because the threshold voltage is affected by process and design parameters. To reduce the effect of process variation, [5]proposed a PMOS-only circuit. However, it requires a different body biasing for a threshold difference that is needed to generate a non-zero reference.

This paper experimentally verifies a simple, intuitive, and accurate closed-form transfer function model for diverse high-speed interconnects for the first time. Recently, an approximate closed-form transfer function model, which is simple, intuitive, and accurate, as well as applicable to diverse high-speed interconnects, was proposed. However, because the model was only verified by SPICE simulation, the experimental verification is required to guarantee the reliability of the model in practical high-speed interconnects. To this end, an example interconnect was designed and fabricated, and its characteristic impedance and propagation constant were extracted. Then, the transfer function calculated from the extracted parameters by using the model was compared with measurement. The result shows that the model can describe the behavior of the fabricated example interconnect and thus is reliable in practical high-speed interconnects.

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit with an asynchronous baud-rate sampling to achieve an adaptive equalization as well as a data rate acquisition. The proposed scheme also enables the use of a successive approximation register (SAR) based approach in the frequency acquisition and results in a fast coarse lock process. The CDR guarantees a robust operation of a fine locking even in the presence of large input data jitter due to the adaptive equalization and a jitter-tolerable rotation frequency detector (RFD) that eliminates a dead-zone problem with a simple circuitry. The fabricated CDR in 65 nm CMOS shows a wide lock range of 0.65-to-10.5 Gb/s at a bit error rate (BER) of $10^{-12}$ . The CDR consumes 26 mW from a single supply voltage of 1 V at 10 Gb/s including the power consumption for equalizer. By an adaptive current bias control, the power consumption is also linearly scaled down with the data rate, exhibiting a slope of about 2 mW decrease per Gb/s.

This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of ${0}.{047}\;\text{mm}^{2}$ and achieves a stable in-band phase noise of lower than $- {100}\ \text{dBc}{/}\text{Hz}$ in a wide range of supply voltage from 1 to 1.4 V.

A feedback edge combiner is proposed for the duty-cycle corrector (DCC) of a delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge combiner generates the rising edge of a DCC output at the rising edge of an input clock. It generates the falling edge of the DCC output at the rising edge of a feedback clock that is a half-period-delayed signal of the DCC output. A dual-delay-line digitally controlled delay line (DCDL) is used for seamless boundary switching. The chip area of the DCDL is reduced by around 46% by employing the architecture of two short coarse delay lines followed by a fine phase mixer (FPM) and a long coarse delay line in series instead of the architecture of two long coarse delay lines followed by an FPM. The measurements on the chip fabricated in the 65-nm CMOS show the allowed input duty cycle in the range from 20% to 80%; root-mean-square and peak-to-peak jitters of 2.69 and 14.0 ps, respectively, at 2 GHz and 1.2 V; and the operating frequency range from 0.12 to 2.0 GHz at 1.2 V. The measured power consumption is 3.3 mW/GHz at 1.2 V. The chip area is 0.059 mm 2.

A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor α, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor α an attractive option for lower power applications.

H-field EMI measurements have been performed for the single-ended, the differential, and the pseudo-differential signaling on a 11” FR4 microstrip line. The pseudo-differential signaling reduces EMI by more than 10 ㏈ compared to the single-ended signaling if the delay mismatch is lower than 5% of a period for a 3 ㎓ clock signal. Empirical H-field equations for both differential and single-ended signaling showed fair agreements with measurements.