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Ultra low energy ion implantation is a promising technique for the wafer-scale fabrication of Silver nanoparticle planar arrays embedded in thermal silica on silicon substrate. The stability versus time of these nanoparticles is studied at ambient conditions on a time scale of months. The plasmonic signature of Ag NPs vanishes several months after implantation for as-implanted samples, while samples annealed at intermediate temperature under N(2) remain stable. XPS and HREM analysis evidence the presence of Silver oxide nanoparticles on aged samples and pure Silver nanoparticles on the annealed ones. This thermal treatment does not modify the size-distribution or position of the particles but is very efficient in stabilizing the metallic particles and to prevent any form of oxidation.

Non volatile flash memories based on nanoparticles (nps) are one of the identified routes to a further downscaling of future CMOS technology. New features such as Coulomb blockade and quantized charging effects can appear at room temperature only for a limited number of addressed nanometer sized nps [1]. It has been previously demonstrated that ultra low energy ion implantation (1keV) into an ultra thin SiO2 layer (7nm) through a stencil mask containing apertures (from 50nm to 2μm) [2], followed by annealing allows to produce 2D arrays of Si nps into localized areas of the gate oxide [3]. The I(t) and I(V) measurements of the nano-MOS capacitors reveal single electron transport at room temperature. At the same time, the C(V) electrical measurements reveal significant flat-band voltage shift as high as 4V denoting strong memory effect in these isolated areas. However, as a result of ion implantation damage into the oxide, the remaining structural defects (e.g. excess of silicon atoms, Si/SiO2 interface defects…) and their localization play a major part in the electrical characteristics of these devices. In this paper, we propose a complementary electrical study using AFM/Kelvin Probe (KFM) technique. The amount of charges stored in each nps with different sizes can be evaluated from the surface potential change with the electron injection into and extraction from the ncs. Moreover, the temporal decay of the surface potential has been systematically studied as a function of ncs characteristics (density, size, localization…) and the retention time extracted from the exponential decay was found much longer than 4000s in the implanted areas. These measurements clearly add to the understanding of memories based on these nanostructures.

Flash memories based on nanoparticles (NPs) offer an attractive alternative for performance enhancement and size downscaling of non-volatile memory cells. In these devices, Coulomb blockade and quantized charging effects can be exploited at room temperature for a limited number of addressed NPs [1]. A successful exploitation of these nanoscale effects requires not only knowledge of the NPs properties (size, nature, structure and location) but also a sound understanding of the charge trapping phenomena that govern the memory behaviour of the devices. In this study, fabrication of 2D arrays pockets of Si nanocrystals (NCs) is demonstrated by implanting 1keV Si ions into thin SiO2 layer (7nm) through a stencil mask with 50nm to 2μm apertures. Upon thermal annealing, Photoluminescence spectroscopy (PL) and Energy-Filtered Transmission Electron Microscopy (EFTEM) reveal characteristics of NCs in the implanted SiO2 pockets. Then, charging dynamics examined by I(V) and I(t) measurements on nano-MOS capacitors in the 80K-300K temperature range clearly show an increasing Coulomb gap with decreasing temperature. Moreover, below a critical temperature (T=150K), N-shapes which are voltage sweep ramp dependent, appear on the I(V) curves. Comparison of the CDG capacitance extracted from QDG (charges of Dots/Gate) calculations on different I(V) ramp measurements and the CDG capacitance evaluated from structural parameters (sizes, tunnel distances…) extracted from EFTEM and PL characterizations provide relevant information regarding the kind and localization of the charge trapping centers.

Photoluminescence (PL) spectroscopy has been demonstrated as a suitable technique to characterize Si nanocrystal-based non-volatile memory devices (Carrada et al. APL 2005). These are formed by a single plane of Si nanocrystals (NCs) buried in the gate oxide of a MOS device, at a tunneling distance from the channel. Such a 2D array was obtained by low-energy ion implantation followed by annealing. It was shown that the electrical properties are dramatically improved after annealing in oxidizing conditions. These necessary conditions for oxide healing also lead to a strong increase of the PL intensity as well as to a good agreement between the PL energies and the NCs sizes measured by electron microscopy (Bonafos et al., Solid State Electr. 2005). Recently, both these elaboration and characterization techniques were extended to the production and the study of new nano-scale electronic devices which exploit the Coulomb blockade effect and other quantized charging features at 300 K (Shalchian et al., APL 2005). The fabrication of such devices requires the fine control of a small number of NCs of about 3 nm in diameter, ideally down of the single particle. This can be achieved by 1 keV Si-implantation through stencil masks with window sizes ranging from 300*300 nm2 to 1*3 micron2. After mask removal and annealing, PL spectroscopic imaging under a confocal microscope is used to detect the NCs rich areas. The image of the PL intensity is found to mimic the mask geometry. Moreover, a blueshift of the PL energy is detected in the same image near the edges of the mask holes. This blueshift is probably due to the smaller sizes of Si-NCs near the mask edge. Energy filtered transmission electron microscopy is underway to assess and study this size distribution.

Non volatile flash memories based on nanoparticles are one of the possible routes to further downscaling of CMOS technology. The increase of scale integration should involve some new features for memory cells such as Coulomb blockade and quantized charging effects. These previously mentioned effects appear at room temperature, for nanometer sized nanoparticles (nps), if their number is reduced to a few or even a single particle. Fabrication of 2D arrays of Si nanoparticles have been previously demonstrated using, ultra low energy ion implantation (1keV) into an ultra thin SiO2 layer (7nm), followed by annealing. Nano-MOS capacitors were then elaborated using e-beam lithography, creating gates at the nanometer scale capable of addressing only a few nps and obtaining a single electron transfer sensitivity. However, this complex process has many disadvantages and suffers from non-reproducibility. In this work, we propose an alternative approach combining stencil lithography masks and low energy ion implantation (called “stencil mask ion implantation process”). The process leads to a localized synthesis of only few self-organised nps. In this process, the SiO2 thin layer is irradiated by a 1keV silicon ion beam through a stencil mask, which contains a periodic array of membrane apertures. The size of these apertures are in the 50nm to 2um range and shaped as, square, circle, cross, etc. This stencil mask locally modulates the dose of the implanted Si ions which produces nps in these Si rich regions upon annealing. For the smallest membrane apertures the number of fabricated nps could be reduce to one. After the removal of the stencil and after thermal annealing, the photoluminescence (PL) spectroscopic imaging under a confocal microscope is performed to detect the nps rich areas by using their quantum confinement linked red light emission. The image of the PL intensity is found to perfectly mimic the mask geometry. Moreover, a blueshift of the PL energy is detected near mask edge window which is probably due to the smaller sizes of Si-nps. Energy filtered transmission electron microscopy is underway and is used to determine the density and the size distribution of these nps. Using these few nps of localized 2D-layers samples, elaboration of more robust nano-MOS devices is underway, revealing the nps quantized charging features in a more reliable way. These two kinds of nano-MOS devices will be compared via the I-V and I-t electrical characterization.

We have synthesized Si Nps rich submicron area within a thin SiO2 layer using a new method called “stencil-masked ion implantation”. It consists in implanting silicon ions at ultra-low energy through windows (from 50nm to 2μm) opened in a stencil mask containing. After thermal annealing the implanted regions perfectly mimic the mask geometry. Energy-filtered transmission electron microscopy images and PL measurement reveal that smaller nanocrystals are formed near the edges of the implanted areas due to a dose edge effect.