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The lumped-charge (LC) technique is widely used to develop simple and physically based power device models for circuit simulators. The existing models, due to the linearization of the diffusion equations in the drift region, have some limitations that impact accuracy and numerical stability. In this work, the carriers’ transport equations, rather than linearized, are treated as differential equations, and an LC model that exactly solves the diffusion equations is presented. It improves the accuracy of the traditional models and provides a numerically stable expression of the currents while keeping the same simplicity. Furthermore, the continuity equations are rigorously discretized by means of the box integration method, widely used in finite element device simulators, which has been proven to be numerically stable and accurate. The new model is verified both on the static and transient characteristics of commercial insulated-gate bipolar transistors and power diodes.

In this paper the CMOS amplifier behaviour has been further investigated respect to the previous works in the literature. An exhaustive scenario for the EMI pollution has been considered: the injected interferences can indeed directly reach the amplifier pins or can be coupled from the PCB ground. This is a key point for evaluating also the susceptibility from the EMI coupled to the output pin, which is disclosed as a critical point. The investigated topologies are basically derived from the Miller and the Folded Cascode, which are well-known and widely used by the CMOS analog designers; all of them are re-designed in UMC 180 nm CMOS process in order to have a fair comparison.

A new unipolar differential logic (UDL) for the large-scale integration of amorphous In-Ga-Zn-O (aIGZO) digital circuits is proposed. Only single-threshold single-gate and aIGZO thin-film transistors are required. The proposed UDL logic gates are very insensitive to transistor parameter variations (i.e., threshold voltage, mobility, off-current, and subthreshold slope), which are inherently due to large-area low-temperature fabrication processes and operating conditions. To assess the UDL effectiveness, a wide range of parameter variations is considered: and, owing to the proposed architecture up to 1.5 $\times$ 107 UDL gates that can be integrated with a yield that is greater than 90%.

This paper depicts and investigates the effect of a possible EMI attack to the analog integrated circuits (ICs) commonly used in the automotive systems. In particular, all the possible paths from the EMI sources to the IC are considered. Measurements and simulations show that the integrated circuits are susceptible to the EMI injection from all the possible paths and that resulting EMI-induced offset can be considerable at frequencies ranging from tens of MHz up to GHz.

The Internet of Things (IoT) has found application in many components of implantable medical devices, wearable smart devices, monitoring systems, etc. The IoT devices are conventionally battery powered, even though, in several low power applications, they can also be powered using energy harvesting technology. Independently of the power sources (if batteries or environment), efficient and robust power converters must be designed to provide the small and distributed energy required by such IoT devices. This review paper will first provide an overview about the power consumption in IoT devices; second, it will discuss the most recent research and advance in the field of fully-integrated or embedded DC/DC converters, starting from high-performance integrated charge pumps or embedded inductive boost converters for specific harvesting sources (temperature, solar, and so on), to novel DC/DC converters for multiple energy sources.

Over the last decade, energy demand from the power grid has increased significantly due to the increasing number of users and the emergence of high-power industries. This has led to a significant increase in global emissions with conventional energy generation. Therefore, the penetration of renewable energy resources into the power grid has increased significantly. Photovoltaic systems have become the most popular resources as their protentional is enormous, thus, the worldwide installed PV capacity has increased to more than 635 gigawatts (GW), covering approximately 2% of the global electricity demand. Power electronics are an essential part of photovoltaic generation; the drive for efficient power electronic converters is gaining more and more momentum. Presently, multilevel inverters (MLI) have become more attractive to researchers compared to two-level inverters due to their abilities to provide lower electromagnetic interference, higher efficiency, and larger DC link voltages. This paper reviews multilevel inverters based on their classifications, development, and challenges with practical recommendations in utilizing them in renewable energy systems. Moreover, PV systems with various maximum power point tracking (MPPT) methods have been extensively considered in this paper as well. The importance and the development of a modified multilevel inverter are also highlighted in this review. In general, this paper focuses on utilizing multilevel inverters for PV systems to motivate and guide society to focus on inventing an efficient and economical multilevel inverter that has the combined capabilities of these converters reported in the literature.

In practical printed circuit board (PCB) designs, electromagnetic interference (EMI) is coupled from the ground plane, which is commonly shared among the analog, digital, and mixed-signal integrated circuits. This noisy ground plane couples interference capacitively to all the IC pins, including the output: this effect is exacerbated when the IC is connected to long wires and traces that are routed close to the conductive ground plane. This paper reports on the effect of interference, which is coupled capacitively from the PCB ground plane into all the IC pins of an opamp connected as a voltage buffer. Simulations illustrate the susceptibilities in custom operational amplifier designs, and are corroborated by measurements on several commercial devices. These measurements show that the EMI-induced offset can attain considerable values for the most critical EMI frequencies, which lie between 10 and 100 MHz. Moreover, these illustrate that there is a considerable susceptibility of operational amplifiers to electromagnetic interference coupled to their output pins.

A fully integrated DC/DC converter for low-voltage applications is presented. It is based on a modified Dickson charge pump which exhibits improved performances by using integrated small inductors. The proposed charge pump is superior in terms of power efficiency, maximum output voltage, rise time, and voltage output ripple. The overall circuit does not require any external components and can be fully integrated in a standard complementary metal–oxide semiconductor technology. The converter has been designed in STMicroelectronics 180 nm process.

One of the most challenging tasks for analog and digital designers is to maintain the circuit performances by developing novel circuit structures, robust, reliable, and capable of operating with low supply voltage [...]

This letter presents an on-chip common-mode cancelation circuit (CMCC), which increases the immunity to electromagnetic interference (EMI) of the input stage in a classic CMOS operational amplifier. Two test chips, containing a classic Miller amplifier and a Miller amplifier with CMCC, respectively, have been fabricated in the UMC 180 nm CMOS process. Measurements illustrate how the latter amplifier exhibits an increased immunity to EMI compared with the former.

An extremely accurate yet simple form of the charge-sheet model (CSM) is developed using the third-order Hermite interpolation polynomial to model the inversion charge in the channel. This new formulation of the drain current retains the same simplicity of the most advanced surface potential compact MOSFET models based on the symmetric linearisation method (SLM). However, unlike the SLM, it is developed without requiring the crude linearisation of the inversion charge, hence the asymmetry and the non-linearity in the channel are accurately accounted for. Nevertheless, the expression of the drain current can be worked out to be analytically equivalent to SLM. Its mathematic formulation is even easier with respect to SLM since it does not require the evaluation of the inversion charge at the surface potential midpoint, but at source and drain only, as the conventional CSM.

Measurements in commercial devices demonstrate a considerable susceptibility of the operational amplifiers to the electromagnetic interferences coupled to their output pin. This paper investigates some basic architectures starting from single stage amplifiers up to a whole operational amplifier. The result is a correlation between the different amplifier configurations, the output impedance and the susceptibility to the interferences. The simulations are perfomed by using the standard CMOS UMC 180nm technology and by running the netlist of the schematics extracted from the layout.

Two fully-integrated DC/DC converters for energy harvesting applications are presented. The startup-voltages of the converters are, respectively, 140 and 100 mV, the output voltage exceeds 1.2 V, with a power efficiency of about 20%. The architectures for boosting such extremely low voltages are based on an ultra-low-voltage oscillator cross connected to a capacitive converter. The overall circuits do not require any external components and can be fully integrated in a standard complementary metal oxide semiconductor low-voltage technology. The converters have been designed in United Microelectronics Corporation 180 nm process.

A novel multiple-time programmable (MTP) single-poly EEPROM cell based on a half-MOS device is presented. The proposed cell is fabricated in a standard complementary metal-oxide-semiconductor (CMOS) process without any additional mask or process step. It is based on a novel approach, which provides many advantages with respect to the state-of-the-art standard MTP cells, in terms of area, program/erase performance, and endurance. A test-chip is fabricated in a standard 0.13 μm CMOS process and extensive experimental results are provided.

In this paper, we present two charge pump architectures for nonvolatile memories with dynamic biasing of the gate and the body voltages. By controlling the gate and the body voltage of each pass-transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the following with a negligible voltage drop and large conductivity. The charge pumps were fabricated in the ST 130-nm digital standard CMOS technology. Compared to conventional charge pumps, larger output voltage and better power efficiency are achieved still retaining a simple two-phase clocking scheme. Measurements performed on four-stage and eight-stage charge pumps are provided.

This paper presents a successful approach to increase the electromagnetic interference (EMI) immunity of CMOS bandgap reference circuits. Layout techniques along with some changes in the reference schematics lead to a robust electromagnetic immunity, preserving good overall performances. Measurement results confirm the low susceptibility of the proposed circuits. They exhibit only a few millivolts shift, for interfering signals of 1 Vpp in the frequency range of 1 MHz to 4 GHz, compared to the classical topologies that may reach more than 1 V. The circuits were fabricated in a 0.8-mum standard CMOS technology

A single-poly electrically erasable programmable ROM (EEPROM) cell compatible with standard CMOS process is proposed. With respect to the classical embedded NOR cell, it can be programmed and erased by Fowler-Nordheim tunneling with single-bit granularity. The memory cell is based on a novel writing-inhibition scheme enabled by the combination of the body effect with multiple half-MOS devices. Experimental results on programming, erasing, inhibition, reading, and cycling endurance are provided using a 0.13 μm standard CMOS process.

This paper addresses a new approach to design a CMOS operational amplifier which provides a good tradeoff between high gain and strong immunity to electromagnetic interferences. The proposed amplifier is based on two main blocks: the first is a fully differential folded cascode with modified input pair and the second is a source cross coupled AB class buffer. Thanks to the folded cascode stage and to the symmetrical output buffer, the amplifier exhibits both intrinsic robustness to interferences and good amplifier performances. The circuit was fabricated in a 0.8-/spl mu/m n-well CMOS technology (AMS CYE process). Experimental results, in terms of electromagnetic interference (EMI) immunity, are presented and successfully compared with commercial amplifiers. Measurements carried out on the chip and the amplifier overall performances are provided along with the corresponding simulation results.

To the authors knowledge, this is the first time that a paper demonstrates the feasibility of a fully integrated step-up converter based on inductive elements. The prototype is fabricated in the ST M8 0.18-/spl mu/m process, uses a supply voltage of 1.8 V, and provides an output mean voltage of about 6 V at 10 k/spl Omega/ resistive load with a 60-MHz external clock frequency.

A fully-integrated DC/DC converter for energy harvesting applications is presented. The startup-voltage of the converter is about 140mV, the output voltage exceeds 1.5V, with a power efficiency at least 20%. The architecture for boosting such extremely low voltages is based on an ultra-low-voltage oscillator cross connected to two phase charge pump. The overall circuit does not require any external components and can be fully integrated in a standard CMOS low voltage technology. A test-chip has been designed in UMC 0.18µm process.

A DC/DC boost converter to power integrated circuits is presented. It can boost extremely low voltages, starting from about 150 mV. The converter is based on a new hybrid inductive and capacitive architecture and it is suitable for power harvesting applications. A test chip was designed and fabricated using a UMC 180 nm low threshold CMOS process. Measurements on the chip confirm the validity of the design.

In this paper a class AB CMOS operational amplifier is devised. It is based on a two stages strongly symmetrical topology, very attractive in order to minimize the effects of disturbances arising from a wide class of sources. The amplifier can be fabricated in standard CMOS technology and is suitable for the low voltage supply of current integrated circuits. Simulation results, in terms of EMI immunity, are presented and compared with classical architectures.

A charge-pump architecture is presented with an improved power efficiency and a high voltage output compared to the known Dickson and Favrat architectures due to partial reuse of the charge stored on the capacitors. An 8-stage charge pump fabricated in a 0.13mum CMOS process has a 1.2V supply and a 100MHz clock. The measured performance indicates that the efficiency can be 25% higher than a Favrat cell. The efficiency increases with the number of stages, reaching 60% with 10 stages.

In this paper, a new charge pump architecture is presented: it is based on PMOS pass transistors with dynamic biasing of gates and bodies. By controlling the gate and body voltages of each pass transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Furthermore, the overdrive voltage of the pass transistors grows progressively from the first to the last boost stage. This new architecture was developed and validated through simulations and experimental measurements on AMS 0.8/spl mu/m standard CMOS technology.

In this paper a new integrated charge pump is presented, suitable for current 1.2 V CMOS processes. It is based on both n-MOS and p-MOS pass-transistors with dynamic control of the gate and body voltages. By controlling the gate and the bulk of the pass-transistors, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. The proposed charge pump can be integrated in a standard low-voltage technology: the low-voltage transistors and the simple 2-phase clocking scheme allow the use of higher frequencies, compared to conventional solutions, leading to higher currents, high efficiency and smaller area.

The susceptibility to electromagnetic interference (EMI) of an amplifier based on dynamic threshold voltage MOS transistors (DTMOSs) has been analysed and improved thanks to an easy modification of the input differential stage. The final opamp has been designed in a 0.18 μm standard CMOS process.

In this paper a bandgap reference cell with low susceptibility to electromagnetic interferences is presented. The circuit, based on a classical architecture, is modified by using a symmetrical topology amplifier in the output stage leading to a robust electromagnetic immunity, still preserving good performances in the overall bandgap circuit. Results of the simulations, carried out on the circuit extracted from the layout, are reported and compared to a classical bandgap topology. The reference circuit exhibits a 1200 mV shift for interfering signals in the frequency range of 1 MHz-4 GHz, while the shift in the modified version of the same architecture is only 6 mV in the same frequency range.

A simple bulk-driven Miller amplifier is proposed. Along with the main operational amplifier (opamp) characteristics, the EMI susceptibility has also been investigated. The common nonlinearity problem of bulk-driven opamp architectures has been investigated and solved. The solution reduces also the EMI susceptibility. The proposed opamp has been designed in a 0.35 μm standard CMOS process; it is supplied by 1 V, it exhibits a gain of 90 dB, a gain bandwidth product of 113 kHz, a power consumption of 8.4 μW and a high EMI robustness.

In this paper a fully integrated inductive Step-Up converter is presented. This converter is based on a self-tuned sinusoidal oscillator using two integrated transformers. The circuit converts a 1.8 V voltage supply to 10 V output voltage at 500 /spl mu/A output current. The Step-Up converter is fabricated using the ST 0.18 /spl mu/m M8 CMOS process. The overall core area is 300 /spl mu/m /spl times/ 423 /spl mu/m.

This paper addresses an approach to design bandgap voltage references which provides a good trade-off between overall performances and strong immunity to electromagnetic interferences. We investigated two classical topologies of bandgap references. The first circuit exhibits a 1200mV shift for interfering signals in the frequency range of 1MHz-4GHz, while the shift in the modified version of the same architecture is only 6mV. The second circuit exhibits a 300mV shift in the same frequency range while the shift in its modified version is only 20 mV.