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This registration contain information about my research article "A novel deep learning method for recognizing texts printed with multiple different printing methods" and its extended/underlying data which are required by publisher (F1000Research).

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

Editor-in-Chief Harry Levinson introduces a new set of guidelines for papers related to computational lithography.

Lately, Deep Learning has indicated its capacity by adequately tackling complex learning issues which were not possible previously. Specifically, Convolutional Neural Networks are most generally utilized and have indicated their viability in image detection and recognition problems. Convolutional Neural Networks(CNN) can be used to perform different kinds of tasks. However, to recognize even a single image, billions of calculations are required. For example, ResNet 50 takes 8 billion calculations just to figure out what's in a single image. So we need to find out ways to be able to run that superfast and that's why we need hardware accelerators. In this paper the basic information about Convolutional Neural Networks is provided along with the key operations involved and the brief idea about Field Programmable Gate Arrays(FPGA) is given which enable them to be used for accelerating the inference process of Convolutional Neural Networks. Various techniques which were employed previously for accelerating the Convolutional Neural Networks are discussed. We are focussing on designing a energy efficient Field Programmable Gate Arrays accelerator for accelerating the inference process of Convolutional Neural Networks with reduced latency and increased throughput.

Being able to learn from complex data with phase information is imperative for many signal processing applications. Today’s real-valued deep neural networks (DNNs) have shown efficiency in latent information analysis but fall short when applied to the complex domain. Deep complex networks (DCN), in contrast, can learn from complex data, but have high computational costs; therefore, they cannot satisfy the instant decision-making requirements of many deployable systems dealing with short observations or short signal bursts. Recent, Binarized Complex Neural Network (BCNN), which integrates DCNs with binarized neural networks (BNN), shows great potential in classifying complex data in real-time. In this paper, we propose a structural pruning based accelerator of BCNN, which is able to provide more than 5000 frames/s inference throughput on edge devices. The high performance comes from both the algorithm and hardware sides. On the algorithm side, we conduct structural pruning to the original BCNN models and obtain 20 × pruning rates with negligible accuracy loss; on the hardware side, we propose a novel 2D convolution operation accelerator for the binary complex neural network. Experimental results show that the proposed design works with over 90% utilization and is able to achieve the inference throughput of 5882 frames/s and 4938 frames/s for complex NIN-Net and ResNet-18 using CIFAR-10 dataset and Alveo U280 Board.

We propose a coding scheme for low-latency distributed inference at the network edge that combines a rateless code with an irregular-repetition code. The rateless code provides robustness against straggling servers and serves the purpose of reducing the computation latency, while the irregular-repetition code provides spatial diversity to reduce the communication latency. We show that the proposed scheme yields significantly lower latency than a scheme based on maximum distance separable codes recently proposed by Zhang and Simeone.

The Oblivious Relay serves users without a need to know the users error correcting codes. We extend the oblivious relay concept to channels with interference which is known to the transmitter but not to the receiver. Our system uses structured modulation and coding based on lattices. We show that when the interference is known non-causally, it's influence can be overcome wholly and that in simpler causal schemes the performance is usually within the shaping loss of 0.254 bits/channel use from the optimal performance attainable with large lattices.

The work presented in this paper forms part of a literature review conducted during a study on error detection and correction systems. The research formed the foundation of understanding, touching on space radiation, glitches and upsets, geomagnetism, error detection and correction (EDAC) schemes, and implementing EDAC systems. EDAC systems have been around for quite some time, and certain EDAC schemes have been implemented and tested extensively. However, this work is a more focused study on understanding and finding the best-suited EDAC solution for nanosatellites in low earth orbits (LEO).

Predictions have a long and rich history in online optimization research, with applications ranging from video streaming to electrical vehicle charging. Traditionally, different algorithms are evaluated on their performance given access to the same type of predictions. However, motivated by the problem of bandwidth cost minimization in large distributed systems, we consider the benefits of using different types of predictions. We show that the two different types of predictors we consider have complimentary strengths and weaknesses. Specifically, we show that one type of predictor has strong average-case performance but weak worst-case performance, while the other has weak average-case performance but strong worst-case performance. By using a learning-augmented meta-algorithm, we demonstrate that it is possible to exploit both types of predictors for strong performance in all scenarios.

While there are several frameworks for CNN inference on mobile GPUs, they do not achieve real-time processing for the most of the CNNs that aim at reasonable accuracy since they all employ kernel-by-kernel execution model and do not effectively support INT8 quantization yet. In this paper, we reveal that mobile GPUs suffer from large kernel launch overhead unlike server GPUs, and then propose an on-device deep learning inference framework that can achieve real-time inference of CNNs on mobile GPUs by removing kernel launch overhead and by effectively exploiting INT8 quantization. We have evaluated the proposed framework with a state-of-the-art CNN based face detector (RetinaFace), and observed up to 2.01X of speedup compared to ARM Compute Library (ACL) on a commodity smartphone.

Value Prediction was proposed to speculatively break true data dependencies, thereby allowing Out of Order (OOO) processors to achieve higher instruction level parallelism (ILP) and gain performance. State-of-the-art value predictors try to maximize the number of instructions that can be value predicted, with the belief that a higher coverage will unlock more ILP and increase performance. Unfortunately, this comes at increased complexity with implementations that require multiple different types of value predictors working in tandem, incurring substantial area and power cost. In this paper we motivate towards lower coverage, but focused, value prediction. Instead of aggressively increasing the coverage of value prediction, at the cost of higher area and power, we motivate refocusing value prediction as a mechanism to achieve an early execution of instructions that frequently create performance bottlenecks in the OOO processor. Since we do not aim for high coverage, our implementation is light-weight, needing just 1.2 KB of storage. Simulation results on 60 diverse workloads show that we deliver 3.3% performance gain over a baseline similar to the Intel Skylake processor. This performance gain increases substantially to 8.6% when we simulate a futuristic up-scaled version of Skylake. In contrast, for the same storage, state-of-the-art value predictors deliver a much lower speedup of 1.7% and 4.7% respectively. Notably, our proposal is similar to these predictors in performance, even when they are given nearly eight times the storage and have 60% more prediction coverage than our solution.

In this paper, we introduce the optimal design methods of 3D NAND nvCIM [1], and then address the read disturb reliability issue. In recent years CIM [2] is widely considered as a promising solution to accelerate the DNN inference hardware. Theoretically, nvCIM can drastically reduce the power consumption by data movement because of no need to move the weights during computation. 3D NAND has the advantage of extremely low Icell (~nA), while the large ON/OFF ratio provides the capability to sum >10’000 cells together to improve the performance bandwidth and energy efficiency. We think that 3D NAND nvCIM has the potential to serve as the inference accelerator for the high-density fully- connected (FC) network which often requires high-bandwidth inputs. The read disturb property is studied. It is suggested that the "on-the-fly" calibration technique can well maintain the inference accuracy for 10-year usage.

Video detection and classification constantly involve high dimensional data that requires a deep neural network (DNN) with huge number of parameters. It is thereby quite challenging to develop a DNN video comprehension at terminal devices. In this paper, we introduce a deeply tensor compressed video comprehension neural network called DEEPEYE for inference at terminal devices. Instead of building a Long Short-Term Memory (LSTM) network directly from raw video data, we build a LSTM-based spatio-temporal model from tensorized time-series features for object detection and action recognition. Moreover, a deep compression is achieved by tensor decomposition and trained quantization of the time-series feature-based spatio-temporal model. We have implemented DEEPEYE on an ARM-core based IOT board with only 2.4W power consumption. Using the video datasets MOMENTS and UCF11 as benchmarks, DEEPEYE achieves a 228.1× model compression with only 0.47% mAP deduction; as well as 15k× parameter reduction yet 16.27% accuracy improvement.

Robustness is a key requirement for deploying a machine learning (ML) based solution. When a solution involves a ML model whose robustness is not guaranteed, ensuring robustness of the solution might rely on continuous checking of the ML model for its validity after the solution is deployed in production. Using wafer image classification as an example, this paper introduces tensor-based methods that help improve robustness of a neural-network-based classification approach and facilitate its deployment. Experiment results based on data from a commercial product line are presented to explain the key ideas behind the tensor-based methods.

Rapid advancement in the domain of quantum technologies have opened up researchers to the real possibility of experimenting with quantum circuits, and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise pose a challenge in smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit counts with recent emphasis on topology-aware (nearest-neighbour compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks, show that the fidelity of the circuit can be improved up to 3.37 × with an average improvement of 1.87 ×.

“Writing on dirty paper” refers to the communication problem over a channel with both noise and interference, where the interference is known to the encoder non-causally and unknown to the decoder. This problem is regarded as a basic building block in both the single-user and multiuser communications, and it has been extensively investigated by Costa and other researchers. However, little is known in the case that the encoder can have access to feedback from the decoder. In this paper, we study the dirty-paper coding problem for feedback Gaussian channels without or with memory. We provide the most power efficient coding schemes for this problem, i.e., the schemes achieve lossless interference cancelation. These schemes are based on the Kalman filtering algorithm, extend the Schalkwijk-Kailath feedback codes, have low complexity and a doubly exponential reliability function, and reveal the interconnections among information, control, and estimation over dirty-paper channels with feedback. This research may be found useful to, for example, powerconstrained sensor network communication.

Due to continued technology scaling, electromigration (EM) signoff has become increasingly difficult, mainly due to the use of inaccurate methods for EM assessment, such as the empirical Black's model. In this paper, we review the state of the art for EM verification in on-die power/ground grids, with emphasis on a recent finite-difference based approach for power grid EM checking using physics-based models. The resulting model allows the EM damage across the power grid to be simulated based on a Linear Time Invariant (LTI) system formulation. The model also handles early failures and accounts for their impact on the grid lifetime. Our results, for a number of IBM power grid benchmarks, confirm that existing approaches for EM checking can be highly inaccurate. The lifetimes found using our physics-based approach are on average about 2X, or more, those based on the existing approaches, showing that existing EM design guidelines are overly pessimistic. The method is also quite fast, with a runtime of about 8 minutes for a 4M node grid, and so it is suitable for large circuits.

Recently, the development of quantum chips has made great progress – the number of qubits is increasing and the fidelity is getting higher. However, qubits of these chips are not always fully connected, which sets additional barriers for implementing quantum algorithms and programming quantum programs. In this paper, we introduce a general circuit optimizing scheme, which can efficiently adjust and optimize quantum circuits according to arbitrary given qubits’ layout by adding additional quantum gates, exchanging qubits and merging single-qubit gates. Compared with the optimizing algorithm of IBM’s QISKit, the quantum gates consumed by our scheme is 74.7%, and the execution time is only 12.9% on average.

This paper describes the problem of intelligent paper grouping and its mathematical model. By optimizing and improving the traditional dynamic programming algorithm, its space complexity is reduced from O(nb) to O(b). At the same time, the flexibility of dynamic programming algorithm is increased by using marker function and tracking algorithm, and the result composition is tracked to obtain the optimal solution. Finally, through several experiments, the improved dynamic programming algorithm is compared with the greedy algorithm and brute force algorithm, and it is found that the improved dynamic programming algorithm has a very good result and is with high efficiency when applied to the simple test paper. It is the most recommended algorithm among the two algorithms compared in this paper.

In this paper, we propose a dirty paper coding (DPC) scheme that uses trellis shaping for the overlay cognitive radio channel, where a cognitive user and a primary user transmit concurrently in the same spectrum. Interference of the primary user is assumed to be known at the cognitive transmitter non-causally. Based on this knowledge, the shaping code selection, as a key feature of the proposal, is introduced which enables the constellation to be self adaptively changed. The performance of our proposed scheme is compared using simulations with that based on the conventional trellis shaping and it achieves excellent tradeoff between performance and complexity.

We develop a system for generating embedded diagnostics from an ODE model that can isolate faults given the memory and processing limitations of the embedded processor. This system trades off diagnosis isolation accuracy for inference time and/or memory in a principled manner. We use a Polynomial Regression approach for tuning the performance of an ensemble of low-fidelity ODE diagnosis models such that we achieve the target of embedded processing limits. We demonstrate our approach on a non-linear tank benchmark system.

The recent breakthroughs of deep reinforcement learning (DRL) technique in Alpha Go and playing Atari have set a good example in handling large state and actions spaces of complicated control problems. The DRL technique is comprised of (i) an offline deep neural network (DNN) construction phase, which derives the correlation between each state-action pair of the system and its value function, and (ii) an online deep Q-learning phase, which adaptively derives the optimal action and updates value estimates. In this paper, we first present the general DRL framework, which can be widely utilized in many applications with different optimization objectives. This is followed by the introduction of three specific applications: the cloud computing resource allocation problem, the residential smart grid task scheduling problem, and building HVAC system optimal control problem. The effectiveness of the DRL technique in these three cyber-physical applications have been validated. Finally, this paper investigates the stochastic computing-based hardware implementations of the DRL framework, which consumes a significant improvement in area efficiency and power consumption compared with binary-based implementation counterparts.

While the information theoretic result commonly referred to as “dirty paper coding” [1] has been known for long, it has not led to practical schemes that can be implemented easily in real-life communication systems. In this paper, we present the concept of sum codes and show how they provide a convenient platform for dirty paper coding. Comb-combined sum codes, which provide a convenient method of sum-code construction, are particularly useful in this respect. One can build comb-combined sum codes based on any linear block code to achieve reduction in the transmit energy required to attain a desired performance. Using an example based on tail-biting convolutional codes, we show how practical dirty paper coding may be implemented using any convenient linear block code.

Although the information theoretic result referred to as “dirty paper coding” [1] has been known for quite a while, it has not led to schemes that look attractive enough for real-life communication systems. In a companion paper [2], we presented the concept of sum codes and showed how they provide a convenient platform for interference suppression via dirty paper coding. In this paper, we present a dirty paper coding scheme based on trellis-coded modulation, which could be looked upon as an alternative to the sum-codes-based approach. Since trellis-coded modulation is designed for multi-level signal constellations, it is expected to work well as a platform for the proposed dirty paper coding scheme in which multi-level signal constellations play a critical role.

Recently two-way relaying has become a promising protocol. The design of the processing matrix of the two-way relay channel is of significant importance since it could dramatically influence the system performance. In this paper, we propose a nonlinear design of the relay processing matrix with dirty paper coding (DPC). And compared with the traditional linear schemes, it could amplify the useful signal and mitigate the impact of interference and noise. Moreover, the multi-user scenario, which is more common in the practice, is also taken into consideration. And based on different receive criterions DPC-ZF algorithm and DPC-MMSE algorithm are proposed. Simulation results show that both DPC-ZF and DPC-MMSE have a higher throughput and lower bit error ratio (BER) performance compared with the traditional AF algorithm and zero-forcing (ZF) algorithm.

Code obfuscation is the de facto standard to protect intellectual property when delivering code in an unmanaged environment. It relies on additive layers of code tangling techniques, white-box encryption calls and platform-specific or tool-specific countermeasures to make it harder for a reverse engineer to access critical pieces of data or to understand core algorithms. The literature provides plenty of different obfuscation techniques that can be used at compile time to transform data or control flow in order to provide some kind of protection against different reverse engineering scenarii. Scheduling code transformations to optimize a given metric is known as the pass scheduling problem, a problem known to be NP-hard, but solved in a practical way using hard-coded sequences that are generally satisfactory. Adding code obfuscation to the problem introduces two new dimensions. First, as a code obfuscator needs to find a balance between obfuscation and performance, pass scheduling becomes a multi-criteria optimization problem. Second, obfuscation passes transform their inputs in unconventional ways, which means some pass combinations may not be desirable or even valid. This paper highlights several issues met when blindly chaining different kind of obfuscation and optimization passes, emphasizing the need of a formal model to combine them. It proposes a non-intrusive formalism to leverage on sequential pass management techniques. The model is validated on real-world scenarii gathered during the development of an industrial-strength obfuscator on top of the LLVM compiler infrastructure.

Multithreaded programs are prone to dataraces. Dataraces are known to be hard to detect and reproduce by manual effort, although they often have detrimental effects on program reliability. Automated techniques are thus demanded for detecting dataraces efficiently and precisely. There have been proposed a lot of datarace detectors so far, among which dynamic ones are promising because of their precision. However, existing dynamic race detectors incur high race-checking overheads. Even a state-of-the-art dynamic race detector, called Parallel FastTrack, fails to efficiently detect races under certain conditions, despite its attempt to parallelize race detection for efficiency. In this paper, we propose an efficient and precise parallel race detector. For our proposal, we first experimentally reveal that the load-distribution policy of Parallel FastTrack tends to skew race-checking loads to a few detection threads. We then present a simple but effective technique, called POI, for balancing race-checking loads among detection threads. POI takes race-checking loads of each detection thread into account and reduces the load skew by making each detection thread manage almost the same number of memory addresses to be checked. Experiments on several real multithreaded data-processing applications show that POI succeeded in reducing, on average, about 37% of race detection overheads, which the load-distribution policy of Parallel FastTrack would impose.

We present an information-theoretic approach to discrete signal processing called information-optimum signal processing for the example of a wireless receiver comprising LDPC decoding, channel estimation and detection. All operations are replaced by simple lookup tables and all messages which are exchanged between detection stages are unsigned integers. The lookup tables are designed offline using the information bottleneck concept of preserving relevant information. We show that the approach allows for simple signal processing with coarse quantization while achieving virtually the same performance as conventional signal processing approaches with high resolution, e.g. double precision. The contribution of the paper is a tutorial style explanation of the concept as well as an exemplary survey of applications and performance results which illustrate the potential of the concept.

Recently, EM lens-embedded massive array antennas have been proposed for next 5G mobile wireless communications, as the adoption of a lens allows to discriminate the AOA of signals in the analog domain, with the possibility to preserve the processing complexity lower with respect to traditional massive arrays. In fact, in such a way, complex ADC chains can be avoided and the number of required antennas can be decreased. By exploiting these advantages, in this paper we study the possibility to use a single EM lens massive array at mm-wave for the AOA estimation of the received signal. In this perspective, ML estimator and practical approaches, tailored for the considered scenario, are derived. Results, obtained for different number of antennas, confirm the possibility to achieve interesting AOA estimation performance with an extremely compact architecture.

Automated techniques for analysis and optimization of finite-precision computations have recently garnered significant interest. Most of these were, however, developed independently. As a consequence, reuse and combination of the techniques is challenging and much of the underlying building blocks have been re-implemented several times, including in our own tools. This paper presents a new framework, called Daisy, which provides in a single tool the main building blocks for accuracy analysis of floating-point and fixed-point computations which have emerged from recent related work. Together with its modular structure and optimization methods, Daisy allows developers to easily recombine, explore and develop new techniques. Daisy’s input language, a subset of Scala, and its limited dependencies make it furthermore user-friendly and portable.

The ever-escalating attacks on the internet network are due to rapid technological growth. In order to surmount such challenges, multi-layer security algorithms were developed by hybridizing cryptography and steganography techniques. Consequently, the overall memory size became enormous while hybridizing these techniques. On the other side, the least significant bit (LSB) and modified LSB replacing approaches could provide the variability as detected by steganalysis technique, most found to be susceptible to attack too due to numerous reasons. To overcome these issues, in this paper a lightweight and optimized data hiding algorithm is proposed which consume less memory, provide less variability, and robust against histogram attacks. The proposed steganography system was achieved in two stages. First, data was encrypted using lightweight BORON cipher that only consumed less memory as compared to conventional algorithm such as 3DES, AES. Second, the encrypted data was hidden in the complemented or non-complemented form to obtain minimal variability. The performance of the proposed technique was evaluated in terms of avalanche effect, visual quality, embedding capacity and peak signal to noise ratio (PSNR). The results revealed that the lightweight BORON cipher could produce approximate same avalanche effect as the AES algorithm produced. Furthermore, the value of PSNR had shown much improvement in comparison to optimization algorithm GA.

International audience; This paper deals with the improvement of the Dirty Paper Trellis Code (DPTC) watermarking algorithm. This watermarking algorithm is known to be one of the best among the high rate watermarking schemes. Nevertheless, recent researches reveal its security weakness. Previously, we proposed to reinforce its security by using a secret space before the embedding. This secret space requires to compute projections onto secrets carriers. When dealing with high rate watermarking, the CPU cost for those projections is dramatically high. After introducing the watermarking scheme, we then propose two Space Division Multiplexing (SDM) approaches which reduce the complexity. Evaluations are achieved with four different attacks and show that our proposal gives better robustness results with SDM approaches.

Personal computers (PCs) are increasingly being used in industrial applications. Graphical user interface (GUI) software and Windows-based operating systems are proving to be cost-effective, rugged and reliable. These advances have allowed over the the successful installation of several human-machine interface (HMI) systems for paper machine winders. The HMI monitors the operation of a winder and provides complete machine control. An operator interface was developed to both monitor and control a multi-section paper machine drive. The application described highlights the use of a redundant multi-computer network to replace existing benchboard controls. New monitoring and control features and a unique reel roll-density-control scheme were included. The goals achieved were increased paper production and improved control of reel building.

Convolutional Neural Networks (CNNs) have been widely investigated as some of the most promising solution for various computer vision tasks. However, CNNs introduce massive computing overhead due to their complex network computing flow, resulting in significantly reduced applicability and performance, especially in the mobile devices. Various optimization schemes have been proposed mainly based on both model compression and stacked external computing resources. While these schemes have been proven effective, methods which take into account mobile-specific context-aware optimization approaches have been largely overlooked. One such opportunity is the feasible CNN computing flow simplification to the under-test objects with distinguish features, which can be efficiently pre-analyzed inside the mobile sensor system. Hence, we propose VoCaM, a visualization oriented CNN acceleration framework on mobile devices for image classification tasks. VoCaM takes advantage of the mobile camera system, where the comprehensive pre-analysis can be conducted to reveal the color composition of the under-test images without incurring any additional overhead. Also, the visualization analysis of VoCaM reveals that, certain color-specific filters may have very trivial result impact when the under-test images have mismatching primary color components. Then a set of approximate computing methods is applied to these insignificant filters to replace the intensive convolutional operation, and greatly accelerate the computing process. With ignorable overhead, VoCaM can significantly optimize the computation load of the convolutional layers, with very small impact on the overall classification accuracy.

In physical implementation, the quality of net open location finder would directly impact the quality of final routing result. It is important to consider both of the length of indicated paths and the turnaround time. To address this problem, the ICCAD-2017 contest encourages the research in obstacle-aware multi-layer shortest paths finding and the corresponding speedup techniques. We provided (i) a set of benchmarks and (ii) an evaluation metric that facilitate contestants to develop and test their new algorithms.

MIMO systems are of interest to meet the expected demands for higher data rates and lower delays in future wireless systems. The introduction of multiple transmit antennas adds additional complexity to any scheduling algorithm for the multi-user system. It is optimal to transmit to multiple users simultaneously in contrast to a single user in a single-input single-output (SISO) system, resulting in a combinatorial optimization problem. In this paper, we analyze the performance of scheduling through utility functions implemented via a genetic algorithm. Namely, we investigate the maximum throughput and the proportionally fair utility functions. The analysis is in the context of a MIMO broadcast channel using dirty paper coding (DPC). This paper builds upon earlier work using zero-forcing beamforming instead of DPC. Under DPC, the order of user encoding affects the user data rates and hence the performance of the scheduling algorithm. We demonstrate that the genetic algorithm is able to achieve a near-optimal performance relative to an exhaustive search at a significant reduction in computational complexity.

Stochastic Petri nets (SPNs) are widely used for the performance evaluation of computer and telecommunication systems. They inherit from their untimed version the capability of modeling parallel computations in a simple, graphical way. Simulation of SPNs is an important way to assess the performance of a system measured as throughput, response time or expected number of customers/resources in some places. Perfect sampling allows for the selection of the initial state of a simulation with a probability which corresponds to its stationary probability and hence the warm-up period is not required any more. In this paper we present performance tests of spnps, a tool based on some previous works that implements perfect sampling algorithm for SPNs by using decision diagrams. We test performance of the tool on a class of stochastic models of great importance in the quantitative evaluation of distributed systems and communication networks: the fork-join queueing networks.

Wet paper codes are used to design steganographic schemes, in which the sender can embed messages into a cover with arbitrarily selected changeable bits that are not shared by the recipient. In this letter, we propose a novel approach to wet paper codes by folding the cover into several layers and applying basic wet paper coding methods with low computational complexity to each layer. This method uses the changes introduced in the first layer to embed messages into every layer and therefore achieves high embedding efficiency (average number of bits embedded by per change).

Exploiting resource reusability and low precision in neural networks is a promising approach to achieve energy efficient computational platforms. This research presents two generalizable approaches to reuse resources in feed-forward neural networks and demonstrated on extreme learning machines. In the first approach, coalescing, a single stack of neuronal units perform both feature extraction and classification tasks through shared resources. In the second approach, folding, the neurons in a high-dimension feedforward layer are folded to execute multiple-tasks. The folding technique can also be combined with low precision modules. The proposed design techniques are validated for a classification task on binary (Australian credit and Diabetes corpus) and multi-class (MNIST) dataset. The total power consumption is measured to be 3.65 mW on TSMC 65nm technology node, while yielding an accuracy of 91.7% for MNIST.

Nowadays, Wi-Fi is a very popular Technology. Faster data transfer and Security both are very important for Wi-Fi. At present, Advanced Encryption Standard (AES) is used for Wi-Fi that is more secured than other encryption algorithms but it is not so fast because of it's complex functions. On the other hand, Blowfish is a very faster encryption algorithm but it cannot apply on Wi-Fi because of it's security problems. In this paper, a hybrid algorithm of Blowfish and Rivest Cipher 6 (RC6) is proposed that solves the security problems of Blowfish and also maintains the fastness of Blowfish and makes it able to use it in place of AES. It uses two innovative criteria. One is ingenious confusion process using two random numbers "a" and "w" that removes reflectively weak key attack and Known plaintext attack of Blowfish. The other is usage of one S-Box by overlapping process that eliminates the collision key attack of Blowfish. Sub key generation process of this algorithm also removes the Brute Force attack of AES. This paper tries to give an efficient algorithm that enhances the performance of Blowfish algorithm by adding a function of RC6 with it. The adding process is trickily handed here that makes the proposed algorithm as fast as Blowfish and also secured like existing AES. The proposed algorithm takes less encryption –decryption time like Blowfish and also secured like AES. Throughput, Average time for different data lengths and attack removal process are used to measure the efficiency of this proposed algorithm.

Cognitive radar refers to an adaptive sensing system exhibiting high degree of waveform adaptivity and diversity enabled by intelligent processing and exploitation of information from the environment. The next generation of radar systems are characterized by their application to scenarios exhibiting non-stationary scenes as well as interference caused by use of shared spectrum. Cognitive radar systems, by their inherent adaptivity, seem to be the natural choice for such applications. However, adaptivity opens up reliability issues due to uncertainties induced in the information gathering and processing. This paper lists some of the reliability aspects foreseen for cognitive radar systems and motivates the need for waveform designs satisfying different metrics simultaneously towards enhancing the reliability. An iterative framework based on multi-objective optimization is proposed to provide Pareto-optimal waveform designs.

Paper on Gesture Recognition

A knowledge map, which has been recently applied in various fields, is discovering characteristics hidden in a large amount of information and showing a tangible output to understand the meaning of the discovery. In this paper, we suggested a knowledge map for research trend analysis based on keyword-relation networks which are constructed by using a database of the domestic journal articles in the computer engineering field from 2000 through 2010. From that knowledge map, we could infer influential changes of a research topic related a specific keyword through examining the change of sizes of the connected components to which the keyword belongs in the keyword-relation networks. In addition, we observed that the size of the largest connected component in the keyword-relation networks is relatively small and groups of high-similarity keyword pairs are clustered in them by comparison with the random networks. This implies that the research field corresponding to the largest connected component is not so huge and many small-scale topics included in it are highly clustered and loosely-connected to each other. our proposed knowledge map can be considered as a approach for the research trend analysis while it is impossible to obtain those results by conventional approaches such as analyzing the frequency of an individual keyword.

Due to the continually growing complexity demands of integrated circuits (ICs), electronic design automation flows must enable efficient design of ICs through design entry at higher abstraction levels. IC design has gradually transitioned from circuit-level to logic-level, register-transfer level, behavioral-level and now electronic-system-level design abstractions. Higher abstraction levels are required to make large scale design entry feasible, but design and development of tools for such design entry poses significant research challenges. The research community has tackled these problems individually by decomposing the synthesis problem into a series of sequential stages. Although this strategy has proven successful and led to the rise of commercial synthesis tools, necessary major improvements require optimizing the interactions and interdependencies between these stages. In this paper, we discuss challenges and opportunities for optimizing inter-stage interactions, and present results of four example works that target these interactions.