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The keywords for the ubiquitous network and high-information-content era are “information” and “audio-visual”. Novel devices to serve the needs of ubiquitous network require powerful input-output terminals with exceptional characteristics. In response to these requirements, we have developed high performance TFTs and “System LCD” using CG Silicon® technology. In addition, we have demonstrated advanced system integration technology for mobile application such as sensors, the fusion of “audio” with “visual” and fine picture quality with good image control. For future, ubiquitous information tools, we are developing super-advanced poly-Si TFT devices capable of frequencies of over 1GHz on glass substrate.

A data processing system for paper testing utilising local area network (LAN) has beendeveloped as a part of laboratory automation program. The system consists of paper testinginstruments, personal computers, and a LAN network. Testing results are made into a reportby communicating data between instruments and computers, and between computers.

The goal of this work is to introduce and discuss different kinds of emerging technologies for logic circuitry and memory with respect to the key question of how they will impact future system-on-chip architectures and system-level management techniques. It is obvious that emerging technologies should have an impact there in order to fully exploit their technological advantages but also in order to deal with any disadvantages they might come with. In this special session paper, three promising emerging technologies are presented: (i) Negative Capacitance Field-Effect Transistor (NCFET) as a new CMOS technology with advantages primarily for low-power design, (ii) Ferroelectric FET (FeFET) as a non-volatile, area-efficient and low-power combined logic and memory as well as (iii) a Phase-Change Memory (PCM) and Resistive RAM (ReRAM) offering a large potential for tackling the memory wall problem in the von Neumann architecture. Our analysis demonstrates that not only new computing paradigms are promoted by these new technologies, it will also be seen that the trade-offs between the classical design parameters of low power, performance etc. will shift and hence emerging technologies will offer new Pareto points in the design space of future on-chip architectures. In that context, this work is unique as it bridges the gap between the technology side and system/architecture-level side to draw a vision of new technologies and their impact on architectures and system-level management.

Publisher Summary Integrated Circuit (IC) technology has made the production of chips with several transistors possible. Systems of such complexity are difficult to design. The computer architect faces problems in the areas of system partitioning with sub goal specification, subsystems interface specification and verification, and overall system integration. This improvement in IC technology allows the fabrication of processors with complexity, comparable to the largest mainframe computers designed using off-the-shelf technologies (SSI, MSI, and LSI). The advent of very large scale integrated (VLSI) processor has significantly changed the way in which computers are designed and implemented. This chapter discusses the use of VLSI as an implementation medium and it focuses on the design of general purpose microprocessors. In many ways, the architecture and organization of a VLSI processor are similar to the designs used in the CPUs of modern machines implemented by using standard parts. The MOS technology imposes some new constraints that emphasize on the interaction between architecture and implementation. The chapter discusses the issues that arise in determining the suitability of architecture as a program host, the implications of the architecture on the organization, and some guidelines to help evaluate the suitability of architecture both for an application environment and for implementation using VLSI.

CMOS technology and its Moore’s Law scaling is an enormously successful technology paradigm that has continued to transform our computation and communication abilities. Outside the applications in computation and communication, CMOS technology has been increasingly applied to the life sciences, with a wealth of silicon integrated circuits developed to interface with biological molecules and cells. Concretely, large-scale arrays of active electrodes are integrated using CMOS technology for highly parallel electronic detection of biomolecular/ionic charges and cellular potentials for DNA sequencing, molecular diagnostics, and electrophysiology. Parallelism enabled by CMOS scalability is well suited to process the big data in these biotechnological applications. Here we offer a brief review on these CMOS-bio interfaces, while the corresponding presentation will focus on a sub-topic of CMOS electrophysiology with mammalian neurons.

Background Obtaining explicit consent from patients to use their remnant biological samples and deidentified clinical data for research is essential for advancing precision medicine. Objective We aimed to describe the operational implementation and scalability of an electronic universal consent process that was used to power an institutional precision health biobank across a large academic health system. Methods The University of California, Los Angeles, implemented the use of innovative electronic consent videos as the primary recruitment tool for precision health research. The consent videos targeted patients aged ≥18 years across ambulatory clinical laboratories, perioperative settings, and hospital settings. Each of these major areas had slightly different workflows and patient populations. Sociodemographic information, comorbidity data, health utilization data (ambulatory visits, emergency room visits, and hospital admissions), and consent decision data were collected. Results The consenting approach proved scalable across 22 clinical sites (hospital and ambulatory settings). Over 40,000 participants completed the consent process at a rate of 800 to 1000 patients per week over a 2-year time period. Participants were representative of the adult University of California, Los Angeles, Health population. The opt-in rates in the perioperative (16,500/22,519, 73.3%) and ambulatory clinics (2308/3390, 68.1%) were higher than those in clinical laboratories (7506/14,235, 52.7%; P Conclusions This is one of the few large-scale, electronic video–based consent implementation programs that reports a 65.5% (26,314/40,144) average overall opt-in rate across a large academic health system. This rate is higher than those previously reported for email (3.6%) and electronic biobank (50%) informed consent rates. This study demonstrates a scalable recruitment approach for population health research.

This paper presents an application-specific instruction-set processor (ASIP) for multiuser multiple-input multiple-output (MU-MIMO) broadcast precoding. The ASIP is designed for a base station (BS) with four antennas to perform user scheduling and precoding. Transport triggered architecture (TTA) is used as the processor template and high level language is used to program the ASIP. Several special function units (SFU) are designed to accelerate norm-based greedy user scheduling and minimum-mean square error (MMSE) precoding. We also program zero forcing dirty paper coding (ZF-DPC) to demonstrate the reusability of the ASIP. A single core provides a throughput of 52.17 Mbps for MMSE precoding and takes an area of 87.53 kgates at 200 MHz on 90 nm technology.

This paper presents results of a user study into extending the functionality of an existing case-based search engine for similar architectural designs to a flexible process-oriented case-based support tool for the architectural conceptualization phase. Based on a research examining the target group’s (architects) thinking and working processes during the early conceptualization phase (especially during the search for similar architectural references), we identified common features for defining retrieval strategies for a more flexible case-based search for similar building designs within our system. Furthermore, we were also able to infer a definition for implementing these strategies into the early conceptualization process in architecture, that is, to outline a definition for this process as a wrapping structure for a user model. The study was conducted among the target group representatives (architects, architecture students and teaching personnel) by means of applying the paper prototyping method and Business Processing Model and Notation (BPMN). The results of this work are intended as a foundation for our upcoming research, but we also think it could be of wider interest for the case-based design research area.

A framework of open interoperable simulators for computer architecture is long overdue. Today there are many separate, uncoordinated efforts to develop simulation and modeling artifacts (tools) for computer architecture research. The artifacts are used to empirically evaluate new computer architecture innovations and compare them with the state of the art. The artifacts are usually developed by individual groups, often for a specific purpose, and may not be publicly released. Consequently, it is difficult to leverage investment in artifact development and to repeat or reproduce experiments. In this position paper, we present recommendations and a roadmap for sharing and building open-source, interoperable simulation and modeling artifacts. The recommendations are the outcome of a community workshop involving industry, government and academia to determine how to coordinate effort, share tools and improve methodology.

This short paper proposes two novel methodologies for analyzing scientific applications in distributed environments, using workload requirements. The first explores the impact of features such as problem size and programming language, over different computational architectures. The second explores the impact of mapping virtual cluster resources on the performance of parallel applications.

1. ABSTRACT Dynamic modifications to architectures include replacing components and re-wiring of connectors. In this position paper we present the manner in which architectures can perform self-governed re-configurations dynamically using rule-based architectural agents. Agents can monitor the architecture and perform simple re-configurations. This paper describes work in progress, and point out interesting areas of research connected to architectural agents.

Summary form only given. The full paper presents a number of approaches to choreographing regular and irregular computations, and shows how a number of model applications can be choreographed. The paper will also compare SMA architectures to UMA and NUMA architectures.

The aim of the KCM (Knowledge Crunching Machine) project was to study how to speed-up Prolog, and more generally Logic Programming, through hardware support at the processor level. An experimental approach was taken, which resulted in the design and implementation of a real system, hardware and software. This short paper outlines the key features of the system as well as the main conclusions which can be drawn from the project.

The aim of this short paper is to set out the author’s views on the issues which must be addressed by a real-time systems specification, design and implementation method. This is a very broad topic, so the main focus is on timing issues, and on the overall specification process. More specifically the paper sets out views on how specifications are, or should be, derived progressively from high level requirements, and considers the nature of systems architectures, which defines both the needs for high level design specification, and the constraints on implementation.

As computing has moved relentlessly through giga-, tera-, and peta-scale systems, exa-scale (a million trillion operations/sec.) computing is currently under active research. DARPA has recently sponsored the "UHPC" [1] --- ubiquitous high-performance computing --- program, encouraging partnership with academia and industry to explore such systems. Among the requirements are the development of novel techniques in "self-awareness"in support of performance, energy-efficiency, and resiliency.Trends in processor and system architecture, driven by power and complexity, point us toward very high-core-count designs and extreme software parallelism to solve exascaleclass problems. Our research is exploring a fine-grain, event-driven model in support of adaptive operation of these machines. We are developing a Codelet Program Execution Model which breaks applications into codelets (small bits of functionality) and dependencies (control and data) between these objects. It then uses this decomposition to accomplish advanced scheduling, to accommodate code and data motion within the system, and to permit flexible exploitation of parallelism in support of goals for performance and power.

This short paper briefly describes the computer architecture courses at the University of Illinois Urbana-Champaign. It then examines the opinions of computer architecture undergraduate and graduate students who have taken these courses. Based on these opinions, suggestions are made on how to improve the curriculum.

The University of Illinois has traditionally been a major center for computer architecture education and research in the nation. This short paper briefly describes the computer architecture curriculum at the University of Illinois and discusses a few ideas for improving the computer architecture education of our students. In particular, to improve the education of undergraduates, we suggest a higher emphasis on parallel architectures and programming, and the provision of practical experiences. For graduate students, we argue about the need to develop close links with industry and educate graduate students from other scientific and engineering disciplines.

In the Address Programming Language (1955), the concept of indirect addressing of higher ranks (Pointers) was introduced, which allows the arbitrary connection of the computer’s RAM cells. This connection is based on standard sequences of the cell addresses in RAM and addressing sequences, which is determined by the programmer with indirect addressing. Two types of sequences allow programmers to determine an arbitrary connection of RAM cells with the arbitrary content: data, addresses, subroutines, program labels, etc. Therefore, the formed connections of cells can relate to each other. The result of connecting cells with the arbitrary content and any structure is called tree-shaped formats. Tree-shaped formats allow programmers to combine data into complex data structures that are like abstract data types. For tree-shaped formats, the concept of “review scheme” is defined, which is like the concept of “bypassing” trees. Programmers can define multiple overview diagrams for the one tree-shaped format. Programmers can create tree-shaped formats over the connected cells to define the desired overview schemes for these connected cells. The work gives a modern interpretation of the concept of tree-shaped formats in Address Programming. Tree-shaped formats are based on “stroke-operation” (pointer dereference), which was hardware implemented in the command system of computer “Kyiv”. Group operations of modernization of computer “Kyiv” addresses accelerate the processing of tree-shaped formats and are designed as organized cycles, like those in high-level imperative programming languages. The commands of computer “Kyiv”, due to operations with indirect addressing, have more capabilities than the first high-level programming language – Plankalkül. Machine commands of the computer “Kyiv” allow direct access to the i-th element of the “list” by its serial number in the same way as such access is obtained to the i-th element of the array by its index. Given examples of singly linked lists show the features of tree-shaped formats and their differences from abstract data types. The article opens a new branch of theoretical research, the purpose of which is to analyze the expe- diency of partial inclusion of Address Programming in modern programming languages., В Адресному програмуванні було введено поняття опосередкованої адресації вищих рангів (Pointers), яка дає змогу довільним чином з’єднувати комірки оперативної пам’яті комп’ютера. Засадами цього з’єднання є стандартне слідування адрес комірок в оперативній пам’яті та адресне слідування, яке визначається опосередкованою адресацією. Використання двох відношень дає можливість визначати довільне об’єднання комірок пам’яті з будь-яким їх змістом. Машинні команди комп’ютера «Київ» надають прямий доступ до елементу «списку» за його порядковим номером. У статті на прикладах однозв’язних «списків» продемонстровано особливості деревоподібних форматів та їх відмінності від абстрактних типів даних. Стаття відкриває нову галузь теоретичних досліджень, метою яких є аналіз доцільності включення у сучасні мови програмування окремих можливостей Адресного програмування.

Programs for parallel computers of distributed memory are difficult to write, understand, evaluate and debug. The design and performance evaluation of algorithms is much complex than the conventional sequential one. This short paper describes the PSEE (Parallel System Evaluation Environment), an interactive graphical environment, which permits to study the behaviour of parallel distributed memory systems. PSEE is an easy-to-use environment that enables parallel distributed memory systems programmers take decisions about the behaviour program and parallel computer in terms such as: scalability, tuning and performance of the underlying parallel machine.

When applied to artificial intelligence edge devices, the conventionally von Neumann computing architecture imposes numerous challenges (e.g., improving the energy efficiency), due to the memory-wall bottleneck involving the frequent movement of data between the memory and the processing elements (PE). Computing-in-memory (CIM) is a promising candidate approach to breaking through this so-called memory wall bottleneck. SRAM cells provide unlimited endurance and compatibility with state-of-the-art logic processes. This paper outlines the background, trends, and challenges involved in the further development of SRAM-CIM macros. This paper also reviews recent silicon-verified SRAM-CIM macros designed for logic and multiplication-accumulation (MAC) operations.

In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

This paper provides a review of design approaches towards artificial intelligence (AI) System-on-Chip. AI algorithms have progressed over the past decades from perceptron-based neural network (NN) and neuro-fuzzy (NF) system to today’s deep neural network (DNN) and neuromorphic computing. Recent DNN hardware accelerators focus on energy-efficient integration of digital circuits to realize real-time DNN operation while neuromorphic processors deploy new memory technologies with analog computation for low power consumption. However, different design approaches can be applied to such processor implementation with their pros and cons. This paper reviews from the early processor designs for NN and NF in both mixed-mode and digital implementations to the recent DNN SoC designs that we have proposed for a decade. The former content deals with NN and NF processors used as a functional building block of a machine vision SoC, while the latter concentrates on integration of the whole DNN function. We also provide a discussion on the approaches, and provide perspective on future research directions.

Recent years have seen an increasing interest in the development of artificial intelligence circuits and systems for edge computing applications. In-memory computing mixed-signal neuromorphic architectures provide promising ultra-low-power solutions for edge-computing sensory-processing applications, thanks to their ability to emulate spiking neural networks in real-time. The fine-grain parallelism offered by this approach allows such neural circuits to process the sensory data efficiently by adapting their dynamics to the ones of the sensed signals, without having to resort to the time-multiplexed computing paradigm of von Neumann architectures. To reduce power consumption even further, we present a set of mixed-signal analog/digital circuits that exploit the features of advanced Fully-Depleted Silicon on Insulator (FDSOI) integration processes. Specifically, we explore the options of advanced FDSOI technologies to address analog design issues and optimize the design of the synapse integrator and of the adaptive neuron circuits accordingly. We present circuit simulation results and demonstrate the circuit's ability to produce biologically plausible neural dynamics with compact designs, optimized for the realization of large-scale spiking neural networks in neuromorphic processors., 11 pages, 9 figures, TCAS submission

As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance. In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.

Aim: The method of utilization of IoT and other evolving techniques in medical equipment design field is discussed in the present paper. A remotely managed interface equipped in a wheelchair cum bed is embedded for elderly or physically challenged people. With the help of a camera embedded in the proposed solution, a real-time remote monitoring of the patient is achieved using an android application on the concerned person. For achieving the above mentioned purpose, the use of linear actuators has been done. This paper further aims to explore the hidden potentials of the merger of all these fields to benefit the end users. Objectives: Remote monitoring of health of the patient through a cloud-based android application. Automatic adjustment of the wheelchair into bed and vice-versa. Automatic stool passing chamber facility is available under the proposed model. Injuries during transportation of the patient from one chair to another (or chair to bed) have been limited in our designed model. Methods: The basic mechanism of proposed wheelchair has been designed using the computer-aided design software. The basic methodology adopted for development of prototype & subsequent “user review analysis” is displayed. The CAD Model of the wheelchair cum stretcher was designed using the “Solid works solid modelling techniques”. The basic structure has been designed with several modifications when compared to the conventional wheelchair design. The computer made design was then utilized for final fabrication of the prototype. The prototype was tested for endurance, load bearing capacity and customer comfort during various phases of development. The feedbacks of several subjects were recorded for future utilization in improved design & fabrication. Results: The proposed model is of utmost importance as the number of critical patients like accident cases, critical pre and post-surgery cases is increasing day by day. Sometimes these patients need intime medication during transition in ambulance while they are picked up from houses and referred to nearby big hospitals. During transition or in hospital, critical patients can be handled efficiently by a specialist doctor through his/her smart phone applications. It also optimizes the services of specialist doctors as we can find the shortage of specialists in Indian hospitals. In a nutshell, this WheelChair system can be moved anywhere due to its portability. Following are the most highlighted features: 1. Authorized relatives and Doctors can see and interact with the patient remotely at any time on his/her smart phone. 2. Authorized relatives and Doctors can see the Vital Sign of patient like BP, ECG, and Pulse etc. at any time through Smart Phone. 3. Doctor can instruct the caretaker to release the emergency drugs through Infusion Pump. 4. Doctor can plan the exceptions, drug infusion, alarm, etc. 5. System is portable and can easily be shifted to ambulance. All transmissions are wireless, so there is no hassle of wires and connectivity. Conclusion: The presented work is limited to the design and fabrication of a new model of wheelchair, which works as a stretcher and has locomotive capabilities. The key feature of the design is its versatility and adaptability to various working conditions. The feedback obtained from various subjects during the testing of wheelchair shows their confidence and a fair degree of comfort which they felt while using the wheelchair. The easy and user-friendly use of the android application helps to monitor the health of the patient. The smartphone camera helped to achieve this data. The analysis of the data can be done in the cloud-based station. The linear actuator has proved to be the low cost and highly reliable equipment to propel the wheelchair.

Transmission applications in wireless networks have brought unprecedented demands. The demand for high-performance wireless transmission is increasing day by day. Antenna technology is an indispensable part of the development of wireless communication. One potential solution is to resort t intelligent learning techniques to help breakthroughs in the limited antenna technical field. It is based on an adaptive antenna using intelligent learning. It has laid the foundation for signal strength adjustment to enhance wireless transmission efficiency. This paper evaluates the most advanced literature and techniques. A comprehensive description from different perspectives covers several adaptive antenna structures, including diversity antennas, phased array antennas, and beamforming specific learning methods. After that, this paper divides it into different categories, from intelligent learning algorithms and feature data perspectives in a different light to analyze and discuss. This article expects to help readers understand the latest intelligent technology based on adaptive antennas. Further, it sheds novel light on future research directions to meet the development needs of adaptive antennas for future wireless networks.

Blockchain technologies are gradually being deployed in a variety of industries, including telecommunications. In this paper, due to the strict governance of telecommunication infrastructure, we propose a permissioned distributed ledger (PDL)-based blockchain supported architecture for a network management and orchestration platform. The work focuses on creating a trusted environment for both Cloud Service Providers (CSPs) and Mobile Network Operators (MNOs) for managing the lifecycle of network services (e.g., instantiation, scaling, termination, etc.) in a multi-cloud environment. We also validate our proposed approach with an experimental scenario using the Quorum blockchain network (BCN) to measure various performance metrics (e.g., number of transactions and blocks, time to write, and transactions per second) of different service orchestrator (SO)-related instantiation metrics. Our evaluation results show that the values for the service instantiation time and the corresponding BCN metrics can be completely different, suggesting that some logs arrive very quickly and generate a high transaction load, while others take longer and generate a low number of transactions. As a solution, at the end of the paper, we also provide some recommendations for appropriate optimizations during transfer of SO-related logs to BCNs and some observed challenges. IEEE

As the trend of technology shrinking continues a vast amount of processors are being incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication. Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs. NoCs provide the advantage of customized architecture, increased scalability and bandwidth. NoC is a structured framework where communication is the prime concern. In this review paper we present an overview of research and design approaches in the communication centric areas of NoCs. Here we have tried to discuss and iterate most of the available work done for communication in 2D NoCs. This paper gives the insight of different attributes and performance parameters of NoCs. Further it gives a detailed description of how topology, flow control and routing mechanisms can affect the qualitative aspects (performance) of NoCs. It then explains how various attributes of routing can help in increasing the efficacy of NoCs. Subsequently a brief review of different simulators used for NoCs is given. All of this is provided based on the survey of academic, theoretical and experimental approaches presented in the past. Finally some suggestions for future work are also given.

The Ring-AllReduce framework is currently the most popular solution to deploy industry-level distributed machine learning tasks. However, only about half of the maximum bandwidth can be achieved in the optimal condition. In recent years, several in-network aggregation frameworks have been proposed to overcome the drawback, but limited hardware information have been disclosed. In this paper, we propose a scalable fully-pipelined architecture that handles tasks like forwarding, aggregation and retransmission with no bandwidth loss. The architecture is implemented on a Xilinx Ultrascale FPGA that connects to 8 working servers with 10 Gb/s network adapters, and it is able to scale to more complicated scenarios involving more workers. Compared with Ring-AllReduce, using AllReduce-Switch improves the efficient bandwidth of AllReduce communication with a ratio of $1.75\times $ . In image training tasks, the proposed hardware architecture helps to achieve up to $1.67\times $ speedup to the training process. For computing-intensive models, the speedup from communication may be partially hidden by computing. In particular, for ResNet-50, AllReduce-Switch improves the training process with MPI and NCCL by $1.30\times $ and $1.04\times $ respectively.

Computer Networking Play’s a major role for data communication or data sharing and data transmissions from one location to another, which are geographically differ, but in today’s scenario where the main and primary major concerns are not to data transfer but also utilize all resources with greater efficiency and also preserves the confidentiality and integrity of the messages with respect to speed and time with lower Bandwidth and also consume a very low computational costs with low power supply and redirect to optimality. Cloud Computing also play’s a significant role to access data at geographically different locations. So In this paper we create a fusion of Computer Networking Architecture and Cloud Computing Architecture and released a very much superior fundamentally strong Cloud computing based Computer Networking model, which works on the concepts of ‘Virtualization’. Because when the number of hardware components (Servers) drastically increases all factors which are responsible to make possible networking among nodes are also consume each resources at extreme level, and networking becomes complex and slow, that’s why we used the concept of Virtual Machine. In this paper we proposed a Computer Networking model using the concepts of Cloud Computing. This model also suitable for data transmission but also take concern the most significant feature of Computer Networking, which is Data Security. This model also used some Proxy servers/ firewalls to take concern some security mechanisms. In this paper we also proposed Communication Oriented model among the Intercluster domains that how one node which belongs to another CLOUD cluster make possible communication among other InterCLOUD clusters with respect to data security measures. In this paper we proposed three models related to this networking model, which is CLOUD Networking Infrastructure, Connection Oriented model, Communication Oriented model. The detailed description of all three models are in the upcoming sections of this paper. Keywords: Cloud computing based computer networking model, A virtual model for computer networking, Computer Networking model based on virtualization, Virtualization based computer networking model.

Purpose This paper aims to solve the web service selection problem using an efficient meta-heuristic algorithm. The problem of selecting a set of web services from a large-scale service environment (web service repository) while maintaining Quality-of-Service (QoS), is referred to as web service selection (WSS). With the explosive growth of internet services, managing and selecting the proper services (or say web service) has become a pertinent research issue. Design/methodology/approach In this paper, to address WSS problem, the authors propose a new modified fruit fly optimization approach, called orthogonal array-based learning in fruit fly optimizer (OL-FOA). In OL-FOA, they adopt a chaotic map to initialize the population; they add the adaptive DE/best/2mutation operator to improve the exploration capability of the fruit fly approach; and finally, to improve the efficiency of the search process (by reducing the search space), the authors use the orthogonal learning mechanism. Findings To test the efficiency of the proposed approach, a test suite of 2500 web services is chosen from the public repository. To establish the competitiveness of the proposed approach, it compared against four other meta-heuristic approaches (including classical as well as state-of-the-art), namely, fruit fly optimization (FOA), differential evolution (DE), modified artificial bee colony algorithm (mABC) and global-best ABC (GABC). The empirical results show that the proposed approach outperforms its counterparts in terms of response time, latency, availability and reliability. Originality/value In this paper, the authors have developed a population-based novel approach (OL-FOA) for the QoS aware web services selection (WSS). To justify the results, the authors compared against four other meta-heuristic approaches (including classical as well as state-of-the-art), namely, fruit fly optimization (FOA), differential evolution (DE), modified artificial bee colony algorithm (mABC) and global-best ABC (GABC) over the four QoS parameter response time, latency, availability and reliability. The authors found that the approach outperforms overall competitive approaches. To satisfy all objective simultaneously, the authors would like to extend this approach in the frame of multi-objective WSS optimization problem. Further, this is declared that this paper is not submitted to any other journal or under review.

This paper presents an approach for development of costeffective custom video / image processing systems. The approach utilizes the concept of temporal partitioning of resources in the partially reconfigurable FPGA devices. Paper proposes architecture of the multi-mode video-stream processor with cyclically reconfigurable structure. The cost-effectiveness of the proposed approach has been analyzed on the basis of experiments conducted on Multi-mode Adaptive Reconfigurable System (MARS) platform that was developed for that purpose. The video-processing cores associated with stereo-vision algorithms have been developed, tested and analyzed. The experiments have shown that the cost-effectiveness of the systems based on proposed approach can be better than the traditional approaches based on large statically configured FPGAs.

Video standards are crucial for exchanging video content, enabling a myriad of services and supporting a wide variety of devices ranging from personal devices to clouds and IoT. One of the core requirements in video standards is the rate control that regulates the bit allocation and picture quality. This paper presents an overview of rate control techniques in the HEVC video coding standard. While providing an insight into the rate control mechanism specific to HEVC, it describes the basic operating principle of rate control algorithms, including their essential parameter, outputs, and performance measures. We review rate control in past coding standards and bring out the basic features of HEVC that drive the need for new rate control algorithms. Alongside, we delineate the Rate-Distortion model-based taxonomy of various algorithms, including their classification criteria. The paper gives out another classification of the rate control algorithms based on their basic principle and mechanisms. The article also explains the scalable extension of HEVC, namely SHVC, while highlighting some of the possible SHVC rate control design challenges. Finally, we present some of the unresolved research issues in HEVC rate control and outline possible future research directions.

With the maturity of the most advanced technology and virtual reality, the application of digital media technology in various fields has become more and more extensive. Digital media technology has greatly promoted the development of all classes of society. Therefore, how to develop digital media technology applications has become a major issue. This article aims to study the digital media application technology of mobile terminals based on edge computing and virtual reality. In this paper, we use edge computing and virtual reality methods to study the digital media application technology of mobile terminals. We used the SD-CEN architecture and FWA in edge computing to conduct simulation experiments and compared the delay time performance of the FWA with that of the PSO-CO algorithm, WRR algorithm, and Pick-KX algorithm. The results of this paper show that it can effectively reduce the response delay of real-time face recognition services and improve user experience. Compared with the traditional cloud computing architecture and a single MEC device, the SD-CEN network architecture based on FWA strategy has more advantages. The latency of the FWA is increased by 61%, 46%, and 17%, respectively, compared with that of the WRR, Pick-KX, and PSO-CO algorithms.

To efficiently deploy machine learning applications to the edge, compute-in-memory (CIM) based hardware accelerator is a promising solution with improved throughput and energy efficiency. Instant-on inference is further enabled by emerging non-volatile memory technologies such as resistive random access memory (RRAM). This paper reviews the recent progresses of the RRAM based CIM accelerator design. First, the multilevel states RRAM characteristics are measured from a test vehicle to examine the key device properties for inference. Second, a benchmark is performed to study the scalability of the RRAM CIM inference engine and the feasibility towards monolithic 3D integration that stacks RRAM arrays on top of advanced logic process node. Third, grand challenges associated with in-situ training are presented. To support accurate and fast in-situ training and enable subsequent inference in an integrated platform, a hybrid precision synapse that combines RRAM with volatile memory (e.g. capacitor) is designed and evaluated at system-level. Prospects and future research needs are discussed.

The domain of engineering has always taken inspiration from the biological world. Understanding the functionalities of the human brain is one of the key areas of interest over time and has caused many advancements in the field of computing systems. The computational capability per unit power per unit volume of the human brain exceeds the current best supercomputers. Mimicking the physics of computations used by the nervous system and the brain can bring a paradigm shift to the computing systems. The concept of bridging computing and neural systems can be termed as neuromorphic computing and it is bringing revolutionary changes in the computing hardware. Neuromorphic computing systems have seen swift progress in the past decades. Many organizations have introduced a variety of designs, implementation methodologies and prototype chips. This paper discusses the parameters that are considered in the advanced neuromorphic computing systems and the tradeoffs between them. There have been attempts made to make computer models of neurons. Advancements in the hardware implementation are fuelling the applications in the field of machine learning. This paper presents the applications of these modern computing systems in Machine Learning.

The increasing maturity of Internet information technology has led to the rapid rise of block-chain technology. In essence, the block-chain is a shared database. In recent years, block-chain technology has attracted the attention of the public and society. This paper mainly conducts systematic research and analysis on the integration and optimization of big data in sports training by block-chain, and achieves large-scale consensus in the case of decentralization, therefore, the information of the network will not be tampered with and forged, thus crossing the boundary of the bottom layer of the information system. This paper is based on the integration and optimization of sports training is big data. With the help of block-chain technology, each module is designed and implemented according to the needs. At the same time, the pow algorithm inside the block-chain is improved. The research results show that it is based on the block-chain. The integration and optimization of technical sports training big data can reduce the number of sports training injuries of sports school students by 10% -20%, which is very conducive to the healthy growth and development of sports school students.

Traffic shaping controls communication traffic flow to prevent a specified communication rate from being exceeded. In conventional networks, the traffic shaping device is implemented at a predetermined location and only a communication flow passing through the device is targeted. If the traffic can be shaped dynamically on any selected communication flows at the optimal point only when necessary, it could use network bandwidths and packet relay processing capacity more efficiently and flexibly. This paper proposes a dynamic shaping method using Software-Defined Networking (SDN) and Network Functions Virtualization (NFV) paradigms, which selects the optimal communication flows to be shaped, and the optimal shaping points dynamically. This paper also presented system configuration and functions for the proposed dynamic shaping, and the method to simplify the process of collecting the traffic data of each communication flow by SDN controller.

With the improvement of software system complexity and frequent updating of user requirements, the requirements of the information software development industry for information construction are constantly improved, and the quality and management requirements of software products researched and developed are also constantly improved. Project managers in the information software development industry gradually realize the importance and necessity of software system deployment. It requires scientific, timely, effective and clear work. Software system deployment system for task division and task monitoring. Based on the research results at home and abroad, this paper studies the deployment of computer software system based on event-driven architecture by using a discrete Fourier transform algorithm, decision tree algorithm and parallel algorithm. By comparing and optimizing the advantages and disadvantages of discrete Fourier transform algorithm, decision tree algorithm and parallel algorithm. This paper studies the unified management, scheduling and allocation of computer software resources. The results show that after using the research model, the data error is controlled within 5%, and the overall data accuracy is improved by 15% compared with the previous methods, which have certain practical value.

In year 2020, a large-scale outbreak of pneumonia caused by new coronavirus has affected the development of many industries and enterprises in China. Under the strong leadership of the Chinese government, the development of the epidemic situation in China has been well controlled. The development of various industries also began to show a good situation, many large-scale sports competitions also need to be restored. In order to ensure the normal development of large-scale sports events, we need to consider the development of epidemic situation to determine the time of sports events. Based on the study of FPGA theory, this paper designs a specific scheme of programming and system debugging, which includes a variety of program operations. In order to better predict the situation of the epidemic situation, this paper also uses the basic knowledge of machine learning to establish a relevant model to evaluate the situation of large-scale sports events under the development of the epidemic situation, and provide feasible suggestions for the recovery of large-scale sports events under the epidemic situation.

Recently, emerging edge computing technology has been proposed as a new paradigm that compensates for the disadvantages of the current cloud computing. In particular, edge computing is used for service applications with low latency while using local data. For this emerging technology, a neural network approach is required to run large-scale machine learning on edge servers. In this paper, we propose a pod allocation method by adding various graphics processing unit (GPU) resources to increase the efficiency of a Kubernetes-based edge server configuration using a GPU-based embedded board and a TensorFlow-based neural network service application. As a result of experiments performed on the proposed edge server, the following are inferred: 1) The bandwidth, according to the time and data size, changes in local (20.4–42.4 Mbps) and Internet environments (6.31–25.5 Mbps) for service applications. 2) When two neural network applications are run on an edge server consisted with Xavier, TX2 and Nano, the network times of the object detection application are from 112.2 ms (Xavier) to 515.8 ms (Nano); the network times of the driver profiling application are from 321.8 ms (Xavier) to 495.7 ms (Nano). 3) The proposed pod allocation method demonstrates better performance than the default pod allocation method. We observe that the number of allocatable pods on three worker nodes increases from five to seven, and compared to other papers, the proposed offloading shows similar or better response times in environments where multiple deep learning applications are implemented.

Automation of Radio Access Network (RAN) operation is a fundamental feature to manage sustainable and efficient Beyond Fifth-generation wireless (5G) networks, in the context of the Next Generation Self-Organizing Network (NG-SON) vision. Machine Learning (ML) is already identified as the key ingredient of this vision, with new standardized and open architectures, like Open-RAN (O-RAN), taking momentum. In this paper, we propose models based on single-task and Multi-Task Learning (MTL) paradigms to address two RAN use cases, handover management and initial Modulation and Coding Scheme (MCS) selection. Traditional handover schemes have the drawback of taking into account the quality of the signals from the serving, and the target cell, before the handover. Also, initial MCS at the start of the session and after a handover usually is handled conservatively. The proposed ML solutions allow to address these drawbacks by 1) considering the expected Quality of Experience (QoE) resulting from the decision of a target cell to handover, as the driving principle of the handover decision and 2) using the experience extracted from network data to make smarter initial MCS allocations. In this line, we implement a realistic cellular simulation scenario by incorporating coverage holes to build an extensive database to train and test the proposed models. The results show that the ML-based models outperform the 3rd Generation Partnership Project (3GPP) standardized handover and initial MCS selection approaches by improving the QoE of users resulting from a handover and the throughput obtained upon establishing a new connection with a network. Besides that, using the obtained results, this paper extensively discusses the merits of leveraging the MTL model to address different, but related multiple RAN functions because it allows reusing a common learning architecture for multiple RAN use cases, which provides significant implementation advantages., This work was supported in part by under Grant PID2020-113832RB-C22 (ORIGIN)/AEI/10.13039/501100011033, and in part by Huawei Technologies, Sweden AB.

The sixth generation (6G) wireless communication network presents itself as a promising technique that can be utilized to provide a fully data-driven network evaluating and optimizing the end-to-end behavior and big volumes of a real-time network within a data rate of Tb/s. In addition, 6G adopts an average of 1000+ massive number of connections per person in one decade (2030 virtually instantaneously). The data-driven network is a novel service paradigm that offers a new application for the future of 6G wireless communication and network architecture. It enables ultra-reliable and low latency communication (URLLC) enhancing information transmission up to around 1 Tb/s data rate while achieving a 0.1 millisecond transmission latency. The main limitation of this technique is the computational power available for distributing with big data and greatly designed artificial neural networks. The work carried out in this paper aims to highlight improvements to the multi-level architecture by enabling artificial intelligence (AI) in URLLC providing a new technique in designing wireless networks. This is done through the application of learning, predicting, and decision-making to manage the stream of individuals trained by big data. The secondary aim of this research paper is to improve a multi-level architecture. This enables user level for device intelligence, cell level for edge intelligence, and cloud intelligence for URLLC. The improvement mainly depends on using the training process in unsupervised learning by developing data-driven resource management. In addition, improving a multi-level architecture for URLLC through deep learning (DL) would facilitate the creation of a data-driven AI system, 6G networks for intelligent devices, and technologies based on an effective learning capability. These investigational problems are essential in addressing the requirements in the creation of future smart networks. Moreover, this work provides further ideas on several research gaps between DL and 6G that are up-to-date unknown.

Nonvolatile memory (NVM)-based computing-in-memory (nvCIM) is a promising candidate for artificial intelligence (AI) edge devices to overcome the latency and energy consumption imposed by the movement of data between memory and processors under the von Neumann architecture. This paper explores the background and basic approaches to nvCIM implementation, including input methodologies, weight formation and placement, and readout and quantization methods. This paper outlines the major challenges in the further development of nvCIM macros and reviews trends in recent silicon-verified devices.

Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer’s overlay is unrealistic and impractical. Hence, wafers are selectively inspected at metrology stations through sampling strategies. With virtual metrology (VM), the metrology quality of the uninspected wafers can be estimated. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a VM to estimate the overlay of the photolithography process is envisioned. Past researches on overlay VM leveraged fault detection and classification (FDC) data to estimate the overlay errors. As such, for fabs in the progress of completing their FDC development for photolithography equipment, a different modeling approach is required to realize an overlay VM that sustains the production line until FDC data can be leveraged for VM. With practical gaps that must be addressed in real fabs, this paper focuses on realizing an overlay VM for the photolithography process without leveraging FDC data. Therefore, the objectives of this paper are two folds: First, to identify the research challenges towards realizing the overlay VM. Second, to propose the future research perspectives of the envisioned overlay VM. Based on the future research perspectives, a two-steps overlay VM modeling approach utilizing data mining techniques is proposed toward realizing the envisioned overlay VM system. The proposed approach first classifies the process stability at the wafer lot level, and subsequently, performs overlay error estimations for wafers in the wafer lots classified with stable process. Linear regression models are proposed to perform overlay error estimations in this work to augment the interpretability of the overlay VM.

International audience; In this paper we give an overview of both hardware and software architectures of real time systems used in devices for various purposes-from lab bench contraptions to cars. The goal of the paper is to reveal separate classes of such architectures as well as to define preconditions for choosing a particular architecture.

False data detection, intrusion detection and coverage rate are major challenges in wireless sensor networks (WSN). Scheduling in media access control (MAC) using gateway and relay nodes solve some of the problems. In this paper, we carried out a brief survey on scheduling, delay aware MAC, cooperative communications in MAC, and adaptive listening to keep controlling the energy in sensors. In addition, multichannel MAC and various routing strategy techniques for WSN are discussed. Firefly algorithm for dynamic scheduling pipelined scheduling for linear sensor networks gives better throughput and latency. Heuristic configuration solves the overhearing problem, as node power-based MAC controls power of each node. Based on WSN applications and the performance metrics concentrated, various techniques for MAC are discussed throughout in this paper.

Under the influence of novel corona virus pneumonia epidemic prevention and control, it has put forward higher requirements for data storage and processing for personnel management system. The distributed asynchronous data aided computer information interaction system can solve the problem of multi node concurrent data processing. The traditional computer information interaction system has poor real-time performance, low precision and asynchronous data processing ability. The invocation features of message queuing asynchronous caching mode are combined with the standardization of Web services and cross language with cross platform access features in this paper. Through the combination of the two technologies, a flexible and universal asynchronous interaction architecture of distributed system is established. Based on Web service technology and system to system access, the call and response of tasks between modules are carried out in the system, which makes the interaction between the whole system have the characteristics of message driven. The test result shows that the system proposed in this paper has good real-time performance and strong data processing ability. It is suitable for the data interaction of distributed personal management system under the influence of novel corona virus pneumonia epidemic prevention and control.

This paper is dealing with the reconfiguration of a flexible real-time Network-on-Chip (NoC) in Multiprocessors System-on-Chip MPSoC architectures. We assume that each NoC’s node is composed of a processor and a router. A processor is assumed to be composed of dependent periodic and aperiodic operating system tasks. The paper addresses low-power adaptations of MPSoC when dynamic reconfigurations of the periodic and aperiodic tasks (sharing resources) are applied at run-time to save or improve the performance. The reconfiguration is defined as any operation allowing the addition-removal-update of periodic dependent OS (Operating System) tasks that share resources. For two added dependent tasks assigned to different processors, a message is added automatically on the NoC. After a such scenario, several real-time constraints may be violated and the power consumption increased.In order to resolve this problem, a new approach CRMPSoC (Abbrev. Cynapsys-Reconfigurable MPSoC) that is composed of two steps is proposed: (1) Applying a reconfiguration: Selection of reconfiguration scenarios, and (2) System Feasibility: A multi-agent architecture based on a master/slave model is defined where a slave agent is assigned to each node to verify the system/bus feasibility, and a master is proposed for the whole architecture if any perturbation occurs at run-time by proposing software or hardware solutions. Since the kernel is not reconfigurable, we develop a new middleware that will support the different steps of our approach. The latter is applied to a real case study for the evaluation of the paper’s contribution.

Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed in order to cope with the requirements of this forthcoming computing target. This paper presents the ExaNoDe H2020 research project aiming to design a highly energy efficient and highly integrated heterogeneous compute node targeting Exascale level computing, mixing low-power processors, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system. This work was supported by the ExaNoDe project that has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 671578. The work presented in this paper reflects only authors’ view and the European Commission is not responsible for any use that may be made of the information it contains.