16,100 results
Search Results
2. CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper)
- Author
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Xinyuan Wang, Xiaoyi Ling, Hsuan Hsiao, Rami Beidas, Omar Ragheb, Tianyi Yu, Vimal Chacko, and Jason H. Anderson
- Subjects
Computer science ,CAD ,Solid modeling ,computer.software_genre ,Software framework ,Application-specific integrated circuit ,Computer architecture ,Systems architecture ,Verilog ,ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS ,Field-programmable gate array ,computer ,computer.programming_language ,Abstraction (linguistics) - Abstract
Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware platforms that can be used to realize application-specific accelerators for higher performance and energy efficiency. A CGRA is a 2D array of configurable logic blocks & interconnect, where the logic blocks are typically large & ALU-like, and the interconnect is word-wide. CGRA-ME is a software framework that enables the modelling and exploration of CGRA architectures, as well as research on CGRA CAD algorithms. With CGRA-ME, an architect can specify a CGRA architecture at a high level of abstraction. A set of applications can be mapped onto the architecture to assess the mappability, power, performance and cost. CGRA-ME also allows one to generate synthesizable Verilog RTL for the modelled CGRA, permitting its implementation as an ASIC or FPGA overlay. In this paper, we describe the CGRA-ME framework [5] and overview its capabilities and current limitations. We discuss ongoing and prior research conducted with the framework, as well as outline future plans. We believe CGRA-ME will be a valuable contribution to the community, enabling new research on CGRA CAD & architectures.
- Published
- 2021
3. Reproducibility Companion Paper: Outfit Compatibility Prediction and Diagnosis with Multi-Layered Comparison Network
- Author
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Wei Hu, Bo Wu, Yueqi Zhong, Jan Zahálka, and Xin Wang
- Subjects
Reproducibility ,Experimental Replication ,Computer architecture ,Computer science ,business.industry ,Deep learning ,Compatibility (mechanics) ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,02 engineering and technology ,Artificial intelligence ,business ,Software package - Abstract
This companion paper supports the experimental replication of paper "Outfit Compatibility Prediction and Diagnosis with Multi-Layered Comparison Network", which is presented at ACM Multimedia 2019. We provide the software package for replicating the implementation of Multi-Layered Comparison Network (MCN), as well as the Polyvore-T dataset and baseline methods compared in the original paper. This paper contains the guides to reproduce the experiment results including outfit compatibility prediction, outfit diagnosis and automatic outfit revision.
- Published
- 2020
4. High performance network components for scalable spaceborne processing needs: Poster, short paper
- Author
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Richard W. Berger and Joseph R. Marshall
- Subjects
Engineering ,Random access memory ,Computer architecture ,business.industry ,Interface (Java) ,Embedded system ,Emphasis (telecommunications) ,Short paper ,Scalability ,Electromagnetic compatibility ,High performance network ,business ,SpaceWire - Abstract
This paper will describe high performance interface building blocks, compare their networking features and show how they may be used in small and large systems especially as they apply to SpaceVPX modules. Emphasis will be placed on their SpaceWire and other networking capabilities.1
- Published
- 2016
5. Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper
- Author
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Chun Zhao, Dustin Richmond, Scott Davidson, Dai Cheol Jung, and Michael Taylor
- Subjects
Standard cell ,Router ,Very-large-scale integration ,Computer science ,Network packet ,Mesh networking ,02 engineering and technology ,021001 nanoscience & nanotechnology ,Chip ,Column (database) ,020202 computer hardware & architecture ,Computer architecture ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Bandwidth (computing) ,0210 nano-technology - Abstract
Network-On-Chip design has been an active area of academic research for two decades, but many proposed ideas have not been adopted in real chips because they have complex behavior or create significant risks in chip implementation. For this reason, many existing chips just employ fast, replicated vanilla dimension-ordered mesh NoCs. However, these networks do not come close to utilizing the full available VLSI wiring capabilities, and propagate packets at speeds that are significantly below the raw speed of wires.The ideal network would not require any custom circuits, and would decompose easily into a hierarchical CAD flow consisting of a top-level design instantiating a mesh of identical hardened tiles with short-wire neighbor connections.At the same time, this ideal network would easily scale to efficiently utilize the majority of the available chip wiring resources, and would offer a mechanism for scaling this wire usage up or down based on available bandwidth. Packets would spend a significant fraction of their time in wire delay rather than router delay. Finally, the NoC would be simple to understand.This paper proposes Ruche Networks, which fulfill these requirements. They are based on simple 2-D mesh networks but amplify the NoC bandwidth and reduce NoC diameter of tiled architectures by adding long-range physical channels from each tile to other tiles on the same row or column. The more distant the connections, the greater the bandwidth of the network and the lower the diameter. The distance is typically increased until all of the physical VLSI wiring bandwidth have been absorbed.We explain the rational for this "ruching" and provide a simple methodology for designing and implementing these networks using a standard cell VLSI CAD flow.In this paper, we show the steps involved in ruching the HammerBlade Manycore’s mesh networks; these steps can easily apply to other designs.
- Published
- 2020
6. Ascend: a Scalable and Unified Architecture for Ubiquitous Deep Neural Network Computing : Industry Track Paper
- Author
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Yuxing Hu, Jing Xia, Hu Liu, Xiping Zhou, Jiajin Tu, Honghui Yuan, and Heng Liao
- Subjects
Memory hierarchy ,business.industry ,Computer science ,020208 electrical & electronic engineering ,Symmetric multiprocessor system ,02 engineering and technology ,Data access ,Memory management ,Computer architecture ,Datapath ,Scalability ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,Data center ,business ,Heterogeneous network - Abstract
Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center. In order to improve the efficiency of processing these DNN models, dedicated hardware accelerators are required for all these scenarios. Theoretically, there exists an optimized acceleration architecture for each application. However, considering the cost of chip design and corresponding tool-chain development, researchers need to trade off between efficiency and generality. In this work, we demonstrate that it is practical to use a unified architecture, called Ascend, to support those applications, ranging from IoT devices to data-center services. We provide a lot of design details to explain that the success of Ascend relies on contributions from different levels. First, heterogeneous computing units are employed to support various DNN models. And the datapath is adapted according to the requirement of computing and data access. Second, when scaling the Ascend architecture from a single core to a cluster containing thousands of cores, it involves design efforts, such as memory hierarchy and system level integration. Third, a multi-tier compiler, which provides flexible choices for developers, is the last critical piece. Experimental results show that using accelerators based on the Ascend architecture can achieve comparable or even better performance in different applications. In addition, various chips based on the Ascend architecture have been successfully commercialized. More than 100 million chips have been used in real products.
- Published
- 2021
7. AWD: Best Paper Competition (AWD) Enabling Next Generation Video Applications on Consumer Integrated and Discrete Client GPUs
- Author
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Jill Macdonald Boyce and Basel Salahieh
- Subjects
Competition (economics) ,Computer architecture ,Computer science ,Encoding (memory) ,Codec ,Content adaptive ,Graphics ,Implementation ,Transform coding ,Power optimization - Abstract
This "success story" panel illustrates how next generation video applications are enabled on PCs today using consumer integrated and discrete GPUs launched in 2020. Intel's XeLP graphics technology with dedicated media hardware powers the integrated graphics in Intel's latest client processor, Tiger Lake, and Intel's first entry-level mainstream discrete graphics card, DG1. XeLP graphics in Tiger Lake and DG1 has democratized access to high performance implementations of the latest emerging video codec standards. Three topics will be covered: (i) 8K HEVC/AV1 Playback with Content Adaptive Power Optimization; (ii) Ludicrous Speed HEVC Encoding with Integrated + Discrete GPU; and (iii) MPEG Immersive Video (MIV) Playback on DG1.
- Published
- 2021
8. MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper
- Author
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Mingjie Liu, Nan Sun, David Z. Pan, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, and Yibo Lin
- Subjects
Heuristic (computer science) ,business.industry ,Computer science ,020208 electrical & electronic engineering ,Constraint (computer-aided design) ,02 engineering and technology ,Integrated circuit design ,Integrated circuit layout ,Automation ,020202 computer hardware & architecture ,Computer architecture ,Fully automated ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Netlist ,Routing (electronic design automation) ,business - Abstract
Despite tremendous advancement of digital IC design automation tools over the last few decades, analog IC layout is still heavily manual which is very tedious and error-prone. This paper will first review the history, challenges, and current status of analog IC layout automation. Then, we will present MAGICAL, a human-intelligence inspired, fully-automated analog IC layout system currently being developed under the DARPA IDEA program. It starts from an unannotated netlist, performs automatic layout constraint extraction and device generation, then performs placement and post-placement optimization, followed by routing to obtain the final GDSII layout. Various analytical, heuristic, and machine learning algorithms will be discussed. MAGICAL has obtained promising preliminary results. We will conclude the paper with further discussions on challenges and future directions for fully-automated analog IC layout.
- Published
- 2019
9. Wavelength-Routed Optical NoCs: Design and EDA — State of the Art and Future Directions: Invited Paper
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Ulf Schlichtmann, Alexandre Truppel, Mengchu Li, Mahdi Nikdast, and Tsun-Ming Tseng
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Range (mathematics) ,Computer architecture ,Computer science ,020208 electrical & electronic engineering ,Scalability ,0202 electrical engineering, electronic engineering, information engineering ,Electronic design automation ,02 engineering and technology ,State (computer science) ,Routing (electronic design automation) ,Component placement ,Waveguide (optics) ,020202 computer hardware & architecture - Abstract
Wavelength-routed optical network-on-chip (WRONoC) design consists of topological and physical synthesis. It covers many interacting design aspects such as wavelength assignment, message routing, network construction, component placement, and waveguide routing. Due to the high complexity of the design problem, current manual design usually trades optimality for scalability and feasibility, which results in performance degradation and waste of resources. In this paper, we will present an overview of the existing design automation approaches that have demonstrated their effectiveness in customizing and optimizing application-specific WRONoC designs, and of the potential design automation directions to address a wider range of design challenges. We will also discuss the advantages of comprehensive optimization considering multiple design aspects simultaneously, and the possible barriers that need to be removed to achieve this goal.
- Published
- 2019
10. Deep neural networks compiler for a trace-based accelerator (short WIP paper)
- Author
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Aliasger Zaidy, Eugenio Culurciello, Lukasz Burzawa, and Andre Xian Ming Chang
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020203 distributed computing ,business.industry ,Computer science ,Dataflow ,Deep learning ,Image processing ,Memory bandwidth ,02 engineering and technology ,010501 environmental sciences ,computer.software_genre ,01 natural sciences ,Computer Graphics and Computer-Aided Design ,Computer architecture ,0202 electrical engineering, electronic engineering, information engineering ,Deep neural networks ,Artificial intelligence ,Compiler ,business ,Field-programmable gate array ,computer ,Software ,0105 earth and related environmental sciences ,TRACE (psycholinguistics) - Abstract
Deep Neural Networks (DNNs) are the algorithm of choice for image processing applications. DNNs present highly parallel workloads that lead to the emergence of custom hardware accelerators. Deep Learning (DL) models specialized in different tasks require a programmable custom hardware and a compiler/mapper to efficiently translate different DNNs into an efficient dataflow in the accelerator. The goal of this paper is to present a compiler for running DNNs on Snowflake, which is a programmable hardware accelerator that targets DNNs. The compiler correctly generates instructions for various DL models: AlexNet, VGG, ResNet and LightCNN9. Snowflake, with a varying number of processing units, was implemented on FPGA to measure the compiler and Snowflake performance properties upon scaling up. The system achieves 70 frames/s and 4.5 GB/s of off-chip memory bandwidth for AlexNet without linear layers on Xilinx’s Zynq-SoC XC7Z045 FPGA.
- Published
- 2018
11. HPDM: A Survey Paper
- Author
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Li Wang
- Subjects
MIMD ,Focus (computing) ,Computer architecture ,Shared memory ,Workstation ,law ,Computer science ,Carry (arithmetic) ,Component (UML) ,Parallelism (grammar) ,SIMD ,law.invention - Abstract
This survey reviews several approaches of HPDM from many research groups world wide. Modern computer hardware supports the development of high-performance applications for data analysis on many different levels. The focus is on modern multi-core processors built into today's commodity computers, which are typically found at university institutes both as small server and workstation computers. So they are deliberately not high-performance computers. Modern multi-core processors consist of several (2 to over 100) computer cores, which work independently of each other according to the principle of "multiple instruction multiple data'' (MIMD). They have a common main memory (shared memory). Each of these computer cores has several (2-16) arithmetic-logic units, which can simultaneously carry out the same arithmetic operation on several data in a vector-like manner (single instruction multiple data, SIMD). HPDM algorithms must use both types of parallelism (SIMD and MIMD), with access to the main memory (centralized component) being the main barrier to increased efficiency.
- Published
- 2020
12. LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper
- Author
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Pierre-Emmanuel Gaillardon, Luca Amaru, Max Austin, Scott Temple, Xifan Tang, and Walter Lau Neto
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Standard cell ,Computer science ,Context (language use) ,02 engineering and technology ,Integrated circuit ,020202 computer hardware & architecture ,law.invention ,Logic synthesis ,Computer architecture ,Application-specific integrated circuit ,law ,0202 electrical engineering, electronic engineering, information engineering ,Graph (abstract data type) ,020201 artificial intelligence & image processing ,Electronic design automation ,Hardware_LOGICDESIGN ,Electronic circuit - Abstract
The increasing complexity of modern Integrated Circuits (ICs) leads to systems composed of various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such complexity requires strong expertise from engineers, that rely on expansive commercial EDA tools. To overcome such a limitation, an automated open-source logic synthesis flow is required. In this context, this work proposes LSOracle: a novel automated mixed logic synthesis framework. LSOracle is the first to exploit state-of-the-art And-Inverter Graph (AIG) and Majority-Inverter Graph (MIG) logic optimizers and relies on a Deep Neural Network (DNN) to automatically decide which optimizer should handle different portions of the circuit. To do so, LSOracle applies $k-way$ partitioning to split a DAG into multiple partitions and uses a to chose the best-fit optimizer. Post-tech mapping ASIC results, targeting the 7nm ASAP standard cell library, for a set of mixed-logic circuits, show an average improvement in area-delay product of 6.87% (up to 10.26%) and 2.70% (up to 6.27%) when compared to AIG and MIG, respectively. In addition, we show that for the considered circuits, LSOracle achieves an area close to AIGs (which delivered smaller circuits) with a similar performance of MIGs, which delivered faster circuits.
- Published
- 2019
13. Ultra-Low Power and Minimal Design Effort Interfaces for the Internet of Things: Invited paper
- Author
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Orazio Aiello, Paolo Stefano Crovetti, and Massimo Alioto
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Ultra low power ,Computer science ,business.industry ,020208 electrical & electronic engineering ,Design flow ,Digital-to-analog converter ,Reconfigurability ,020206 networking & telecommunications ,02 engineering and technology ,law.invention ,Software portability ,Computer architecture ,law ,Scalability ,0202 electrical engineering, electronic engineering, information engineering ,Internet of Things ,business - Abstract
This paper reviews the results of recent researches aimed to extend the standard-cell based digital design flow to analog building blocks, so that to enhance scalability, reconfigurability and portability across technology nodes and to reduce design effort, time-to-market and costs. In this framework, the application of the proposed fully digital design approach to a wake up oscillator and to a Digital-to-Analog Converter, which are two building blocks widely employed in IoT sensor nodes, is illustrated in detail.
- Published
- 2019
14. Short Paper: Neuromorphic Chip Embedded Electronic Systems to Expand Artificial Intelligence
- Author
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Hamid Abdi and Lahiru L. Abeysekara
- Subjects
medicine.anatomical_structure ,Neuromorphic engineering ,Artificial neural network ,Application-specific integrated circuit ,Computer architecture ,Computer science ,medicine ,Human brain ,Applications of artificial intelligence ,Electronics ,Electronic hardware ,Chip - Abstract
Neuromorphic chips are electronic hardware mimicking neurons in human brain in an electronic structure. These ASICs (Application Specific Integrated Circuits) provide artificial neural networks with computational power comparatively higher than most neural networks generated by software algorithms. 'CM1K' is an electronic chip in this family of products. It has a parallel neural network of 1024 neurons. These neurons provide K-Nearest Neighbor (KNN) data classification. The chip requires to be embedded in an electronic system to access all its capabilities. This paper deliver a novel hardware system embedding CM1K neuromorphic chip. The system was implemented in image and video frame analysis for evaluation. The results prove that the system could benefit various applications including security, asset management, home appliances, mail sorting and manufacturing. Since the embedded system provide opportunity to integrate AI in to simple electronics, it helps on extending AI applications.
- Published
- 2019
15. Exploiting reconfigurable computing in 5G: a case study of latency critical function: Invited Paper
- Author
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Piero Castoldi, F. Civerchia, Maxime Pelcat, Luca Valcarenghi, Scuola Universitaria Superiore Sant'Anna [Pisa] (SSSUP), Institut d'Electronique et de Télécommunications de Rennes (IETR), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Institut Pascal - Clermont Auvergne (IP), Sigma CLERMONT (Sigma CLERMONT)-Centre National de la Recherche Scientifique (CNRS)-Université Clermont Auvergne (UCA), Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Nantes Université (NU)-Université de Rennes 1 (UR1)
- Subjects
OpenCL ,business.industry ,Orthogonal frequency-division multiplexing ,Computer science ,Hardware Acceleration ,030204 cardiovascular system & hematology ,Reconfigurable computing ,[SPI]Engineering Sciences [physics] ,03 medical and health sciences ,0302 clinical medicine ,Software ,Computer architecture ,Reconfigurable Computing ,Hardware acceleration ,030212 general & internal medicine ,Mobile telephony ,Latency (engineering) ,business ,Field-programmable gate array ,[SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing ,5G ,ComputingMilieux_MISCELLANEOUS - Abstract
The fifth generation of mobile communications (5G) is expected to dramatically improve performance compared to preceding standards by offering very high bandwidths and low latencies. To provide this performance, heavy processing is required and must meet strong timing constraints. Reconfigurable computing, managing processing in software and exploiting reconfigurable hardware acceleration, is an innovative approach that should be considered for 5G for its capacity to combine high throughput and high flexibility. This paper presents a case study for Orthogonal Frequency Division Multiplexing (OFDM) computation reconfigurable offloading onto an Field Programmable Gate Array (FPGA). The implementation is based on Open Computing Language (OpenCL) that represents a versatile solution, as this language can be compiled for several architectures, provided that a Host+Accelerator structure is used. The objective of our study is to demonstrate that, by means of hardware offloading, the 5G architecture resources can reach high computational load, avoiding processing stalls and latency increase. Results show that around 15% of the software processing can be freed through hardware acceleration and reallocated to support other tasks.
- Published
- 2019
16. Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper)
- Author
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Bon Woong Ku, Sung Kyu Lim, Kyungwook Chang, and Saurabh Sinha
- Subjects
Computer architecture ,Computer science ,020208 electrical & electronic engineering ,0202 electrical engineering, electronic engineering, information engineering ,Key (cryptography) ,Power performance ,Process design ,Node (circuits) ,02 engineering and technology ,Chip ,3d ic design ,020202 computer hardware & architecture - Abstract
In this paper, we present full-chip designs and their power, performance, and area (PPA) metrics using the ASAP7 process design kit (PDK) and library. Reliable cell library is a key element in evaluating new technological options such as monolithic 3D (M3D) ICs. Given an RTL, we conduct synthesis and place/route to obtain commercial-quality 2D and M3D IC designs and compare PPA. The ASAP7 library is highly useful to build high-quality designs that accurately reflect 7nm technology node. In addition, the full front-end and back-end access provided in ASAP7 allows us to see the impact of various device and interconnect parameters at the full-chip level for both 2D and monolithic 3D ICs. This work demonstrates the critical role of an academic PDK and library in enabling high-quality research in disruptive technologies such as M3D integration.
- Published
- 2017
17. ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper
- Author
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Vinay Vashishtha, Manoj Vangala, and Lawrence T. Clark
- Subjects
010302 applied physics ,Standard cell ,Computer science ,Extreme ultraviolet lithography ,Process design ,01 natural sciences ,010309 optics ,Computer architecture ,0103 physical sciences ,Parasitic extraction ,Place and route ,Physical design ,Routing (electronic design automation) ,Lithography - Abstract
This work discusses the ASAP7 predictive process design kit (PDK) and associated standard cell library. The necessity for multi-patterning (MP) techniques at advanced nodes results in the standard cell and SRAM architecture becoming entangled with design rules, mandating design-technology co-optimization (DTCO). This paper discusses the DTCO process involving standard cell physical design. An assumption of extreme ultraviolet (EUV) lithography availability in the PDK allows bi-directional M1 geometries that are difficult with MP. Routing and power distribution schemes for self-aligned quadruple patterning (SAQP) friendly, high density standard cell based blocks are shown. Restrictive design rules are required and supported by the automated place and route (APR) setup. Supporting sub-20 nm dimensions with academic tool licenses is described. The APR (QRC techfile) extraction shows high correlation with the Calibre extraction deck. Finally, use of the PDK for academic coursework and research is discussed.
- Published
- 2017
18. Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)
- Author
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Andrew Evans, Brian Cline, Xiaoqing Xu, Saurabh Sinha, Greg Yeric, and Nishi Shah
- Subjects
Standard cell ,Computer science ,Transistor ,Process design ,02 engineering and technology ,Integrated circuit ,021001 nanoscience & nanotechnology ,020202 computer hardware & architecture ,law.invention ,Computer architecture ,law ,0202 electrical engineering, electronic engineering, information engineering ,Key (cryptography) ,Node (circuits) ,0210 nano-technology ,Design methods - Abstract
Standard cell libraries are the foundation for the entire back-end design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and beyond, standard cell library design and optimization is becoming increasingly difficult due to extremely complex design constraints, as described in the ASAP7 process design kit (PDK). Notable complexities include discrete transistor sizing due to FinFETs, complicated design rules from lithography and restrictive layout space from modern standard cell architectures. The design methodology presented in this paper enables efficient and high-quality standard cell library design and optimization with the ASAP7 PDK. The key techniques include exhaustive transistor sizing for cell timing optimization, transistor placement with generalized Euler paths and back-end design prototyping for library-level explorations.
- Published
- 2017
19. Multi-broker based software-defined optical networks (Invited paper)
- Author
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Xiaoliang Chen, Andrea Castro, Roberto Proietti, S.J.B. Yoo, and Zuqing Zhu
- Subjects
Network control ,business.industry ,Computer science ,Quality of service ,Topology (electrical circuits) ,02 engineering and technology ,Blocking (statistics) ,Service provisioning ,Reduction (complexity) ,020210 optoelectronics & photonics ,Software ,Computer architecture ,Scalability ,0202 electrical engineering, electronic engineering, information engineering ,business - Abstract
This paper investigates the multi-broker based network control and management paradigm for realizing scalable and cost-effective service provisioning in multi-domain software-defined optical networks. Experimental results verify the feasibility of the proposal and demonstrate ∼ 7.6× blocking reduction comparing with the conventional single-broker based solution.
- Published
- 2017
20. Generating FPGA-based image processing accelerators with Hipacc: (Invited paper)
- Author
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Richard Membarth, Oliver Reiche, Jürgen Teich, Frank Hannig, and M. Akif Ozkan
- Subjects
020203 distributed computing ,Source code ,Computer science ,media_common.quotation_subject ,Image processing ,02 engineering and technology ,computer.software_genre ,020202 computer hardware & architecture ,Domain (software engineering) ,Digital subscriber line ,Computer architecture ,0202 electrical engineering, electronic engineering, information engineering ,Compiler ,Field-programmable gate array ,computer ,media_common ,Abstraction (linguistics) - Abstract
Domain-Specific Languages (DSLs) provide a high-level and domain-specific abstraction to describe algorithms within a certain domain concisely. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs are becoming another attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGA have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.
- Published
- 2017
21. 2017 International Symposium on Computer Architecture Influential Paper Award
- Author
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David Brooks
- Subjects
Hardware_MEMORYSTRUCTURES ,Computer architecture ,Hardware and Architecture ,Computer science ,Hardware_INTEGRATEDCIRCUITS ,Hardware_PERFORMANCEANDRELIABILITY ,Electrical and Electronic Engineering ,Software ,Hardware_LOGICDESIGN - Abstract
This article discusses the 2017 ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award, which was given to the 2002 ISCA paper, “Drowsy Caches: Simple Techniques for Reducing Leakage Power.”
- Published
- 2017
22. 4.2: Invited Paper: OLCD: a low cost, area‐scalable manufacturing process for flexible displays
- Author
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Paul Cain
- Subjects
Computer architecture ,Manufacturing process ,Flexible display ,Computer science ,Scalability - Published
- 2019
23. 2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar
- Author
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Dean M. Tullsen and Stephen W. Keckler
- Subjects
Computer architecture ,Hardware and Architecture ,Computer science ,Electrical and Electronic Engineering ,ComputingMilieux_MISCELLANEOUS ,GeneralLiterature_MISCELLANEOUS ,Software - Abstract
This column discusses two awards given in 2014: the International Symposium on Computer Architecture Influential Paper Award, which was given to the authors of the paper "PipeRench: A Coprocessor for Streaming Multimedia Acceleration," and the Maurice Wilkes Award, which was given to Ravi Rajwar.
- Published
- 2014
24. Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper)
- Author
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Kaushik Roy, Aayush Ankit, and Abhronil Sengupta
- Subjects
010302 applied physics ,Spiking neural network ,Network complexity ,Speedup ,Artificial neural network ,Computer science ,business.industry ,Node (networking) ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Bottleneck ,Synapse ,Computer architecture ,Embedded system ,0103 physical sciences ,Benchmark (computing) ,Crossbar switch ,0210 nano-technology ,business - Abstract
Spiking Neural Network based brain-inspired computing paradigms are becoming increasingly popular tools for various cognitive tasks. The sparse event-driven processing capability enabled by such networks can be potentially appealing for implementation of low-power neural computing platforms. However, the parallel and memory-intensive computations involved in such algorithms is in complete contrast to the sequential fetch, decode, execute cycles of conventional von-Neumann processors. Recent proposals have investigated the design of spintronic “in-memory” crossbar based computing architectures driving “spin neurons” that can potentially alleviate the memory-access bottleneck of CMOS based systems and simultaneously offer the prospect of low-power inner product computations. In this article, we perform a rigorous system-level simulation study of such All-Spin Spiking Neural Networks on a benchmark suite of 6 recognition problems ranging in network complexity from 10k–7.4M synapses and 195–9.2k neurons. System level simulations indicate that the proposed spintronic architecture can potentially achieve ∼1292× energy efficiency and ∼ 235× speedup on average over the benchmark suite in comparison to an optimized CMOS implementation at 45nm technology node.
- Published
- 2017
25. A PAPER SURVEY ON THE IMPLEMENTATION OF THE PARALLEL FDTD ON MULTIPROCESSORS USING MPI
- Author
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Oyku Akaydin, Adamu Abubakar Isah, and Mehmet Kusaf
- Subjects
Computer architecture ,Computer science ,Interface (computing) ,010401 analytical chemistry ,0202 electrical engineering, electronic engineering, information engineering ,Local area network ,Finite-difference time-domain method ,020206 networking & telecommunications ,02 engineering and technology ,General Medicine ,Parallel computing ,01 natural sciences ,0104 chemical sciences - Abstract
The research work explains a cost-effective, highperformance computing platform for the parallel implementation of the FDTD algorithm on PC clusters using the message-passing interface (MPI) library, which is a local area network system consisting of multiple interconnected personal computers (PCs), and is already widely employed for parallel computing.
- Published
- 2017
26. Hybrid large-area systems and their interconnection backbone (invited paper)
- Author
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Warren Rieutort-Louis, Yu Hen Hu, Josue Sanz-Robinson, Naveen Verma, Tiffany Moy, Liechao Huang, Yasmin Afsar, Sigurd Wagner, Levent E. Aygun, and James C. Sturm
- Subjects
010302 applied physics ,Interconnection ,business.industry ,Computer science ,020208 electrical & electronic engineering ,02 engineering and technology ,Integrated circuit ,Modular design ,01 natural sciences ,law.invention ,CMOS ,Computer architecture ,law ,Hybrid system ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Electronics ,Telecommunications ,business - Abstract
Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various system functionalities (sensing, processing, powering), specific approaches are surveyed and analyzed, taking from insights derived from several previous experimental demonstrations of complete hybrid systems.
- Published
- 2016
27. Hardware optimizations for crypto implementations (Invited paper)
- Author
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Sandeep K. Shukla and M. Mohamed Asan Basiri
- Subjects
Very-large-scale integration ,Cryptographic primitive ,Computer science ,business.industry ,020208 electrical & electronic engineering ,02 engineering and technology ,Fault injection ,Encryption ,Multiplexing ,Multiplexer ,020202 computer hardware & architecture ,Computer architecture ,Embedded system ,0202 electrical engineering, electronic engineering, information engineering ,Side channel attack ,Elliptic curve cryptography ,business ,Computer hardware - Abstract
Latency, Area, and Power are three important metrics that a VLSI designer wants to optimize. However, often one of these may have to be optimized at the cost of another or the other two. Depending on the application scenario, choice of the metric to optimize is made. In this paper, we consider hardware implementations of a number of cryptographic primitives and present a number of optimizations. We consider three areas of cryptoengineering. They are building physical unclonable functions (PUFs), implementing encryption/decryption algorithms, and side channel proof crypto implementations. The techniques we employ range from area optimization through customized multiplexer design, fusing multiple operations into a single hardware element, folding and unrolling of iterative algorithms, creating reconfigurable implementations to achieve multiple operations with the same set of hardware elements, to techniques of obfuscation to defeat fault injection based attacks on the crypto implementation. All the proposed and existing designs are implemented with 45 nm CMOS library.
- Published
- 2016
28. Fast development of source-level debugging system using hardware emulation (short paper)
- Author
-
Yeon-Ho Im, Byoung-Woon Kim, Junhee Lee, Chong-Min Kyung, Kyong-Gu Kang, Young-Su Kwon, and Sang-Joon Nam
- Subjects
Background debug mode interface ,Computer science ,business.industry ,Semulation ,media_common.quotation_subject ,Short paper ,Source level ,Hardware emulation ,Development (topology) ,Debugging ,Computer architecture ,Embedded system ,business ,media_common - Published
- 2000
29. Resistive non-volatile memory devices (Invited Paper)
- Author
-
Rainer Waser
- Subjects
Resistive touchscreen ,Hardware_MEMORYSTRUCTURES ,Materials science ,Integrated circuit ,Condensed Matter Physics ,Atomic and Molecular Physics, and Optics ,Sketch ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,law.invention ,Non-volatile memory ,Computer architecture ,Nanoelectronics ,law ,Resistive switching ,Scalability ,Electrical and Electronic Engineering - Abstract
The review provides a survey of non-volatile, highly scalable memory devices which are based on redox phenomena controlling the resistance of nanoscale memory cells. The classification of the memory effects, the understanding of the underlying mechanisms, and a sketch of the integration efforts will be presented.
- Published
- 2009
30. Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper)
- Author
-
Mengjie Mao, Qing Wu, Yi Chen, Xiaoxiao Liu, Hai Li, and Mark Bamell
- Subjects
Speedup ,Artificial neural network ,business.industry ,Computer science ,Symmetric multiprocessor system ,Memristor ,law.invention ,symbols.namesake ,Neuromorphic engineering ,Computer architecture ,law ,Embedded system ,Scalability ,symbols ,Unconventional computing ,business ,Von Neumann architecture - Abstract
The explosion of big data applications imposes severe challenges of data processing speed and scalability on traditional computer systems. However, the performance of the von Neumann machine is greatly hindered by the increasing performance gap between CPU and memory, motivating the active research on new or alternative computing architectures. As one important instance, neuromorphic computing systems inspired by the working mechanism of human brains have gained considerable attention. In this work, we propose a heterogeneous computing system with neuromorphic computing accelerators (NCAs) that are built with emerging memristor technology. In the proposed system, NCA is designed to speed up the artificial neural network (ANN) executions in many high-performance applications by leveraging the extremely efficient mixed-signal computation capability of nanoscale memristor-based crossbar (MBC) arrays. The hierarchical MBC arrays of the NCA can be flexibly configured to different ANN topologies through the help of an analog Network-on-Chip (A-NoC). A general approach which translates the target codes within a program to the corresponding NCA instructions is also developed to facilitate the utilization of the NCA. Our simulation results show that compared to the baseline general purpose processor, the proposed heterogeneous system can achieve on average 18.2x performance speedup and 20.1x energy reduction over nine representative applications while constraining the computation accuracy degradation within an acceptable range.
- Published
- 2014
31. Process technology implications for FPGAs (Invited Paper)
- Author
-
Jeffery Chromczak and David Lewis
- Subjects
Engineering ,Reliability (semiconductor) ,Computer architecture ,business.industry ,law ,Transistor ,Electronic engineering ,Process (computing) ,Network routing ,Routing (electronic design automation) ,Field-programmable gate array ,business ,law.invention - Abstract
This paper presents aspects of process technology applicable to FPGAs. Overdrive of transistors for routing pass gates is an important performance and reliability factor. Random variation effects are significant for small arrays of configuration RAM, but small impact on performance. We discuss challenges for CRAM and switch replacement using novel technologies.
- Published
- 2012
32. A BIBLIOGRAPHY OF PUBLISHED PAPERS ON DYNAMICALLY RECONFIGURABLE ARCHITECTURES
- Author
-
Koji Nakano
- Subjects
Reconfigurable mesh ,Computer architecture ,Hardware and Architecture ,Computer science ,Computation ,Bibliography ,Parallel algorithm ,Parallel computer architecture ,Parallel computing ,Architecture ,Software ,Theoretical Computer Science - Abstract
A dynamically reconfigurable architecture is a parallel computer architecture that supports a physical switching of communication patterns during a computation. Basically, the dynamically reconfigurable architecture consists of locally controllable switches, which enables flexible-connection patterns of the network. The bibliography attempts to classify published papers on dynamically reconfigurable architectures according to the problems that are dealt with.
- Published
- 1995
33. Adaptive processor architecture - invited paper
- Author
-
Jürgen Becker, Michael Huebner, Carsten Tradowsky, Joerg Henkel, and Diana Goehringer
- Subjects
Group method of data handling ,business.industry ,Computer science ,media_common.quotation_subject ,Application-specific instruction-set processor ,Information processor ,Microarchitecture ,Computer architecture ,General purpose ,Embedded system ,Quality (business) ,Architecture ,Field-programmable gate array ,business ,media_common - Abstract
This paper introduces a novel methodology to adapt the microarchitecture of a processor at run-time. The goal is to tailor the internal architecture to the requirements of an application and the data to be processed. The latter parameter is normally not known at design time. This leads to the development of more general purpose processors which are capable to handle the data to be processed in any case. With the novel approach which keeps the microarchitecture of a processor flexible, the processor can start as a general purpose device and end up with a specific parameterization, comparable with application specific processor architectures. Furthermore, the increased degree of freedom which is enabled through the approach for a novel quality of processors is described.
- Published
- 2012
34. A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)
- Author
-
Tomohiro Yoneda, Naohiro Hamada, H. Saito, Takashi Nanya, Chris J. Myers, and Yuki Shiga
- Subjects
Computer architecture ,Asynchronous communication ,Computer science ,Informatics ,Signal synthesis ,Network synthesis filters ,Resource management (computing) ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION ,Behavioral synthesis ,Space exploration ,Hardware_LOGICDESIGN ,Electronic circuit - Abstract
This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.
- Published
- 2008
35. An H.264/AVC to SVC TemporalTranscoder in Baseline profile digest of technical papers
- Author
-
Antonio Garrido, Rosario Garrido-Cantos, Pedro Cuenca, Sebastiaan Van Leuven, José Luis Martínez, Jan De Cock, and Rik Van de Walle
- Subjects
Technology and Engineering ,computational complexity ,H.264/AVC bitstream ,coding complexity ,Computer science ,scalable video coding ,baseline profile digest ,Real-time computing ,Data_CODINGANDINFORMATIONTHEORY ,Coding tree unit ,video coding ,Scalable Video Coding ,SVC temporaltranscoder ,Computer architecture ,encoded bitstream ,Bitstream format ,Bitstream ,Context-adaptive binary arithmetic coding ,Context-adaptive variable-length coding - Abstract
Scalable Video Coding provides temporal, spatial and quality scalability using layers within the encoded bitstream. This feature allows the encoded bitstream to be adapted to different devices and heterogeneous networks. This paper proposes a technique to convert an H.264/AVC bitstream in Baseline profile to a scalable stream which provides temporal scalability. Applying the presented approach, a reduction of 65% of coding complexity is achieved while maintaining the coding efficiency.
- Published
- 2011
36. Session details: Paper - architecture and hardware
- Author
-
Timothy Daryl Stanley
- Subjects
Computer architecture ,Computer science ,Session (computer science) ,Architecture - Published
- 2013
37. Tutorial paper: Parallel architectures for model predictive control
- Author
-
George A. Constantinides
- Subjects
Digital electronics ,Model predictive control ,Computer architecture ,Parallel processing (DSP implementation) ,Computer engineering ,Computer science ,Control theory ,business.industry ,Gate array ,Computation ,Graphics ,Field-programmable gate array ,business - Abstract
This tutorial paper surveys recent developments in parallel computer architecture, focusing on the field-programmable gate array and the graphics processor. We aim to illustrate the potential of these architectures for the type of high-speed numerical computation required in on-line optimization for model predictive control. While significant performance advantages can be gained by migrating existing control algorithms to these processor architectures, in order to realise their full potential, further research is needed at the boundary of control theory, digital electronics, and computer architecture. We survey some of the open questions in this area.
- Published
- 2009
38. A Biochemically-Engineered Molecular Communication System (Invited Paper)
- Author
-
Satoshi Hiyama, Yuki Moritani, and Tatsuya Suda
- Subjects
Engineering ,Molecular communication ,Computer architecture ,business.industry ,Interface (computing) ,Key (cryptography) ,Systems design ,Communication source ,business ,Simulation ,Short distance - Abstract
Molecular communication uses molecules (i.e., chemical signals) as an information carrier and allows biologically- and artificially-created nano- or cell-scale entities to communicate over a short distance. It is a new communication paradigm and is different from the traditional communication paradigm that uses electromagnetic waves (i.e., electronic and optical signals) as an information carrier. Key research challenges in molecular communication include design of a sender, design of a molecular propagation system, design of a receiver, design of a molecular communication interface, and mathematical modeling of molecular communication components and systems. This paper focuses on system design and experimental results of molecular communication and briefly refers to recent activities in molecular communication.
- Published
- 2009
39. An FPGA Implementation of Dirty Paper Precoder
- Author
-
Zixiang Xiong, Momin Uppal, Weihuang Wang, P. Bhagawat, Gwan Choi, A. Harris, and Mark Yeary
- Subjects
Virtex ,Digital subscriber line ,Computer architecture ,Computer science ,Real-time computing ,Code (cryptography) ,Codec ,Data_CODINGANDINFORMATIONTHEORY ,Trellis (graph) ,Field-programmable gate array ,Telecommunications network ,Realization (systems) ,Communication channel - Abstract
Dirty paper code (DPC) can be used in a number of communication network applications; broadcast channels, multiuser interference channels and ISI channels to name a few. We study various implementation bottlenecks and issues with implementing a DPC pre-coder based on nested trellis technique. The aim is to achieve a practical hardware realization of the precoder for wireless LAN/DSL applications. We describe the architectural development process and realization of the precoder on a Xilinx Virtex 2V8000 FPGA. To the best of our knowledge this is the first reported DPC pre-coder hardware implementation.
- Published
- 2007
40. Invited Paper: A Compile-time Cost Model for OpenMP
- Author
-
Barbara Chapman and Chunhua Liao
- Subjects
Distributed shared memory ,Multi-core processor ,Application programming interface ,Computer science ,Message passing ,Parallel computing ,Software_PROGRAMMINGTECHNIQUES ,computer.software_genre ,Computer architecture ,Shared memory ,Multithreading ,Compiler ,computer ,Compile time - Abstract
OpenMP has gained wide popularity as an API for parallel programming on shared memory and distributed shared memory platforms. It is also a promising candidate to exploit the emerging multicore, multithreaded processors. In addition, there is an increasing trend to combine OpenMP with MPI to take full advantage of mainstream supercomputers consisting of clustered SMPs. All of these require that attention be paid to the quality of the compiler's translation of OpenMP and the flexibility of runtime support. Many compilers and runtime libraries have an internal cost model that helps evaluate compiler transformations, guides adaptive runtime systems, and helps achieve load balancing. But existing models are not sufficient to support OpenMP, especially on new platforms. In this paper we present our experience adapting the cost models in OpenUH, a branch of Open64, to estimate the execution cycles of parallel OpenMP regions using knowledge of both software and hardware. Our OpenMP cost model reuses major components from Open64, along with extensions to consider more OpenMP details. Preliminary evaluations of the model are presented using kernel benchmarks. The challenges and possible extensions for modeling OpenMP on multicore platforms are also discussed.
- Published
- 2007
41. 2012 International Symposium on Computer Architecture Influential Paper Award
- Author
-
Josep Torrellas
- Subjects
ComputingMilieux_THECOMPUTINGPROFESSION ,Point (typography) ,Computer architecture ,Hardware and Architecture ,Computer science ,Electrical and Electronic Engineering ,GeneralLiterature_REFERENCE(e.g.,dictionaries,encyclopedias,glossaries) ,Column (database) ,ComputingMilieux_MISCELLANEOUS ,GeneralLiterature_MISCELLANEOUS ,Software - Abstract
This column discusses the winner of the 2012 International Symposium on Computer Architecture Influential Paper Award. It describes, from the point of view of the chair of the committee, what makes the paper influential.
- Published
- 2012
42. Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs
- Author
-
Jay Young, Brendan K. Bridgford, Brandon J. Blodget, Patrick Lysaght, and Jeffrey M. Mason
- Subjects
Computer science ,business.industry ,Industrial property ,Control reconfiguration ,Reconfigurable computing ,Computer architecture ,Cad tools ,Embedded system ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Field-programmable gate array ,Design methods ,business ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION ,Hardware_LOGICDESIGN - Abstract
The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinx's commercial CAD tools
- Published
- 2006
43. Architectures for Mobile Device Integration into Service-Oriented Architectures (short paper)
- Author
-
Markus Aleksy, Ingrid Duda, and Thomas Butter
- Subjects
Computer architecture ,business.industry ,Computer science ,Mobile station ,Embedded system ,Artificial intelligence systems integration ,Component-based software engineering ,Mobile computing ,Mobile search ,Mobile Web ,Mobile agent ,Mobile technology ,business - Abstract
The usage of mobile devices rose enormously. Their integration into complex interacting systems leads to new software architectures. This paper shows the general design considerations of service-oriented systems integrating mobile devices, together with its motivation. We identify a smaller granularity of design components - tasks for service invocation - and examine their distribution between mobile device and not mobile components of the software system.
- Published
- 2005
44. Extracting Information from Experimental Software Engineering Papers
- Author
-
Daniela Cruzes, Manoel Mendonca, Victor Basili, Forrest Shull, and Mario Jino
- Subjects
business.industry ,Computer science ,Porting ,Unified Modeling Language ,Computer architecture ,Formal specification ,Product (mathematics) ,Reference architecture ,Architecture ,Software architecture ,Space-based architecture ,Software engineering ,business ,computer ,computer.programming_language - Abstract
Designing a product line architecture can be approached from scratch or by deducing it after having built a series of similar products. We hereby present a different approach where we designed a product line architecture after only one product was built. Given MCC+, a product for consistency checking of different diagrams in a UML model, we identified the variabilities it should manage in order to be useful for a variety of modeling tools, obtaining a product line MCC-SPL. We accordingly upgraded the original architecture to a product line architecture (PLA). We verified how well the proposed PLA generalizes the single product architecture using a simple yet well known product line architecture assessment method. We also validated the usefulness of the just designed PLA by porting the tool to a different modeling platform.
- Published
- 2007
45. Session details: Distributed systems and grid computing (DSGC): poster paper
- Author
-
Robert van Engelen, Nectarios Koziris, Madhu Govindaraju, and Kleanthis Psarris
- Subjects
Grid computing ,Computer architecture ,Computer science ,Session (computer science) ,computer.software_genre ,computer - Published
- 2005
46. Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
- Author
-
Peter Athanas, Jürgen Becker, and René Cumplido
- Subjects
Virginia tech ,lcsh:Computer engineering. Computer hardware ,Article Subject ,Computer architecture ,Hardware and Architecture ,Computer science ,lcsh:TK7885-7895 ,Electronics ,Parallel computing ,Field-programmable gate array ,Reconfigurable computing - Abstract
1 Reconfigurable Computing Group, Computer Science Department, National Institute for Astrophysics, Optics and Electronics, 72840 Puebla, PUE, Mexico 2Department of Electrical and Computer Engineering, Virginia Tech Configurable Computing Laboratory, Blacksburg, VA 24061, USA 3 Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), 76131 Karlsruhe, Germany
- Published
- 2013
47. Methodology for hardware/software co-verification in C/C++ (short paper)
- Author
-
Abhijit Ghosh and Luc Séméria
- Subjects
Hardware architecture ,Computer architecture ,Computer science ,Design for testing ,Software construction ,Hardware compatibility list ,Software design ,System on a chip ,Software design description ,Register-transfer level - Published
- 2000
48. 16.1: Invited Paper: Development of TFT Process and Circuit Integration on the Flexible Substrate to Enhance Flexibility of the Display
- Author
-
Yong-In Park, Jong-Kwon Lee, Soo Young Yoon, In Byeong Kang, Juhn-Suk Yoo, In-Jae Chung, Sang-Hoon Jung, and Chang-Dong Kim
- Subjects
Flexibility (engineering) ,Engineering ,Backplane ,Computer architecture ,Thin-film transistor ,Process (engineering) ,Flexible display ,business.industry ,Key (cryptography) ,Electrical engineering ,Substrate (printing) ,Electronics ,business - Abstract
Flexible displays have been considered as one of the future displays. To make real flexible displays, there are several key technical issues, such as the robust backplane process on flexible substrates and removing rigid electronics. In this paper, we summarized on our recent technical approaches and results on these two issues.
- Published
- 2009
49. Best paper awards: 26th international parallel and distributed processing symposium (IPDPS 2012)
- Author
-
Leonid Oliker and Katherine Yelick
- Subjects
Computer architecture ,Artificial Intelligence ,Computer Networks and Communications ,Hardware and Architecture ,Computer science ,Software ,Theoretical Computer Science - Published
- 2013
50. Call for Papers: Nanoscale Integrated Photonics for Optical Networks
- Author
-
Keren Bergman and Madeleine Glick
- Subjects
Network architecture ,Computer science ,business.industry ,Network packet ,Computer Networks and Communications ,Subject (documents) ,Network interface ,Condensed Matter Physics ,Atomic and Molecular Physics, and Optics ,Computer Science Applications ,Network element ,Computer architecture ,Optical networking ,Electronics ,Photonics ,Electrical and Electronic Engineering ,Telecommunications ,business - Abstract
Call for Papers: Nanoscale Integrated Photonics for Optical Networks Keren Bergman, Coordinating Associate Editor Madeleine Glick, Guest Feature Editor Submission Deadline: 1 August 2006 Recent dramatic advances in nanoscale materials and nanophotonic device fabrication have yielded unprecedented control over the optical properties of synthetic structures. These extraordinary innovations at the nanoscale offer the possibility of creating high-functionality photonic devices in ultradense integration platforms. We can now envision nanoscale integrated photonics modules that may be application-specific designed in a similar fashion to integrated electronics for applications ranging from ultra-long-haul telecommunications to on-chip networks and high-performance computing. The applications of these advances to the transformation of optical networking is the theme of this Journal of Optical Networking (JON) feature issue. Scope of Submission The Editors of JON are soliciting papers on Nanoscale Integrated Photonics for Optical Networks. The aim in this feature issue is to publish original research on topics including--but not limited to--the following nanoscale materials and device fabrication as related to Novel optical network architectures Photonic switching fabrics and network elements Advances enabling new network functionalities such as novel solutions for optical buffering, packet or label processing, and routing modules Miniature mux/demux technology Application-specific design Integration and high-volume manufacture of photonics devices/modules Network interface and control planes Manuscript Submission To submit to this special issue, follow the normal procedure for submission to JON and select ``Integration' in the features indicator of the online submission form. For all other questions relating to this feature issue, please send an e-mail to jon@osa.org, subject line ``Integration.' Additional information can be found on the JON website: http://www.osa-jon.org/journal/jon/author.cfm. Submission Deadline: 1 August 2006
- Published
- 2006
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